vmwgfx_kms.c 48 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  72. bool show, int x, int y)
  73. {
  74. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  75. uint32_t count;
  76. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  77. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  78. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  79. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  80. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  81. }
  82. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  83. uint32_t handle, uint32_t width, uint32_t height)
  84. {
  85. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  86. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  87. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  88. struct vmw_surface *surface = NULL;
  89. struct vmw_dma_buffer *dmabuf = NULL;
  90. int ret;
  91. if (handle) {
  92. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  93. handle, &surface);
  94. if (!ret) {
  95. if (!surface->snooper.image) {
  96. DRM_ERROR("surface not suitable for cursor\n");
  97. return -EINVAL;
  98. }
  99. } else {
  100. ret = vmw_user_dmabuf_lookup(tfile,
  101. handle, &dmabuf);
  102. if (ret) {
  103. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  104. return -EINVAL;
  105. }
  106. }
  107. }
  108. /* takedown old cursor */
  109. if (du->cursor_surface) {
  110. du->cursor_surface->snooper.crtc = NULL;
  111. vmw_surface_unreference(&du->cursor_surface);
  112. }
  113. if (du->cursor_dmabuf)
  114. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  115. /* setup new image */
  116. if (surface) {
  117. /* vmw_user_surface_lookup takes one reference */
  118. du->cursor_surface = surface;
  119. du->cursor_surface->snooper.crtc = crtc;
  120. du->cursor_age = du->cursor_surface->snooper.age;
  121. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  122. 64, 64, du->hotspot_x, du->hotspot_y);
  123. } else if (dmabuf) {
  124. struct ttm_bo_kmap_obj map;
  125. unsigned long kmap_offset;
  126. unsigned long kmap_num;
  127. void *virtual;
  128. bool dummy;
  129. /* vmw_user_surface_lookup takes one reference */
  130. du->cursor_dmabuf = dmabuf;
  131. kmap_offset = 0;
  132. kmap_num = (64*64*4) >> PAGE_SHIFT;
  133. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  134. if (unlikely(ret != 0)) {
  135. DRM_ERROR("reserve failed\n");
  136. return -EINVAL;
  137. }
  138. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  139. if (unlikely(ret != 0))
  140. goto err_unreserve;
  141. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  142. vmw_cursor_update_image(dev_priv, virtual, 64, 64,
  143. du->hotspot_x, du->hotspot_y);
  144. ttm_bo_kunmap(&map);
  145. err_unreserve:
  146. ttm_bo_unreserve(&dmabuf->base);
  147. } else {
  148. vmw_cursor_update_position(dev_priv, false, 0, 0);
  149. return 0;
  150. }
  151. vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
  152. return 0;
  153. }
  154. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  155. {
  156. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  157. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  158. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  159. du->cursor_x = x + crtc->x;
  160. du->cursor_y = y + crtc->y;
  161. vmw_cursor_update_position(dev_priv, shown,
  162. du->cursor_x, du->cursor_y);
  163. return 0;
  164. }
  165. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  166. struct ttm_object_file *tfile,
  167. struct ttm_buffer_object *bo,
  168. SVGA3dCmdHeader *header)
  169. {
  170. struct ttm_bo_kmap_obj map;
  171. unsigned long kmap_offset;
  172. unsigned long kmap_num;
  173. SVGA3dCopyBox *box;
  174. unsigned box_count;
  175. void *virtual;
  176. bool dummy;
  177. struct vmw_dma_cmd {
  178. SVGA3dCmdHeader header;
  179. SVGA3dCmdSurfaceDMA dma;
  180. } *cmd;
  181. int ret;
  182. cmd = container_of(header, struct vmw_dma_cmd, header);
  183. /* No snooper installed */
  184. if (!srf->snooper.image)
  185. return;
  186. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  187. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  188. return;
  189. }
  190. if (cmd->header.size < 64) {
  191. DRM_ERROR("at least one full copy box must be given\n");
  192. return;
  193. }
  194. box = (SVGA3dCopyBox *)&cmd[1];
  195. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  196. sizeof(SVGA3dCopyBox);
  197. if (cmd->dma.guest.pitch != (64 * 4) ||
  198. cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  199. box->x != 0 || box->y != 0 || box->z != 0 ||
  200. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  201. box->w != 64 || box->h != 64 || box->d != 1 ||
  202. box_count != 1) {
  203. /* TODO handle none page aligned offsets */
  204. /* TODO handle partial uploads and pitch != 256 */
  205. /* TODO handle more then one copy (size != 64) */
  206. DRM_ERROR("lazy programmer, can't handle weird stuff\n");
  207. return;
  208. }
  209. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  210. kmap_num = (64*64*4) >> PAGE_SHIFT;
  211. ret = ttm_bo_reserve(bo, true, false, false, 0);
  212. if (unlikely(ret != 0)) {
  213. DRM_ERROR("reserve failed\n");
  214. return;
  215. }
  216. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  217. if (unlikely(ret != 0))
  218. goto err_unreserve;
  219. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  220. memcpy(srf->snooper.image, virtual, 64*64*4);
  221. srf->snooper.age++;
  222. /* we can't call this function from this function since execbuf has
  223. * reserved fifo space.
  224. *
  225. * if (srf->snooper.crtc)
  226. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  227. * srf->snooper.image, 64, 64,
  228. * du->hotspot_x, du->hotspot_y);
  229. */
  230. ttm_bo_kunmap(&map);
  231. err_unreserve:
  232. ttm_bo_unreserve(bo);
  233. }
  234. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  235. {
  236. struct drm_device *dev = dev_priv->dev;
  237. struct vmw_display_unit *du;
  238. struct drm_crtc *crtc;
  239. mutex_lock(&dev->mode_config.mutex);
  240. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  241. du = vmw_crtc_to_du(crtc);
  242. if (!du->cursor_surface ||
  243. du->cursor_age == du->cursor_surface->snooper.age)
  244. continue;
  245. du->cursor_age = du->cursor_surface->snooper.age;
  246. vmw_cursor_update_image(dev_priv,
  247. du->cursor_surface->snooper.image,
  248. 64, 64, du->hotspot_x, du->hotspot_y);
  249. }
  250. mutex_unlock(&dev->mode_config.mutex);
  251. }
  252. /*
  253. * Generic framebuffer code
  254. */
  255. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  256. struct drm_file *file_priv,
  257. unsigned int *handle)
  258. {
  259. if (handle)
  260. handle = 0;
  261. return 0;
  262. }
  263. /*
  264. * Surface framebuffer code
  265. */
  266. #define vmw_framebuffer_to_vfbs(x) \
  267. container_of(x, struct vmw_framebuffer_surface, base.base)
  268. struct vmw_framebuffer_surface {
  269. struct vmw_framebuffer base;
  270. struct vmw_surface *surface;
  271. struct vmw_dma_buffer *buffer;
  272. struct list_head head;
  273. struct drm_master *master;
  274. };
  275. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  276. {
  277. struct vmw_framebuffer_surface *vfbs =
  278. vmw_framebuffer_to_vfbs(framebuffer);
  279. struct vmw_master *vmaster = vmw_master(vfbs->master);
  280. mutex_lock(&vmaster->fb_surf_mutex);
  281. list_del(&vfbs->head);
  282. mutex_unlock(&vmaster->fb_surf_mutex);
  283. drm_master_put(&vfbs->master);
  284. drm_framebuffer_cleanup(framebuffer);
  285. vmw_surface_unreference(&vfbs->surface);
  286. ttm_base_object_unref(&vfbs->base.user_obj);
  287. kfree(vfbs);
  288. }
  289. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  290. struct drm_file *file_priv,
  291. struct vmw_framebuffer *framebuffer,
  292. unsigned flags, unsigned color,
  293. struct drm_clip_rect *clips,
  294. unsigned num_clips, int inc)
  295. {
  296. struct drm_clip_rect *clips_ptr;
  297. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  298. struct drm_crtc *crtc;
  299. size_t fifo_size;
  300. int i, num_units;
  301. int ret = 0; /* silence warning */
  302. int left, right, top, bottom;
  303. struct {
  304. SVGA3dCmdHeader header;
  305. SVGA3dCmdBlitSurfaceToScreen body;
  306. } *cmd;
  307. SVGASignedRect *blits;
  308. num_units = 0;
  309. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  310. head) {
  311. if (crtc->fb != &framebuffer->base)
  312. continue;
  313. units[num_units++] = vmw_crtc_to_du(crtc);
  314. }
  315. BUG_ON(!clips || !num_clips);
  316. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  317. cmd = kzalloc(fifo_size, GFP_KERNEL);
  318. if (unlikely(cmd == NULL)) {
  319. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  320. return -ENOMEM;
  321. }
  322. left = clips->x1;
  323. right = clips->x2;
  324. top = clips->y1;
  325. bottom = clips->y2;
  326. clips_ptr = clips;
  327. for (i = 1; i < num_clips; i++, clips_ptr += inc) {
  328. left = min_t(int, left, (int)clips_ptr->x1);
  329. right = max_t(int, right, (int)clips_ptr->x2);
  330. top = min_t(int, top, (int)clips_ptr->y1);
  331. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  332. }
  333. /* only need to do this once */
  334. memset(cmd, 0, fifo_size);
  335. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  336. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  337. cmd->body.srcRect.left = left;
  338. cmd->body.srcRect.right = right;
  339. cmd->body.srcRect.top = top;
  340. cmd->body.srcRect.bottom = bottom;
  341. clips_ptr = clips;
  342. blits = (SVGASignedRect *)&cmd[1];
  343. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  344. blits[i].left = clips_ptr->x1 - left;
  345. blits[i].right = clips_ptr->x2 - left;
  346. blits[i].top = clips_ptr->y1 - top;
  347. blits[i].bottom = clips_ptr->y2 - top;
  348. }
  349. /* do per unit writing, reuse fifo for each */
  350. for (i = 0; i < num_units; i++) {
  351. struct vmw_display_unit *unit = units[i];
  352. int clip_x1 = left - unit->crtc.x;
  353. int clip_y1 = top - unit->crtc.y;
  354. int clip_x2 = right - unit->crtc.x;
  355. int clip_y2 = bottom - unit->crtc.y;
  356. /* skip any crtcs that misses the clip region */
  357. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  358. clip_y1 >= unit->crtc.mode.vdisplay ||
  359. clip_x2 <= 0 || clip_y2 <= 0)
  360. continue;
  361. /* need to reset sid as it is changed by execbuf */
  362. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  363. cmd->body.destScreenId = unit->unit;
  364. /*
  365. * The blit command is a lot more resilient then the
  366. * readback command when it comes to clip rects. So its
  367. * okay to go out of bounds.
  368. */
  369. cmd->body.destRect.left = clip_x1;
  370. cmd->body.destRect.right = clip_x2;
  371. cmd->body.destRect.top = clip_y1;
  372. cmd->body.destRect.bottom = clip_y2;
  373. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  374. fifo_size, 0, NULL);
  375. if (unlikely(ret != 0))
  376. break;
  377. }
  378. kfree(cmd);
  379. return ret;
  380. }
  381. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  382. struct drm_file *file_priv,
  383. unsigned flags, unsigned color,
  384. struct drm_clip_rect *clips,
  385. unsigned num_clips)
  386. {
  387. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  388. struct vmw_master *vmaster = vmw_master(file_priv->master);
  389. struct vmw_framebuffer_surface *vfbs =
  390. vmw_framebuffer_to_vfbs(framebuffer);
  391. struct drm_clip_rect norect;
  392. int ret, inc = 1;
  393. if (unlikely(vfbs->master != file_priv->master))
  394. return -EINVAL;
  395. /* Require ScreenObject support for 3D */
  396. if (!dev_priv->sou_priv)
  397. return -EINVAL;
  398. ret = ttm_read_lock(&vmaster->lock, true);
  399. if (unlikely(ret != 0))
  400. return ret;
  401. if (!num_clips) {
  402. num_clips = 1;
  403. clips = &norect;
  404. norect.x1 = norect.y1 = 0;
  405. norect.x2 = framebuffer->width;
  406. norect.y2 = framebuffer->height;
  407. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  408. num_clips /= 2;
  409. inc = 2; /* skip source rects */
  410. }
  411. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  412. flags, color,
  413. clips, num_clips, inc);
  414. ttm_read_unlock(&vmaster->lock);
  415. return 0;
  416. }
  417. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  418. .destroy = vmw_framebuffer_surface_destroy,
  419. .dirty = vmw_framebuffer_surface_dirty,
  420. .create_handle = vmw_framebuffer_create_handle,
  421. };
  422. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  423. struct drm_file *file_priv,
  424. struct vmw_surface *surface,
  425. struct vmw_framebuffer **out,
  426. const struct drm_mode_fb_cmd
  427. *mode_cmd)
  428. {
  429. struct drm_device *dev = dev_priv->dev;
  430. struct vmw_framebuffer_surface *vfbs;
  431. enum SVGA3dSurfaceFormat format;
  432. struct vmw_master *vmaster = vmw_master(file_priv->master);
  433. int ret;
  434. /* 3D is only supported on HWv8 hosts which supports screen objects */
  435. if (!dev_priv->sou_priv)
  436. return -ENOSYS;
  437. /*
  438. * Sanity checks.
  439. */
  440. if (unlikely(surface->mip_levels[0] != 1 ||
  441. surface->num_sizes != 1 ||
  442. surface->sizes[0].width < mode_cmd->width ||
  443. surface->sizes[0].height < mode_cmd->height ||
  444. surface->sizes[0].depth != 1)) {
  445. DRM_ERROR("Incompatible surface dimensions "
  446. "for requested mode.\n");
  447. return -EINVAL;
  448. }
  449. switch (mode_cmd->depth) {
  450. case 32:
  451. format = SVGA3D_A8R8G8B8;
  452. break;
  453. case 24:
  454. format = SVGA3D_X8R8G8B8;
  455. break;
  456. case 16:
  457. format = SVGA3D_R5G6B5;
  458. break;
  459. case 15:
  460. format = SVGA3D_A1R5G5B5;
  461. break;
  462. case 8:
  463. format = SVGA3D_LUMINANCE8;
  464. break;
  465. default:
  466. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  467. return -EINVAL;
  468. }
  469. if (unlikely(format != surface->format)) {
  470. DRM_ERROR("Invalid surface format for requested mode.\n");
  471. return -EINVAL;
  472. }
  473. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  474. if (!vfbs) {
  475. ret = -ENOMEM;
  476. goto out_err1;
  477. }
  478. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  479. &vmw_framebuffer_surface_funcs);
  480. if (ret)
  481. goto out_err2;
  482. if (!vmw_surface_reference(surface)) {
  483. DRM_ERROR("failed to reference surface %p\n", surface);
  484. goto out_err3;
  485. }
  486. /* XXX get the first 3 from the surface info */
  487. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  488. vfbs->base.base.pitch = mode_cmd->pitch;
  489. vfbs->base.base.depth = mode_cmd->depth;
  490. vfbs->base.base.width = mode_cmd->width;
  491. vfbs->base.base.height = mode_cmd->height;
  492. vfbs->surface = surface;
  493. vfbs->base.user_handle = mode_cmd->handle;
  494. vfbs->master = drm_master_get(file_priv->master);
  495. mutex_lock(&vmaster->fb_surf_mutex);
  496. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  497. mutex_unlock(&vmaster->fb_surf_mutex);
  498. *out = &vfbs->base;
  499. return 0;
  500. out_err3:
  501. drm_framebuffer_cleanup(&vfbs->base.base);
  502. out_err2:
  503. kfree(vfbs);
  504. out_err1:
  505. return ret;
  506. }
  507. /*
  508. * Dmabuf framebuffer code
  509. */
  510. #define vmw_framebuffer_to_vfbd(x) \
  511. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  512. struct vmw_framebuffer_dmabuf {
  513. struct vmw_framebuffer base;
  514. struct vmw_dma_buffer *buffer;
  515. };
  516. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  517. {
  518. struct vmw_framebuffer_dmabuf *vfbd =
  519. vmw_framebuffer_to_vfbd(framebuffer);
  520. drm_framebuffer_cleanup(framebuffer);
  521. vmw_dmabuf_unreference(&vfbd->buffer);
  522. ttm_base_object_unref(&vfbd->base.user_obj);
  523. kfree(vfbd);
  524. }
  525. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  526. struct vmw_framebuffer *framebuffer,
  527. unsigned flags, unsigned color,
  528. struct drm_clip_rect *clips,
  529. unsigned num_clips, int increment)
  530. {
  531. size_t fifo_size;
  532. int i;
  533. struct {
  534. uint32_t header;
  535. SVGAFifoCmdUpdate body;
  536. } *cmd;
  537. fifo_size = sizeof(*cmd) * num_clips;
  538. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  539. if (unlikely(cmd == NULL)) {
  540. DRM_ERROR("Fifo reserve failed.\n");
  541. return -ENOMEM;
  542. }
  543. memset(cmd, 0, fifo_size);
  544. for (i = 0; i < num_clips; i++, clips += increment) {
  545. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  546. cmd[i].body.x = cpu_to_le32(clips->x1);
  547. cmd[i].body.y = cpu_to_le32(clips->y1);
  548. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  549. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  550. }
  551. vmw_fifo_commit(dev_priv, fifo_size);
  552. return 0;
  553. }
  554. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  555. struct vmw_private *dev_priv,
  556. struct vmw_framebuffer *framebuffer)
  557. {
  558. int depth = framebuffer->base.depth;
  559. size_t fifo_size;
  560. int ret;
  561. struct {
  562. uint32_t header;
  563. SVGAFifoCmdDefineGMRFB body;
  564. } *cmd;
  565. /* Emulate RGBA support, contrary to svga_reg.h this is not
  566. * supported by hosts. This is only a problem if we are reading
  567. * this value later and expecting what we uploaded back.
  568. */
  569. if (depth == 32)
  570. depth = 24;
  571. fifo_size = sizeof(*cmd);
  572. cmd = kmalloc(fifo_size, GFP_KERNEL);
  573. if (unlikely(cmd == NULL)) {
  574. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  575. return -ENOMEM;
  576. }
  577. memset(cmd, 0, fifo_size);
  578. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  579. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  580. cmd->body.format.colorDepth = depth;
  581. cmd->body.format.reserved = 0;
  582. cmd->body.bytesPerLine = framebuffer->base.pitch;
  583. cmd->body.ptr.gmrId = framebuffer->user_handle;
  584. cmd->body.ptr.offset = 0;
  585. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  586. fifo_size, 0, NULL);
  587. kfree(cmd);
  588. return ret;
  589. }
  590. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  591. struct vmw_private *dev_priv,
  592. struct vmw_framebuffer *framebuffer,
  593. unsigned flags, unsigned color,
  594. struct drm_clip_rect *clips,
  595. unsigned num_clips, int increment)
  596. {
  597. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  598. struct drm_clip_rect *clips_ptr;
  599. int i, k, num_units, ret;
  600. struct drm_crtc *crtc;
  601. size_t fifo_size;
  602. struct {
  603. uint32_t header;
  604. SVGAFifoCmdBlitGMRFBToScreen body;
  605. } *blits;
  606. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  607. if (unlikely(ret != 0))
  608. return ret; /* define_gmrfb prints warnings */
  609. fifo_size = sizeof(*blits) * num_clips;
  610. blits = kmalloc(fifo_size, GFP_KERNEL);
  611. if (unlikely(blits == NULL)) {
  612. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  613. return -ENOMEM;
  614. }
  615. num_units = 0;
  616. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  617. if (crtc->fb != &framebuffer->base)
  618. continue;
  619. units[num_units++] = vmw_crtc_to_du(crtc);
  620. }
  621. for (k = 0; k < num_units; k++) {
  622. struct vmw_display_unit *unit = units[k];
  623. int hit_num = 0;
  624. clips_ptr = clips;
  625. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  626. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  627. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  628. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  629. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  630. /* skip any crtcs that misses the clip region */
  631. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  632. clip_y1 >= unit->crtc.mode.vdisplay ||
  633. clip_x2 <= 0 || clip_y2 <= 0)
  634. continue;
  635. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  636. blits[hit_num].body.destScreenId = unit->unit;
  637. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  638. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  639. blits[hit_num].body.destRect.left = clip_x1;
  640. blits[hit_num].body.destRect.top = clip_y1;
  641. blits[hit_num].body.destRect.right = clip_x2;
  642. blits[hit_num].body.destRect.bottom = clip_y2;
  643. hit_num++;
  644. }
  645. /* no clips hit the crtc */
  646. if (hit_num == 0)
  647. continue;
  648. fifo_size = sizeof(*blits) * hit_num;
  649. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  650. fifo_size, 0, NULL);
  651. if (unlikely(ret != 0))
  652. break;
  653. }
  654. kfree(blits);
  655. return ret;
  656. }
  657. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  658. struct drm_file *file_priv,
  659. unsigned flags, unsigned color,
  660. struct drm_clip_rect *clips,
  661. unsigned num_clips)
  662. {
  663. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  664. struct vmw_master *vmaster = vmw_master(file_priv->master);
  665. struct vmw_framebuffer_dmabuf *vfbd =
  666. vmw_framebuffer_to_vfbd(framebuffer);
  667. struct drm_clip_rect norect;
  668. int ret, increment = 1;
  669. ret = ttm_read_lock(&vmaster->lock, true);
  670. if (unlikely(ret != 0))
  671. return ret;
  672. if (!num_clips) {
  673. num_clips = 1;
  674. clips = &norect;
  675. norect.x1 = norect.y1 = 0;
  676. norect.x2 = framebuffer->width;
  677. norect.y2 = framebuffer->height;
  678. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  679. num_clips /= 2;
  680. increment = 2;
  681. }
  682. if (dev_priv->ldu_priv) {
  683. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  684. flags, color,
  685. clips, num_clips, increment);
  686. } else {
  687. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  688. flags, color,
  689. clips, num_clips, increment);
  690. }
  691. ttm_read_unlock(&vmaster->lock);
  692. return ret;
  693. }
  694. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  695. .destroy = vmw_framebuffer_dmabuf_destroy,
  696. .dirty = vmw_framebuffer_dmabuf_dirty,
  697. .create_handle = vmw_framebuffer_create_handle,
  698. };
  699. /**
  700. * Pin the dmabuffer to the start of vram.
  701. */
  702. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  703. {
  704. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  705. struct vmw_framebuffer_dmabuf *vfbd =
  706. vmw_framebuffer_to_vfbd(&vfb->base);
  707. int ret;
  708. /* This code should not be used with screen objects */
  709. BUG_ON(dev_priv->sou_priv);
  710. vmw_overlay_pause_all(dev_priv);
  711. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  712. vmw_overlay_resume_all(dev_priv);
  713. WARN_ON(ret != 0);
  714. return 0;
  715. }
  716. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  717. {
  718. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  719. struct vmw_framebuffer_dmabuf *vfbd =
  720. vmw_framebuffer_to_vfbd(&vfb->base);
  721. if (!vfbd->buffer) {
  722. WARN_ON(!vfbd->buffer);
  723. return 0;
  724. }
  725. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  726. }
  727. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  728. struct vmw_dma_buffer *dmabuf,
  729. struct vmw_framebuffer **out,
  730. const struct drm_mode_fb_cmd
  731. *mode_cmd)
  732. {
  733. struct drm_device *dev = dev_priv->dev;
  734. struct vmw_framebuffer_dmabuf *vfbd;
  735. unsigned int requested_size;
  736. int ret;
  737. requested_size = mode_cmd->height * mode_cmd->pitch;
  738. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  739. DRM_ERROR("Screen buffer object size is too small "
  740. "for requested mode.\n");
  741. return -EINVAL;
  742. }
  743. /* Limited framebuffer color depth support for screen objects */
  744. if (dev_priv->sou_priv) {
  745. switch (mode_cmd->depth) {
  746. case 32:
  747. case 24:
  748. /* Only support 32 bpp for 32 and 24 depth fbs */
  749. if (mode_cmd->bpp == 32)
  750. break;
  751. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  752. mode_cmd->depth, mode_cmd->bpp);
  753. return -EINVAL;
  754. case 16:
  755. case 15:
  756. /* Only support 16 bpp for 16 and 15 depth fbs */
  757. if (mode_cmd->bpp == 16)
  758. break;
  759. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  760. mode_cmd->depth, mode_cmd->bpp);
  761. return -EINVAL;
  762. default:
  763. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  764. return -EINVAL;
  765. }
  766. }
  767. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  768. if (!vfbd) {
  769. ret = -ENOMEM;
  770. goto out_err1;
  771. }
  772. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  773. &vmw_framebuffer_dmabuf_funcs);
  774. if (ret)
  775. goto out_err2;
  776. if (!vmw_dmabuf_reference(dmabuf)) {
  777. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  778. goto out_err3;
  779. }
  780. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  781. vfbd->base.base.pitch = mode_cmd->pitch;
  782. vfbd->base.base.depth = mode_cmd->depth;
  783. vfbd->base.base.width = mode_cmd->width;
  784. vfbd->base.base.height = mode_cmd->height;
  785. if (!dev_priv->sou_priv) {
  786. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  787. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  788. }
  789. vfbd->base.dmabuf = true;
  790. vfbd->buffer = dmabuf;
  791. vfbd->base.user_handle = mode_cmd->handle;
  792. *out = &vfbd->base;
  793. return 0;
  794. out_err3:
  795. drm_framebuffer_cleanup(&vfbd->base.base);
  796. out_err2:
  797. kfree(vfbd);
  798. out_err1:
  799. return ret;
  800. }
  801. /*
  802. * Generic Kernel modesetting functions
  803. */
  804. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  805. struct drm_file *file_priv,
  806. struct drm_mode_fb_cmd *mode_cmd)
  807. {
  808. struct vmw_private *dev_priv = vmw_priv(dev);
  809. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  810. struct vmw_framebuffer *vfb = NULL;
  811. struct vmw_surface *surface = NULL;
  812. struct vmw_dma_buffer *bo = NULL;
  813. struct ttm_base_object *user_obj;
  814. u64 required_size;
  815. int ret;
  816. /**
  817. * This code should be conditioned on Screen Objects not being used.
  818. * If screen objects are used, we can allocate a GMR to hold the
  819. * requested framebuffer.
  820. */
  821. required_size = mode_cmd->pitch * mode_cmd->height;
  822. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  823. DRM_ERROR("VRAM size is too small for requested mode.\n");
  824. return NULL;
  825. }
  826. /*
  827. * Take a reference on the user object of the resource
  828. * backing the kms fb. This ensures that user-space handle
  829. * lookups on that resource will always work as long as
  830. * it's registered with a kms framebuffer. This is important,
  831. * since vmw_execbuf_process identifies resources in the
  832. * command stream using user-space handles.
  833. */
  834. user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
  835. if (unlikely(user_obj == NULL)) {
  836. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  837. return ERR_PTR(-ENOENT);
  838. }
  839. /**
  840. * End conditioned code.
  841. */
  842. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  843. mode_cmd->handle, &surface);
  844. if (ret)
  845. goto try_dmabuf;
  846. if (!surface->scanout)
  847. goto err_not_scanout;
  848. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  849. &vfb, mode_cmd);
  850. /* vmw_user_surface_lookup takes one ref so does new_fb */
  851. vmw_surface_unreference(&surface);
  852. if (ret) {
  853. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  854. ttm_base_object_unref(&user_obj);
  855. return ERR_PTR(ret);
  856. } else
  857. vfb->user_obj = user_obj;
  858. return &vfb->base;
  859. try_dmabuf:
  860. DRM_INFO("%s: trying buffer\n", __func__);
  861. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
  862. if (ret) {
  863. DRM_ERROR("failed to find buffer: %i\n", ret);
  864. return ERR_PTR(-ENOENT);
  865. }
  866. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  867. mode_cmd);
  868. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  869. vmw_dmabuf_unreference(&bo);
  870. if (ret) {
  871. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  872. ttm_base_object_unref(&user_obj);
  873. return ERR_PTR(ret);
  874. } else
  875. vfb->user_obj = user_obj;
  876. return &vfb->base;
  877. err_not_scanout:
  878. DRM_ERROR("surface not marked as scanout\n");
  879. /* vmw_user_surface_lookup takes one ref */
  880. vmw_surface_unreference(&surface);
  881. ttm_base_object_unref(&user_obj);
  882. return ERR_PTR(-EINVAL);
  883. }
  884. static struct drm_mode_config_funcs vmw_kms_funcs = {
  885. .fb_create = vmw_kms_fb_create,
  886. };
  887. int vmw_kms_present(struct vmw_private *dev_priv,
  888. struct drm_file *file_priv,
  889. struct vmw_framebuffer *vfb,
  890. struct vmw_surface *surface,
  891. uint32_t sid,
  892. int32_t destX, int32_t destY,
  893. struct drm_vmw_rect *clips,
  894. uint32_t num_clips)
  895. {
  896. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  897. struct drm_crtc *crtc;
  898. size_t fifo_size;
  899. int i, k, num_units;
  900. int ret = 0; /* silence warning */
  901. struct {
  902. SVGA3dCmdHeader header;
  903. SVGA3dCmdBlitSurfaceToScreen body;
  904. } *cmd;
  905. SVGASignedRect *blits;
  906. num_units = 0;
  907. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  908. if (crtc->fb != &vfb->base)
  909. continue;
  910. units[num_units++] = vmw_crtc_to_du(crtc);
  911. }
  912. BUG_ON(surface == NULL);
  913. BUG_ON(!clips || !num_clips);
  914. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  915. cmd = kmalloc(fifo_size, GFP_KERNEL);
  916. if (unlikely(cmd == NULL)) {
  917. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  918. return -ENOMEM;
  919. }
  920. /* only need to do this once */
  921. memset(cmd, 0, fifo_size);
  922. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  923. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  924. cmd->body.srcRect.left = 0;
  925. cmd->body.srcRect.right = surface->sizes[0].width;
  926. cmd->body.srcRect.top = 0;
  927. cmd->body.srcRect.bottom = surface->sizes[0].height;
  928. blits = (SVGASignedRect *)&cmd[1];
  929. for (i = 0; i < num_clips; i++) {
  930. blits[i].left = clips[i].x;
  931. blits[i].right = clips[i].x + clips[i].w;
  932. blits[i].top = clips[i].y;
  933. blits[i].bottom = clips[i].y + clips[i].h;
  934. }
  935. for (k = 0; k < num_units; k++) {
  936. struct vmw_display_unit *unit = units[k];
  937. int clip_x1 = destX - unit->crtc.x;
  938. int clip_y1 = destY - unit->crtc.y;
  939. int clip_x2 = clip_x1 + surface->sizes[0].width;
  940. int clip_y2 = clip_y1 + surface->sizes[0].height;
  941. /* skip any crtcs that misses the clip region */
  942. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  943. clip_y1 >= unit->crtc.mode.vdisplay ||
  944. clip_x2 <= 0 || clip_y2 <= 0)
  945. continue;
  946. /* need to reset sid as it is changed by execbuf */
  947. cmd->body.srcImage.sid = sid;
  948. cmd->body.destScreenId = unit->unit;
  949. /*
  950. * The blit command is a lot more resilient then the
  951. * readback command when it comes to clip rects. So its
  952. * okay to go out of bounds.
  953. */
  954. cmd->body.destRect.left = clip_x1;
  955. cmd->body.destRect.right = clip_x2;
  956. cmd->body.destRect.top = clip_y1;
  957. cmd->body.destRect.bottom = clip_y2;
  958. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  959. fifo_size, 0, NULL);
  960. if (unlikely(ret != 0))
  961. break;
  962. }
  963. kfree(cmd);
  964. return ret;
  965. }
  966. int vmw_kms_readback(struct vmw_private *dev_priv,
  967. struct drm_file *file_priv,
  968. struct vmw_framebuffer *vfb,
  969. struct drm_vmw_fence_rep __user *user_fence_rep,
  970. struct drm_vmw_rect *clips,
  971. uint32_t num_clips)
  972. {
  973. struct vmw_framebuffer_dmabuf *vfbd =
  974. vmw_framebuffer_to_vfbd(&vfb->base);
  975. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  976. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  977. struct drm_crtc *crtc;
  978. size_t fifo_size;
  979. int i, k, ret, num_units, blits_pos;
  980. struct {
  981. uint32_t header;
  982. SVGAFifoCmdDefineGMRFB body;
  983. } *cmd;
  984. struct {
  985. uint32_t header;
  986. SVGAFifoCmdBlitScreenToGMRFB body;
  987. } *blits;
  988. num_units = 0;
  989. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  990. if (crtc->fb != &vfb->base)
  991. continue;
  992. units[num_units++] = vmw_crtc_to_du(crtc);
  993. }
  994. BUG_ON(dmabuf == NULL);
  995. BUG_ON(!clips || !num_clips);
  996. /* take a safe guess at fifo size */
  997. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  998. cmd = kmalloc(fifo_size, GFP_KERNEL);
  999. if (unlikely(cmd == NULL)) {
  1000. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1001. return -ENOMEM;
  1002. }
  1003. memset(cmd, 0, fifo_size);
  1004. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1005. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1006. cmd->body.format.colorDepth = vfb->base.depth;
  1007. cmd->body.format.reserved = 0;
  1008. cmd->body.bytesPerLine = vfb->base.pitch;
  1009. cmd->body.ptr.gmrId = vfb->user_handle;
  1010. cmd->body.ptr.offset = 0;
  1011. blits = (void *)&cmd[1];
  1012. blits_pos = 0;
  1013. for (i = 0; i < num_units; i++) {
  1014. struct drm_vmw_rect *c = clips;
  1015. for (k = 0; k < num_clips; k++, c++) {
  1016. /* transform clip coords to crtc origin based coords */
  1017. int clip_x1 = c->x - units[i]->crtc.x;
  1018. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1019. int clip_y1 = c->y - units[i]->crtc.y;
  1020. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1021. int dest_x = c->x;
  1022. int dest_y = c->y;
  1023. /* compensate for clipping, we negate
  1024. * a negative number and add that.
  1025. */
  1026. if (clip_x1 < 0)
  1027. dest_x += -clip_x1;
  1028. if (clip_y1 < 0)
  1029. dest_y += -clip_y1;
  1030. /* clip */
  1031. clip_x1 = max(clip_x1, 0);
  1032. clip_y1 = max(clip_y1, 0);
  1033. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1034. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1035. /* and cull any rects that misses the crtc */
  1036. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1037. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1038. clip_x2 <= 0 || clip_y2 <= 0)
  1039. continue;
  1040. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1041. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1042. blits[blits_pos].body.destOrigin.x = dest_x;
  1043. blits[blits_pos].body.destOrigin.y = dest_y;
  1044. blits[blits_pos].body.srcRect.left = clip_x1;
  1045. blits[blits_pos].body.srcRect.top = clip_y1;
  1046. blits[blits_pos].body.srcRect.right = clip_x2;
  1047. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1048. blits_pos++;
  1049. }
  1050. }
  1051. /* reset size here and use calculated exact size from loops */
  1052. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1053. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1054. 0, user_fence_rep);
  1055. kfree(cmd);
  1056. return ret;
  1057. }
  1058. int vmw_kms_init(struct vmw_private *dev_priv)
  1059. {
  1060. struct drm_device *dev = dev_priv->dev;
  1061. int ret;
  1062. drm_mode_config_init(dev);
  1063. dev->mode_config.funcs = &vmw_kms_funcs;
  1064. dev->mode_config.min_width = 1;
  1065. dev->mode_config.min_height = 1;
  1066. /* assumed largest fb size */
  1067. dev->mode_config.max_width = 8192;
  1068. dev->mode_config.max_height = 8192;
  1069. ret = vmw_kms_init_screen_object_display(dev_priv);
  1070. if (ret) /* Fallback */
  1071. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1072. return 0;
  1073. }
  1074. int vmw_kms_close(struct vmw_private *dev_priv)
  1075. {
  1076. /*
  1077. * Docs says we should take the lock before calling this function
  1078. * but since it destroys encoders and our destructor calls
  1079. * drm_encoder_cleanup which takes the lock we deadlock.
  1080. */
  1081. drm_mode_config_cleanup(dev_priv->dev);
  1082. vmw_kms_close_legacy_display_system(dev_priv);
  1083. return 0;
  1084. }
  1085. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1086. struct drm_file *file_priv)
  1087. {
  1088. struct drm_vmw_cursor_bypass_arg *arg = data;
  1089. struct vmw_display_unit *du;
  1090. struct drm_mode_object *obj;
  1091. struct drm_crtc *crtc;
  1092. int ret = 0;
  1093. mutex_lock(&dev->mode_config.mutex);
  1094. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1095. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1096. du = vmw_crtc_to_du(crtc);
  1097. du->hotspot_x = arg->xhot;
  1098. du->hotspot_y = arg->yhot;
  1099. }
  1100. mutex_unlock(&dev->mode_config.mutex);
  1101. return 0;
  1102. }
  1103. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1104. if (!obj) {
  1105. ret = -EINVAL;
  1106. goto out;
  1107. }
  1108. crtc = obj_to_crtc(obj);
  1109. du = vmw_crtc_to_du(crtc);
  1110. du->hotspot_x = arg->xhot;
  1111. du->hotspot_y = arg->yhot;
  1112. out:
  1113. mutex_unlock(&dev->mode_config.mutex);
  1114. return ret;
  1115. }
  1116. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1117. unsigned width, unsigned height, unsigned pitch,
  1118. unsigned bpp, unsigned depth)
  1119. {
  1120. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1121. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1122. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1123. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1124. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1125. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1126. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1127. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1128. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1129. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1130. return -EINVAL;
  1131. }
  1132. return 0;
  1133. }
  1134. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1135. {
  1136. struct vmw_vga_topology_state *save;
  1137. uint32_t i;
  1138. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1139. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1140. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1141. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1142. vmw_priv->vga_pitchlock =
  1143. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1144. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1145. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1146. SVGA_FIFO_PITCHLOCK);
  1147. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1148. return 0;
  1149. vmw_priv->num_displays = vmw_read(vmw_priv,
  1150. SVGA_REG_NUM_GUEST_DISPLAYS);
  1151. if (vmw_priv->num_displays == 0)
  1152. vmw_priv->num_displays = 1;
  1153. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1154. save = &vmw_priv->vga_save[i];
  1155. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1156. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1157. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1158. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1159. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1160. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1161. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1162. if (i == 0 && vmw_priv->num_displays == 1 &&
  1163. save->width == 0 && save->height == 0) {
  1164. /*
  1165. * It should be fairly safe to assume that these
  1166. * values are uninitialized.
  1167. */
  1168. save->width = vmw_priv->vga_width - save->pos_x;
  1169. save->height = vmw_priv->vga_height - save->pos_y;
  1170. }
  1171. }
  1172. return 0;
  1173. }
  1174. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1175. {
  1176. struct vmw_vga_topology_state *save;
  1177. uint32_t i;
  1178. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1179. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1180. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1181. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1182. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1183. vmw_priv->vga_pitchlock);
  1184. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1185. iowrite32(vmw_priv->vga_pitchlock,
  1186. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1187. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1188. return 0;
  1189. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1190. save = &vmw_priv->vga_save[i];
  1191. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1192. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1193. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1194. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1195. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1196. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1197. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1198. }
  1199. return 0;
  1200. }
  1201. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1202. uint32_t pitch,
  1203. uint32_t height)
  1204. {
  1205. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1206. }
  1207. /**
  1208. * Function called by DRM code called with vbl_lock held.
  1209. */
  1210. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1211. {
  1212. return 0;
  1213. }
  1214. /**
  1215. * Function called by DRM code called with vbl_lock held.
  1216. */
  1217. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1218. {
  1219. return -ENOSYS;
  1220. }
  1221. /**
  1222. * Function called by DRM code called with vbl_lock held.
  1223. */
  1224. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1225. {
  1226. }
  1227. /*
  1228. * Small shared kms functions.
  1229. */
  1230. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1231. struct drm_vmw_rect *rects)
  1232. {
  1233. struct drm_device *dev = dev_priv->dev;
  1234. struct vmw_display_unit *du;
  1235. struct drm_connector *con;
  1236. mutex_lock(&dev->mode_config.mutex);
  1237. #if 0
  1238. {
  1239. unsigned int i;
  1240. DRM_INFO("%s: new layout ", __func__);
  1241. for (i = 0; i < num; i++)
  1242. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1243. rects[i].w, rects[i].h);
  1244. DRM_INFO("\n");
  1245. }
  1246. #endif
  1247. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1248. du = vmw_connector_to_du(con);
  1249. if (num > du->unit) {
  1250. du->pref_width = rects[du->unit].w;
  1251. du->pref_height = rects[du->unit].h;
  1252. du->pref_active = true;
  1253. du->gui_x = rects[du->unit].x;
  1254. du->gui_y = rects[du->unit].y;
  1255. } else {
  1256. du->pref_width = 800;
  1257. du->pref_height = 600;
  1258. du->pref_active = false;
  1259. }
  1260. con->status = vmw_du_connector_detect(con, true);
  1261. }
  1262. mutex_unlock(&dev->mode_config.mutex);
  1263. return 0;
  1264. }
  1265. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1266. {
  1267. }
  1268. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1269. {
  1270. }
  1271. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1272. u16 *r, u16 *g, u16 *b,
  1273. uint32_t start, uint32_t size)
  1274. {
  1275. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1276. int i;
  1277. for (i = 0; i < size; i++) {
  1278. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1279. r[i], g[i], b[i]);
  1280. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1281. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1282. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1283. }
  1284. }
  1285. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1286. {
  1287. }
  1288. void vmw_du_connector_save(struct drm_connector *connector)
  1289. {
  1290. }
  1291. void vmw_du_connector_restore(struct drm_connector *connector)
  1292. {
  1293. }
  1294. enum drm_connector_status
  1295. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1296. {
  1297. uint32_t num_displays;
  1298. struct drm_device *dev = connector->dev;
  1299. struct vmw_private *dev_priv = vmw_priv(dev);
  1300. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1301. mutex_lock(&dev_priv->hw_mutex);
  1302. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1303. mutex_unlock(&dev_priv->hw_mutex);
  1304. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1305. du->pref_active) ?
  1306. connector_status_connected : connector_status_disconnected);
  1307. }
  1308. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1309. /* 640x480@60Hz */
  1310. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1311. 752, 800, 0, 480, 489, 492, 525, 0,
  1312. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1313. /* 800x600@60Hz */
  1314. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1315. 968, 1056, 0, 600, 601, 605, 628, 0,
  1316. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1317. /* 1024x768@60Hz */
  1318. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1319. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1320. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1321. /* 1152x864@75Hz */
  1322. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1323. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1324. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1325. /* 1280x768@60Hz */
  1326. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1327. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1328. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1329. /* 1280x800@60Hz */
  1330. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1331. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1332. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1333. /* 1280x960@60Hz */
  1334. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1335. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1336. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1337. /* 1280x1024@60Hz */
  1338. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1339. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1340. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1341. /* 1360x768@60Hz */
  1342. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1343. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1344. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1345. /* 1440x1050@60Hz */
  1346. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1347. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1348. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1349. /* 1440x900@60Hz */
  1350. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1351. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1352. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1353. /* 1600x1200@60Hz */
  1354. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1355. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1356. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1357. /* 1680x1050@60Hz */
  1358. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1359. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1360. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1361. /* 1792x1344@60Hz */
  1362. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1363. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1364. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1365. /* 1853x1392@60Hz */
  1366. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1367. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1368. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1369. /* 1920x1200@60Hz */
  1370. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1371. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1372. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1373. /* 1920x1440@60Hz */
  1374. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1375. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1376. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1377. /* 2560x1600@60Hz */
  1378. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1379. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1380. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1381. /* Terminate */
  1382. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1383. };
  1384. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1385. uint32_t max_width, uint32_t max_height)
  1386. {
  1387. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1388. struct drm_device *dev = connector->dev;
  1389. struct vmw_private *dev_priv = vmw_priv(dev);
  1390. struct drm_display_mode *mode = NULL;
  1391. struct drm_display_mode *bmode;
  1392. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1393. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1394. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1395. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1396. };
  1397. int i;
  1398. /* Add preferred mode */
  1399. {
  1400. mode = drm_mode_duplicate(dev, &prefmode);
  1401. if (!mode)
  1402. return 0;
  1403. mode->hdisplay = du->pref_width;
  1404. mode->vdisplay = du->pref_height;
  1405. mode->vrefresh = drm_mode_vrefresh(mode);
  1406. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1407. mode->vdisplay)) {
  1408. drm_mode_probed_add(connector, mode);
  1409. if (du->pref_mode) {
  1410. list_del_init(&du->pref_mode->head);
  1411. drm_mode_destroy(dev, du->pref_mode);
  1412. }
  1413. du->pref_mode = mode;
  1414. }
  1415. }
  1416. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1417. bmode = &vmw_kms_connector_builtin[i];
  1418. if (bmode->hdisplay > max_width ||
  1419. bmode->vdisplay > max_height)
  1420. continue;
  1421. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1422. bmode->vdisplay))
  1423. continue;
  1424. mode = drm_mode_duplicate(dev, bmode);
  1425. if (!mode)
  1426. return 0;
  1427. mode->vrefresh = drm_mode_vrefresh(mode);
  1428. drm_mode_probed_add(connector, mode);
  1429. }
  1430. drm_mode_connector_list_update(connector);
  1431. return 1;
  1432. }
  1433. int vmw_du_connector_set_property(struct drm_connector *connector,
  1434. struct drm_property *property,
  1435. uint64_t val)
  1436. {
  1437. return 0;
  1438. }
  1439. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1440. struct drm_file *file_priv)
  1441. {
  1442. struct vmw_private *dev_priv = vmw_priv(dev);
  1443. struct drm_vmw_update_layout_arg *arg =
  1444. (struct drm_vmw_update_layout_arg *)data;
  1445. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1446. void __user *user_rects;
  1447. struct drm_vmw_rect *rects;
  1448. unsigned rects_size;
  1449. int ret;
  1450. int i;
  1451. struct drm_mode_config *mode_config = &dev->mode_config;
  1452. ret = ttm_read_lock(&vmaster->lock, true);
  1453. if (unlikely(ret != 0))
  1454. return ret;
  1455. if (!arg->num_outputs) {
  1456. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1457. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1458. goto out_unlock;
  1459. }
  1460. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1461. rects = kzalloc(rects_size, GFP_KERNEL);
  1462. if (unlikely(!rects)) {
  1463. ret = -ENOMEM;
  1464. goto out_unlock;
  1465. }
  1466. user_rects = (void __user *)(unsigned long)arg->rects;
  1467. ret = copy_from_user(rects, user_rects, rects_size);
  1468. if (unlikely(ret != 0)) {
  1469. DRM_ERROR("Failed to get rects.\n");
  1470. ret = -EFAULT;
  1471. goto out_free;
  1472. }
  1473. for (i = 0; i < arg->num_outputs; ++i) {
  1474. if (rects->x < 0 ||
  1475. rects->y < 0 ||
  1476. rects->x + rects->w > mode_config->max_width ||
  1477. rects->y + rects->h > mode_config->max_height) {
  1478. DRM_ERROR("Invalid GUI layout.\n");
  1479. ret = -EINVAL;
  1480. goto out_free;
  1481. }
  1482. }
  1483. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1484. out_free:
  1485. kfree(rects);
  1486. out_unlock:
  1487. ttm_read_unlock(&vmaster->lock);
  1488. return ret;
  1489. }