tegra20-seaboard.dts 14 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Seaboard";
  5. compatible = "nvidia,seaboard", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "spia",
  27. "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp", "lm1";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. dta {
  63. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  64. nvidia,function = "vi";
  65. };
  66. dtf {
  67. nvidia,pins = "dtf";
  68. nvidia,function = "i2c3";
  69. };
  70. gmc {
  71. nvidia,pins = "gmc";
  72. nvidia,function = "uartd";
  73. };
  74. gmd {
  75. nvidia,pins = "gmd";
  76. nvidia,function = "sflash";
  77. };
  78. gpu {
  79. nvidia,pins = "gpu";
  80. nvidia,function = "pwm";
  81. };
  82. gpu7 {
  83. nvidia,pins = "gpu7";
  84. nvidia,function = "rtck";
  85. };
  86. gpv {
  87. nvidia,pins = "gpv", "slxa", "slxk";
  88. nvidia,function = "pcie";
  89. };
  90. hdint {
  91. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  92. "lsck", "lsda";
  93. nvidia,function = "hdmi";
  94. };
  95. i2cp {
  96. nvidia,pins = "i2cp";
  97. nvidia,function = "i2cp";
  98. };
  99. irrx {
  100. nvidia,pins = "irrx", "irtx";
  101. nvidia,function = "uartb";
  102. };
  103. kbca {
  104. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  105. "kbce", "kbcf";
  106. nvidia,function = "kbc";
  107. };
  108. lcsn {
  109. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  110. "lsdi", "lvp0";
  111. nvidia,function = "rsvd4";
  112. };
  113. ld0 {
  114. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  115. "ld5", "ld6", "ld7", "ld8", "ld9",
  116. "ld10", "ld11", "ld12", "ld13", "ld14",
  117. "ld15", "ld16", "ld17", "ldi", "lhp0",
  118. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  119. "lspi", "lvp1", "lvs";
  120. nvidia,function = "displaya";
  121. };
  122. owc {
  123. nvidia,pins = "owc", "spdi", "spdo", "uac";
  124. nvidia,function = "rsvd2";
  125. };
  126. pmc {
  127. nvidia,pins = "pmc";
  128. nvidia,function = "pwr_on";
  129. };
  130. rm {
  131. nvidia,pins = "rm";
  132. nvidia,function = "i2c1";
  133. };
  134. sdb {
  135. nvidia,pins = "sdb", "sdc", "sdd";
  136. nvidia,function = "sdio3";
  137. };
  138. sdio1 {
  139. nvidia,pins = "sdio1";
  140. nvidia,function = "sdio1";
  141. };
  142. slxc {
  143. nvidia,pins = "slxc", "slxd";
  144. nvidia,function = "spdif";
  145. };
  146. spid {
  147. nvidia,pins = "spid", "spie", "spif";
  148. nvidia,function = "spi1";
  149. };
  150. spig {
  151. nvidia,pins = "spig", "spih";
  152. nvidia,function = "spi2_alt";
  153. };
  154. uaa {
  155. nvidia,pins = "uaa", "uab", "uda";
  156. nvidia,function = "ulpi";
  157. };
  158. uad {
  159. nvidia,pins = "uad";
  160. nvidia,function = "irda";
  161. };
  162. uca {
  163. nvidia,pins = "uca", "ucb";
  164. nvidia,function = "uartc";
  165. };
  166. conf_ata {
  167. nvidia,pins = "ata", "atb", "atc", "atd",
  168. "cdev1", "cdev2", "dap1", "dap2",
  169. "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
  170. "gme", "gpu", "gpu7", "i2cp", "irrx",
  171. "irtx", "pta", "rm", "sdc", "sdd",
  172. "slxd", "slxk", "spdi", "spdo", "uac",
  173. "uad", "uca", "ucb", "uda";
  174. nvidia,pull = <0>;
  175. nvidia,tristate = <0>;
  176. };
  177. conf_ate {
  178. nvidia,pins = "ate", "csus", "dap3",
  179. "gpv", "owc", "slxc", "spib", "spid",
  180. "spie";
  181. nvidia,pull = <0>;
  182. nvidia,tristate = <1>;
  183. };
  184. conf_ck32 {
  185. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  186. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  187. nvidia,pull = <0>;
  188. };
  189. conf_crtp {
  190. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  191. "spig", "spih";
  192. nvidia,pull = <2>;
  193. nvidia,tristate = <1>;
  194. };
  195. conf_dta {
  196. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  197. nvidia,pull = <1>;
  198. nvidia,tristate = <0>;
  199. };
  200. conf_dte {
  201. nvidia,pins = "dte", "spif";
  202. nvidia,pull = <1>;
  203. nvidia,tristate = <1>;
  204. };
  205. conf_hdint {
  206. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  207. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  208. "lvp0";
  209. nvidia,tristate = <1>;
  210. };
  211. conf_kbca {
  212. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  213. "kbce", "kbcf", "sdio1", "spic", "uaa",
  214. "uab";
  215. nvidia,pull = <2>;
  216. nvidia,tristate = <0>;
  217. };
  218. conf_lc {
  219. nvidia,pins = "lc", "ls";
  220. nvidia,pull = <2>;
  221. };
  222. conf_ld0 {
  223. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  224. "ld5", "ld6", "ld7", "ld8", "ld9",
  225. "ld10", "ld11", "ld12", "ld13", "ld14",
  226. "ld15", "ld16", "ld17", "ldi", "lhp0",
  227. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  228. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  229. "lvs", "pmc", "sdb";
  230. nvidia,tristate = <0>;
  231. };
  232. conf_ld17_0 {
  233. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  234. "ld23_22";
  235. nvidia,pull = <1>;
  236. };
  237. drive_sdio1 {
  238. nvidia,pins = "drive_sdio1";
  239. nvidia,high-speed-mode = <0>;
  240. nvidia,schmitt = <0>;
  241. nvidia,low-power-mode = <3>;
  242. nvidia,pull-down-strength = <31>;
  243. nvidia,pull-up-strength = <31>;
  244. nvidia,slew-rate-rising = <3>;
  245. nvidia,slew-rate-falling = <3>;
  246. };
  247. };
  248. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  249. ddc {
  250. nvidia,pins = "ddc";
  251. nvidia,function = "i2c2";
  252. };
  253. pta {
  254. nvidia,pins = "pta";
  255. nvidia,function = "rsvd4";
  256. };
  257. };
  258. state_i2cmux_pta: pinmux_i2cmux_pta {
  259. ddc {
  260. nvidia,pins = "ddc";
  261. nvidia,function = "rsvd4";
  262. };
  263. pta {
  264. nvidia,pins = "pta";
  265. nvidia,function = "i2c2";
  266. };
  267. };
  268. state_i2cmux_idle: pinmux_i2cmux_idle {
  269. ddc {
  270. nvidia,pins = "ddc";
  271. nvidia,function = "rsvd4";
  272. };
  273. pta {
  274. nvidia,pins = "pta";
  275. nvidia,function = "rsvd4";
  276. };
  277. };
  278. };
  279. i2s@70002800 {
  280. status = "okay";
  281. };
  282. serial@70006300 {
  283. status = "okay";
  284. clock-frequency = <216000000>;
  285. };
  286. i2c@7000c000 {
  287. status = "okay";
  288. clock-frequency = <400000>;
  289. wm8903: wm8903@1a {
  290. compatible = "wlf,wm8903";
  291. reg = <0x1a>;
  292. interrupt-parent = <&gpio>;
  293. interrupts = <187 0x04>;
  294. gpio-controller;
  295. #gpio-cells = <2>;
  296. micdet-cfg = <0>;
  297. micdet-delay = <100>;
  298. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  299. };
  300. /* ALS and proximity sensor */
  301. isl29018@44 {
  302. compatible = "isil,isl29018";
  303. reg = <0x44>;
  304. interrupt-parent = <&gpio>;
  305. interrupts = <202 0x04>; /* GPIO PZ2 */
  306. };
  307. gyrometer@68 {
  308. compatible = "invn,mpu3050";
  309. reg = <0x68>;
  310. interrupt-parent = <&gpio>;
  311. interrupts = <204 0x04>; /* gpio PZ4 */
  312. };
  313. };
  314. i2c@7000c400 {
  315. status = "okay";
  316. clock-frequency = <100000>;
  317. };
  318. i2cmux {
  319. compatible = "i2c-mux-pinctrl";
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. i2c-parent = <&{/i2c@7000c400}>;
  323. pinctrl-names = "ddc", "pta", "idle";
  324. pinctrl-0 = <&state_i2cmux_ddc>;
  325. pinctrl-1 = <&state_i2cmux_pta>;
  326. pinctrl-2 = <&state_i2cmux_idle>;
  327. i2c@0 {
  328. reg = <0>;
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. };
  332. i2c@1 {
  333. reg = <1>;
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. smart-battery@b {
  337. compatible = "ti,bq20z75", "smart-battery-1.1";
  338. reg = <0xb>;
  339. ti,i2c-retry-count = <2>;
  340. ti,poll-retry-count = <10>;
  341. };
  342. };
  343. };
  344. i2c@7000c500 {
  345. status = "okay";
  346. clock-frequency = <400000>;
  347. };
  348. i2c@7000d000 {
  349. status = "okay";
  350. clock-frequency = <400000>;
  351. pmic: tps6586x@34 {
  352. compatible = "ti,tps6586x";
  353. reg = <0x34>;
  354. interrupts = <0 86 0x4>;
  355. ti,system-power-controller;
  356. #gpio-cells = <2>;
  357. gpio-controller;
  358. sys-supply = <&vdd_5v0_reg>;
  359. vin-sm0-supply = <&sys_reg>;
  360. vin-sm1-supply = <&sys_reg>;
  361. vin-sm2-supply = <&sys_reg>;
  362. vinldo01-supply = <&sm2_reg>;
  363. vinldo23-supply = <&sm2_reg>;
  364. vinldo4-supply = <&sm2_reg>;
  365. vinldo678-supply = <&sm2_reg>;
  366. vinldo9-supply = <&sm2_reg>;
  367. regulators {
  368. sys_reg: sys {
  369. regulator-name = "vdd_sys";
  370. regulator-always-on;
  371. };
  372. sm0 {
  373. regulator-name = "vdd_sm0,vdd_core";
  374. regulator-min-microvolt = <1300000>;
  375. regulator-max-microvolt = <1300000>;
  376. regulator-always-on;
  377. };
  378. sm1 {
  379. regulator-name = "vdd_sm1,vdd_cpu";
  380. regulator-min-microvolt = <1125000>;
  381. regulator-max-microvolt = <1125000>;
  382. regulator-always-on;
  383. };
  384. sm2_reg: sm2 {
  385. regulator-name = "vdd_sm2,vin_ldo*";
  386. regulator-min-microvolt = <3700000>;
  387. regulator-max-microvolt = <3700000>;
  388. regulator-always-on;
  389. };
  390. /* LDO0 is not connected to anything */
  391. ldo1 {
  392. regulator-name = "vdd_ldo1,avdd_pll*";
  393. regulator-min-microvolt = <1100000>;
  394. regulator-max-microvolt = <1100000>;
  395. regulator-always-on;
  396. };
  397. ldo2 {
  398. regulator-name = "vdd_ldo2,vdd_rtc";
  399. regulator-min-microvolt = <1200000>;
  400. regulator-max-microvolt = <1200000>;
  401. };
  402. ldo3 {
  403. regulator-name = "vdd_ldo3,avdd_usb*";
  404. regulator-min-microvolt = <3300000>;
  405. regulator-max-microvolt = <3300000>;
  406. regulator-always-on;
  407. };
  408. ldo4 {
  409. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  410. regulator-min-microvolt = <1800000>;
  411. regulator-max-microvolt = <1800000>;
  412. regulator-always-on;
  413. };
  414. ldo5 {
  415. regulator-name = "vdd_ldo5,vcore_mmc";
  416. regulator-min-microvolt = <2850000>;
  417. regulator-max-microvolt = <2850000>;
  418. regulator-always-on;
  419. };
  420. ldo6 {
  421. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  422. regulator-min-microvolt = <1800000>;
  423. regulator-max-microvolt = <1800000>;
  424. };
  425. ldo7 {
  426. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  427. regulator-min-microvolt = <3300000>;
  428. regulator-max-microvolt = <3300000>;
  429. };
  430. ldo8 {
  431. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  432. regulator-min-microvolt = <1800000>;
  433. regulator-max-microvolt = <1800000>;
  434. };
  435. ldo9 {
  436. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  437. regulator-min-microvolt = <2850000>;
  438. regulator-max-microvolt = <2850000>;
  439. regulator-always-on;
  440. };
  441. ldo_rtc {
  442. regulator-name = "vdd_rtc_out,vdd_cell";
  443. regulator-min-microvolt = <3300000>;
  444. regulator-max-microvolt = <3300000>;
  445. regulator-always-on;
  446. };
  447. };
  448. };
  449. temperature-sensor@4c {
  450. compatible = "onnn,nct1008";
  451. reg = <0x4c>;
  452. };
  453. magnetometer@c {
  454. compatible = "ak,ak8975";
  455. reg = <0xc>;
  456. interrupt-parent = <&gpio>;
  457. interrupts = <109 0x04>; /* gpio PN5 */
  458. };
  459. };
  460. pmc {
  461. nvidia,invert-interrupt;
  462. };
  463. memory-controller@7000f400 {
  464. emc-table@190000 {
  465. reg = <190000>;
  466. compatible = "nvidia,tegra20-emc-table";
  467. clock-frequency = <190000>;
  468. nvidia,emc-registers = <0x0000000c 0x00000026
  469. 0x00000009 0x00000003 0x00000004 0x00000004
  470. 0x00000002 0x0000000c 0x00000003 0x00000003
  471. 0x00000002 0x00000001 0x00000004 0x00000005
  472. 0x00000004 0x00000009 0x0000000d 0x0000059f
  473. 0x00000000 0x00000003 0x00000003 0x00000003
  474. 0x00000003 0x00000001 0x0000000b 0x000000c8
  475. 0x00000003 0x00000007 0x00000004 0x0000000f
  476. 0x00000002 0x00000000 0x00000000 0x00000002
  477. 0x00000000 0x00000000 0x00000083 0xa06204ae
  478. 0x007dc010 0x00000000 0x00000000 0x00000000
  479. 0x00000000 0x00000000 0x00000000 0x00000000>;
  480. };
  481. emc-table@380000 {
  482. reg = <380000>;
  483. compatible = "nvidia,tegra20-emc-table";
  484. clock-frequency = <380000>;
  485. nvidia,emc-registers = <0x00000017 0x0000004b
  486. 0x00000012 0x00000006 0x00000004 0x00000005
  487. 0x00000003 0x0000000c 0x00000006 0x00000006
  488. 0x00000003 0x00000001 0x00000004 0x00000005
  489. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  490. 0x00000000 0x00000003 0x00000003 0x00000006
  491. 0x00000006 0x00000001 0x00000011 0x000000c8
  492. 0x00000003 0x0000000e 0x00000007 0x0000000f
  493. 0x00000002 0x00000000 0x00000000 0x00000002
  494. 0x00000000 0x00000000 0x00000083 0xe044048b
  495. 0x007d8010 0x00000000 0x00000000 0x00000000
  496. 0x00000000 0x00000000 0x00000000 0x00000000>;
  497. };
  498. };
  499. usb@c5000000 {
  500. status = "okay";
  501. nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
  502. dr_mode = "otg";
  503. };
  504. usb@c5004000 {
  505. status = "okay";
  506. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  507. };
  508. usb@c5008000 {
  509. status = "okay";
  510. };
  511. sdhci@c8000000 {
  512. status = "okay";
  513. power-gpios = <&gpio 86 0>; /* gpio PK6 */
  514. bus-width = <4>;
  515. };
  516. sdhci@c8000400 {
  517. status = "okay";
  518. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  519. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  520. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  521. bus-width = <4>;
  522. };
  523. sdhci@c8000600 {
  524. status = "okay";
  525. bus-width = <8>;
  526. };
  527. gpio-keys {
  528. compatible = "gpio-keys";
  529. power {
  530. label = "Power";
  531. gpios = <&gpio 170 1>; /* gpio PV2, active low */
  532. linux,code = <116>; /* KEY_POWER */
  533. gpio-key,wakeup;
  534. };
  535. lid {
  536. label = "Lid";
  537. gpios = <&gpio 23 0>; /* gpio PC7 */
  538. linux,input-type = <5>; /* EV_SW */
  539. linux,code = <0>; /* SW_LID */
  540. debounce-interval = <1>;
  541. gpio-key,wakeup;
  542. };
  543. };
  544. regulators {
  545. compatible = "simple-bus";
  546. #address-cells = <1>;
  547. #size-cells = <0>;
  548. vdd_5v0_reg: regulator@0 {
  549. compatible = "regulator-fixed";
  550. reg = <0>;
  551. regulator-name = "vdd_5v0";
  552. regulator-min-microvolt = <5000000>;
  553. regulator-max-microvolt = <5000000>;
  554. regulator-always-on;
  555. };
  556. regulator@1 {
  557. compatible = "regulator-fixed";
  558. reg = <1>;
  559. regulator-name = "vdd_1v5";
  560. regulator-min-microvolt = <1500000>;
  561. regulator-max-microvolt = <1500000>;
  562. gpio = <&pmic 0 0>;
  563. };
  564. regulator@2 {
  565. compatible = "regulator-fixed";
  566. reg = <2>;
  567. regulator-name = "vdd_1v2";
  568. regulator-min-microvolt = <1200000>;
  569. regulator-max-microvolt = <1200000>;
  570. gpio = <&pmic 1 0>;
  571. enable-active-high;
  572. };
  573. };
  574. sound {
  575. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  576. "nvidia,tegra-audio-wm8903";
  577. nvidia,model = "NVIDIA Tegra Seaboard";
  578. nvidia,audio-routing =
  579. "Headphone Jack", "HPOUTR",
  580. "Headphone Jack", "HPOUTL",
  581. "Int Spk", "ROP",
  582. "Int Spk", "RON",
  583. "Int Spk", "LOP",
  584. "Int Spk", "LON",
  585. "Mic Jack", "MICBIAS",
  586. "IN1R", "Mic Jack";
  587. nvidia,i2s-controller = <&tegra_i2s1>;
  588. nvidia,audio-codec = <&wm8903>;
  589. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  590. nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
  591. };
  592. };