powergate.c 4.6 KB

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  1. /*
  2. * drivers/powergate/tegra-powergate.c
  3. *
  4. * Copyright (c) 2010 Google, Inc
  5. *
  6. * Author:
  7. * Colin Cross <ccross@google.com>
  8. *
  9. * This software is licensed under the terms of the GNU General Public
  10. * License version 2, as published by the Free Software Foundation, and
  11. * may be copied, distributed, and modified under those terms.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/clk.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/delay.h>
  23. #include <linux/err.h>
  24. #include <linux/init.h>
  25. #include <linux/io.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/spinlock.h>
  28. #include <mach/clk.h>
  29. #include <mach/iomap.h>
  30. #include <mach/powergate.h>
  31. #include "fuse.h"
  32. #define PWRGATE_TOGGLE 0x30
  33. #define PWRGATE_TOGGLE_START (1 << 8)
  34. #define REMOVE_CLAMPING 0x34
  35. #define PWRGATE_STATUS 0x38
  36. static int tegra_num_powerdomains;
  37. static DEFINE_SPINLOCK(tegra_powergate_lock);
  38. static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
  39. static u32 pmc_read(unsigned long reg)
  40. {
  41. return readl(pmc + reg);
  42. }
  43. static void pmc_write(u32 val, unsigned long reg)
  44. {
  45. writel(val, pmc + reg);
  46. }
  47. static int tegra_powergate_set(int id, bool new_state)
  48. {
  49. bool status;
  50. unsigned long flags;
  51. spin_lock_irqsave(&tegra_powergate_lock, flags);
  52. status = pmc_read(PWRGATE_STATUS) & (1 << id);
  53. if (status == new_state) {
  54. spin_unlock_irqrestore(&tegra_powergate_lock, flags);
  55. return -EINVAL;
  56. }
  57. pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
  58. spin_unlock_irqrestore(&tegra_powergate_lock, flags);
  59. return 0;
  60. }
  61. int tegra_powergate_power_on(int id)
  62. {
  63. if (id < 0 || id >= tegra_num_powerdomains)
  64. return -EINVAL;
  65. return tegra_powergate_set(id, true);
  66. }
  67. int tegra_powergate_power_off(int id)
  68. {
  69. if (id < 0 || id >= tegra_num_powerdomains)
  70. return -EINVAL;
  71. return tegra_powergate_set(id, false);
  72. }
  73. static int tegra_powergate_is_powered(int id)
  74. {
  75. u32 status;
  76. if (id < 0 || id >= tegra_num_powerdomains)
  77. return -EINVAL;
  78. status = pmc_read(PWRGATE_STATUS) & (1 << id);
  79. return !!status;
  80. }
  81. int tegra_powergate_remove_clamping(int id)
  82. {
  83. u32 mask;
  84. if (id < 0 || id >= tegra_num_powerdomains)
  85. return -EINVAL;
  86. /*
  87. * Tegra 2 has a bug where PCIE and VDE clamping masks are
  88. * swapped relatively to the partition ids
  89. */
  90. if (id == TEGRA_POWERGATE_VDEC)
  91. mask = (1 << TEGRA_POWERGATE_PCIE);
  92. else if (id == TEGRA_POWERGATE_PCIE)
  93. mask = (1 << TEGRA_POWERGATE_VDEC);
  94. else
  95. mask = (1 << id);
  96. pmc_write(mask, REMOVE_CLAMPING);
  97. return 0;
  98. }
  99. /* Must be called with clk disabled, and returns with clk enabled */
  100. int tegra_powergate_sequence_power_up(int id, struct clk *clk)
  101. {
  102. int ret;
  103. tegra_periph_reset_assert(clk);
  104. ret = tegra_powergate_power_on(id);
  105. if (ret)
  106. goto err_power;
  107. ret = clk_enable(clk);
  108. if (ret)
  109. goto err_clk;
  110. udelay(10);
  111. ret = tegra_powergate_remove_clamping(id);
  112. if (ret)
  113. goto err_clamp;
  114. udelay(10);
  115. tegra_periph_reset_deassert(clk);
  116. return 0;
  117. err_clamp:
  118. clk_disable(clk);
  119. err_clk:
  120. tegra_powergate_power_off(id);
  121. err_power:
  122. return ret;
  123. }
  124. int __init tegra_powergate_init(void)
  125. {
  126. switch (tegra_chip_id) {
  127. case TEGRA20:
  128. tegra_num_powerdomains = 7;
  129. break;
  130. default:
  131. /* Unknown Tegra variant. Disable powergating */
  132. tegra_num_powerdomains = 0;
  133. break;
  134. }
  135. return 0;
  136. }
  137. arch_initcall(tegra_powergate_init);
  138. #ifdef CONFIG_DEBUG_FS
  139. static const char * const powergate_name[] = {
  140. [TEGRA_POWERGATE_CPU] = "cpu",
  141. [TEGRA_POWERGATE_3D] = "3d",
  142. [TEGRA_POWERGATE_VENC] = "venc",
  143. [TEGRA_POWERGATE_VDEC] = "vdec",
  144. [TEGRA_POWERGATE_PCIE] = "pcie",
  145. [TEGRA_POWERGATE_L2] = "l2",
  146. [TEGRA_POWERGATE_MPE] = "mpe",
  147. };
  148. static int powergate_show(struct seq_file *s, void *data)
  149. {
  150. int i;
  151. seq_printf(s, " powergate powered\n");
  152. seq_printf(s, "------------------\n");
  153. for (i = 0; i < tegra_num_powerdomains; i++)
  154. seq_printf(s, " %9s %7s\n", powergate_name[i],
  155. tegra_powergate_is_powered(i) ? "yes" : "no");
  156. return 0;
  157. }
  158. static int powergate_open(struct inode *inode, struct file *file)
  159. {
  160. return single_open(file, powergate_show, inode->i_private);
  161. }
  162. static const struct file_operations powergate_fops = {
  163. .open = powergate_open,
  164. .read = seq_read,
  165. .llseek = seq_lseek,
  166. .release = single_release,
  167. };
  168. static int __init powergate_debugfs_init(void)
  169. {
  170. struct dentry *d;
  171. int err = -ENOMEM;
  172. d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
  173. &powergate_fops);
  174. if (!d)
  175. return -ENOMEM;
  176. return err;
  177. }
  178. late_initcall(powergate_debugfs_init);
  179. #endif