coda.c 54 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/of.h>
  25. #include <mach/iram.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-ioctl.h>
  29. #include <media/v4l2-mem2mem.h>
  30. #include <media/videobuf2-core.h>
  31. #include <media/videobuf2-dma-contig.h>
  32. #include "coda.h"
  33. #define CODA_NAME "coda"
  34. #define CODA_MAX_INSTANCES 4
  35. #define CODA_FMO_BUF_SIZE 32
  36. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  37. #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  38. #define CODA_PARA_BUF_SIZE (10 * 1024)
  39. #define CODA_ISRAM_SIZE (2048 * 2)
  40. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  41. #define CODA_MAX_FRAMEBUFFERS 2
  42. #define MAX_W 720
  43. #define MAX_H 576
  44. #define CODA_MAX_FRAME_SIZE 0x90000
  45. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  46. #define CODA_DEFAULT_GAMMA 4096
  47. #define MIN_W 176
  48. #define MIN_H 144
  49. #define MAX_W 720
  50. #define MAX_H 576
  51. #define S_ALIGN 1 /* multiple of 2 */
  52. #define W_ALIGN 1 /* multiple of 2 */
  53. #define H_ALIGN 1 /* multiple of 2 */
  54. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  55. static int coda_debug;
  56. module_param(coda_debug, int, 0);
  57. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  58. enum {
  59. V4L2_M2M_SRC = 0,
  60. V4L2_M2M_DST = 1,
  61. };
  62. enum coda_fmt_type {
  63. CODA_FMT_ENC,
  64. CODA_FMT_RAW,
  65. };
  66. enum coda_inst_type {
  67. CODA_INST_ENCODER,
  68. CODA_INST_DECODER,
  69. };
  70. enum coda_product {
  71. CODA_DX6 = 0xf001,
  72. CODA_7541 = 0xf012,
  73. };
  74. struct coda_fmt {
  75. char *name;
  76. u32 fourcc;
  77. enum coda_fmt_type type;
  78. };
  79. struct coda_devtype {
  80. char *firmware;
  81. enum coda_product product;
  82. struct coda_fmt *formats;
  83. unsigned int num_formats;
  84. size_t workbuf_size;
  85. };
  86. /* Per-queue, driver-specific private data */
  87. struct coda_q_data {
  88. unsigned int width;
  89. unsigned int height;
  90. unsigned int sizeimage;
  91. struct coda_fmt *fmt;
  92. };
  93. struct coda_aux_buf {
  94. void *vaddr;
  95. dma_addr_t paddr;
  96. u32 size;
  97. };
  98. struct coda_dev {
  99. struct v4l2_device v4l2_dev;
  100. struct video_device vfd;
  101. struct platform_device *plat_dev;
  102. const struct coda_devtype *devtype;
  103. void __iomem *regs_base;
  104. struct clk *clk_per;
  105. struct clk *clk_ahb;
  106. struct coda_aux_buf codebuf;
  107. struct coda_aux_buf workbuf;
  108. long unsigned int iram_paddr;
  109. spinlock_t irqlock;
  110. struct mutex dev_mutex;
  111. struct v4l2_m2m_dev *m2m_dev;
  112. struct vb2_alloc_ctx *alloc_ctx;
  113. struct list_head instances;
  114. unsigned long instance_mask;
  115. struct delayed_work timeout;
  116. struct completion done;
  117. };
  118. struct coda_params {
  119. u8 rot_mode;
  120. u8 h264_intra_qp;
  121. u8 h264_inter_qp;
  122. u8 mpeg4_intra_qp;
  123. u8 mpeg4_inter_qp;
  124. u8 gop_size;
  125. int codec_mode;
  126. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  127. u32 framerate;
  128. u16 bitrate;
  129. u32 slice_max_mb;
  130. };
  131. struct coda_ctx {
  132. struct coda_dev *dev;
  133. struct list_head list;
  134. int aborting;
  135. int rawstreamon;
  136. int compstreamon;
  137. u32 isequence;
  138. struct coda_q_data q_data[2];
  139. enum coda_inst_type inst_type;
  140. enum v4l2_colorspace colorspace;
  141. struct coda_params params;
  142. struct v4l2_m2m_ctx *m2m_ctx;
  143. struct v4l2_ctrl_handler ctrls;
  144. struct v4l2_fh fh;
  145. int gopcounter;
  146. char vpu_header[3][64];
  147. int vpu_header_size[3];
  148. struct coda_aux_buf parabuf;
  149. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  150. int num_internal_frames;
  151. int idx;
  152. };
  153. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  154. {
  155. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  156. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  157. writel(data, dev->regs_base + reg);
  158. }
  159. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  160. {
  161. u32 data;
  162. data = readl(dev->regs_base + reg);
  163. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  164. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  165. return data;
  166. }
  167. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  168. {
  169. return coda_read(dev, CODA_REG_BIT_BUSY);
  170. }
  171. static inline int coda_is_initialized(struct coda_dev *dev)
  172. {
  173. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  174. }
  175. static int coda_wait_timeout(struct coda_dev *dev)
  176. {
  177. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  178. while (coda_isbusy(dev)) {
  179. if (time_after(jiffies, timeout))
  180. return -ETIMEDOUT;
  181. }
  182. return 0;
  183. }
  184. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  185. {
  186. struct coda_dev *dev = ctx->dev;
  187. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  188. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  189. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  190. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  191. }
  192. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  193. {
  194. struct coda_dev *dev = ctx->dev;
  195. coda_command_async(ctx, cmd);
  196. return coda_wait_timeout(dev);
  197. }
  198. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  199. enum v4l2_buf_type type)
  200. {
  201. switch (type) {
  202. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  203. return &(ctx->q_data[V4L2_M2M_SRC]);
  204. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  205. return &(ctx->q_data[V4L2_M2M_DST]);
  206. default:
  207. BUG();
  208. }
  209. return NULL;
  210. }
  211. /*
  212. * Add one array of supported formats for each version of Coda:
  213. * i.MX27 -> codadx6
  214. * i.MX51 -> coda7
  215. * i.MX6 -> coda960
  216. */
  217. static struct coda_fmt codadx6_formats[] = {
  218. {
  219. .name = "YUV 4:2:0 Planar",
  220. .fourcc = V4L2_PIX_FMT_YUV420,
  221. .type = CODA_FMT_RAW,
  222. },
  223. {
  224. .name = "H264 Encoded Stream",
  225. .fourcc = V4L2_PIX_FMT_H264,
  226. .type = CODA_FMT_ENC,
  227. },
  228. {
  229. .name = "MPEG4 Encoded Stream",
  230. .fourcc = V4L2_PIX_FMT_MPEG4,
  231. .type = CODA_FMT_ENC,
  232. },
  233. };
  234. static struct coda_fmt coda7_formats[] = {
  235. {
  236. .name = "YUV 4:2:0 Planar",
  237. .fourcc = V4L2_PIX_FMT_YUV420,
  238. .type = CODA_FMT_RAW,
  239. },
  240. {
  241. .name = "H264 Encoded Stream",
  242. .fourcc = V4L2_PIX_FMT_H264,
  243. .type = CODA_FMT_ENC,
  244. },
  245. {
  246. .name = "MPEG4 Encoded Stream",
  247. .fourcc = V4L2_PIX_FMT_MPEG4,
  248. .type = CODA_FMT_ENC,
  249. },
  250. };
  251. static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
  252. {
  253. struct coda_fmt *formats = dev->devtype->formats;
  254. int num_formats = dev->devtype->num_formats;
  255. unsigned int k;
  256. for (k = 0; k < num_formats; k++) {
  257. if (formats[k].fourcc == f->fmt.pix.pixelformat)
  258. break;
  259. }
  260. if (k == num_formats)
  261. return NULL;
  262. return &formats[k];
  263. }
  264. /*
  265. * V4L2 ioctl() operations.
  266. */
  267. static int vidioc_querycap(struct file *file, void *priv,
  268. struct v4l2_capability *cap)
  269. {
  270. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  271. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  272. strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
  273. /*
  274. * This is only a mem-to-mem video device. The capture and output
  275. * device capability flags are left only for backward compatibility
  276. * and are scheduled for removal.
  277. */
  278. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  279. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  280. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  281. return 0;
  282. }
  283. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  284. enum coda_fmt_type type)
  285. {
  286. struct coda_ctx *ctx = fh_to_ctx(priv);
  287. struct coda_dev *dev = ctx->dev;
  288. struct coda_fmt *formats = dev->devtype->formats;
  289. struct coda_fmt *fmt;
  290. int num_formats = dev->devtype->num_formats;
  291. int i, num = 0;
  292. for (i = 0; i < num_formats; i++) {
  293. if (formats[i].type == type) {
  294. if (num == f->index)
  295. break;
  296. ++num;
  297. }
  298. }
  299. if (i < num_formats) {
  300. fmt = &formats[i];
  301. strlcpy(f->description, fmt->name, sizeof(f->description));
  302. f->pixelformat = fmt->fourcc;
  303. return 0;
  304. }
  305. /* Format not found */
  306. return -EINVAL;
  307. }
  308. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  309. struct v4l2_fmtdesc *f)
  310. {
  311. return enum_fmt(priv, f, CODA_FMT_ENC);
  312. }
  313. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  314. struct v4l2_fmtdesc *f)
  315. {
  316. return enum_fmt(priv, f, CODA_FMT_RAW);
  317. }
  318. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  319. {
  320. struct vb2_queue *vq;
  321. struct coda_q_data *q_data;
  322. struct coda_ctx *ctx = fh_to_ctx(priv);
  323. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  324. if (!vq)
  325. return -EINVAL;
  326. q_data = get_q_data(ctx, f->type);
  327. f->fmt.pix.field = V4L2_FIELD_NONE;
  328. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  329. f->fmt.pix.width = q_data->width;
  330. f->fmt.pix.height = q_data->height;
  331. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  332. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  333. else /* encoded formats h.264/mpeg4 */
  334. f->fmt.pix.bytesperline = 0;
  335. f->fmt.pix.sizeimage = q_data->sizeimage;
  336. f->fmt.pix.colorspace = ctx->colorspace;
  337. return 0;
  338. }
  339. static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
  340. {
  341. enum v4l2_field field;
  342. field = f->fmt.pix.field;
  343. if (field == V4L2_FIELD_ANY)
  344. field = V4L2_FIELD_NONE;
  345. else if (V4L2_FIELD_NONE != field)
  346. return -EINVAL;
  347. /* V4L2 specification suggests the driver corrects the format struct
  348. * if any of the dimensions is unsupported */
  349. f->fmt.pix.field = field;
  350. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  351. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  352. W_ALIGN, &f->fmt.pix.height,
  353. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  354. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  355. f->fmt.pix.sizeimage = f->fmt.pix.width *
  356. f->fmt.pix.height * 3 / 2;
  357. } else { /*encoded formats h.264/mpeg4 */
  358. f->fmt.pix.bytesperline = 0;
  359. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  360. }
  361. return 0;
  362. }
  363. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  364. struct v4l2_format *f)
  365. {
  366. int ret;
  367. struct coda_fmt *fmt;
  368. struct coda_ctx *ctx = fh_to_ctx(priv);
  369. fmt = find_format(ctx->dev, f);
  370. /*
  371. * Since decoding support is not implemented yet do not allow
  372. * CODA_FMT_RAW formats in the capture interface.
  373. */
  374. if (!fmt || !(fmt->type == CODA_FMT_ENC))
  375. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  376. f->fmt.pix.colorspace = ctx->colorspace;
  377. ret = vidioc_try_fmt(ctx->dev, f);
  378. if (ret < 0)
  379. return ret;
  380. return 0;
  381. }
  382. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  383. struct v4l2_format *f)
  384. {
  385. struct coda_ctx *ctx = fh_to_ctx(priv);
  386. struct coda_fmt *fmt;
  387. int ret;
  388. fmt = find_format(ctx->dev, f);
  389. /*
  390. * Since decoding support is not implemented yet do not allow
  391. * CODA_FMT formats in the capture interface.
  392. */
  393. if (!fmt || !(fmt->type == CODA_FMT_RAW))
  394. f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
  395. if (!f->fmt.pix.colorspace)
  396. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  397. ret = vidioc_try_fmt(ctx->dev, f);
  398. if (ret < 0)
  399. return ret;
  400. return 0;
  401. }
  402. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  403. {
  404. struct coda_q_data *q_data;
  405. struct vb2_queue *vq;
  406. int ret;
  407. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  408. if (!vq)
  409. return -EINVAL;
  410. q_data = get_q_data(ctx, f->type);
  411. if (!q_data)
  412. return -EINVAL;
  413. if (vb2_is_busy(vq)) {
  414. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  415. return -EBUSY;
  416. }
  417. ret = vidioc_try_fmt(ctx->dev, f);
  418. if (ret)
  419. return ret;
  420. q_data->fmt = find_format(ctx->dev, f);
  421. q_data->width = f->fmt.pix.width;
  422. q_data->height = f->fmt.pix.height;
  423. q_data->sizeimage = f->fmt.pix.sizeimage;
  424. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  425. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  426. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  427. return 0;
  428. }
  429. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  430. struct v4l2_format *f)
  431. {
  432. int ret;
  433. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  434. if (ret)
  435. return ret;
  436. return vidioc_s_fmt(fh_to_ctx(priv), f);
  437. }
  438. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  439. struct v4l2_format *f)
  440. {
  441. struct coda_ctx *ctx = fh_to_ctx(priv);
  442. int ret;
  443. ret = vidioc_try_fmt_vid_out(file, priv, f);
  444. if (ret)
  445. return ret;
  446. ret = vidioc_s_fmt(ctx, f);
  447. if (ret)
  448. ctx->colorspace = f->fmt.pix.colorspace;
  449. return ret;
  450. }
  451. static int vidioc_reqbufs(struct file *file, void *priv,
  452. struct v4l2_requestbuffers *reqbufs)
  453. {
  454. struct coda_ctx *ctx = fh_to_ctx(priv);
  455. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  456. }
  457. static int vidioc_querybuf(struct file *file, void *priv,
  458. struct v4l2_buffer *buf)
  459. {
  460. struct coda_ctx *ctx = fh_to_ctx(priv);
  461. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  462. }
  463. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  464. {
  465. struct coda_ctx *ctx = fh_to_ctx(priv);
  466. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  467. }
  468. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  469. {
  470. struct coda_ctx *ctx = fh_to_ctx(priv);
  471. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  472. }
  473. static int vidioc_streamon(struct file *file, void *priv,
  474. enum v4l2_buf_type type)
  475. {
  476. struct coda_ctx *ctx = fh_to_ctx(priv);
  477. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  478. }
  479. static int vidioc_streamoff(struct file *file, void *priv,
  480. enum v4l2_buf_type type)
  481. {
  482. struct coda_ctx *ctx = fh_to_ctx(priv);
  483. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  484. }
  485. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  486. .vidioc_querycap = vidioc_querycap,
  487. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  488. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  489. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  490. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  491. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  492. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  493. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  494. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  495. .vidioc_reqbufs = vidioc_reqbufs,
  496. .vidioc_querybuf = vidioc_querybuf,
  497. .vidioc_qbuf = vidioc_qbuf,
  498. .vidioc_dqbuf = vidioc_dqbuf,
  499. .vidioc_streamon = vidioc_streamon,
  500. .vidioc_streamoff = vidioc_streamoff,
  501. };
  502. /*
  503. * Mem-to-mem operations.
  504. */
  505. static void coda_device_run(void *m2m_priv)
  506. {
  507. struct coda_ctx *ctx = m2m_priv;
  508. struct coda_q_data *q_data_src, *q_data_dst;
  509. struct vb2_buffer *src_buf, *dst_buf;
  510. struct coda_dev *dev = ctx->dev;
  511. int force_ipicture;
  512. int quant_param = 0;
  513. u32 picture_y, picture_cb, picture_cr;
  514. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  515. u32 dst_fourcc;
  516. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  517. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  518. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  519. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  520. dst_fourcc = q_data_dst->fmt->fourcc;
  521. src_buf->v4l2_buf.sequence = ctx->isequence;
  522. dst_buf->v4l2_buf.sequence = ctx->isequence;
  523. ctx->isequence++;
  524. /*
  525. * Workaround coda firmware BUG that only marks the first
  526. * frame as IDR. This is a problem for some decoders that can't
  527. * recover when a frame is lost.
  528. */
  529. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  530. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  531. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  532. } else {
  533. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  534. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  535. }
  536. /*
  537. * Copy headers at the beginning of the first frame for H.264 only.
  538. * In MPEG4 they are already copied by the coda.
  539. */
  540. if (src_buf->v4l2_buf.sequence == 0) {
  541. pic_stream_buffer_addr =
  542. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  543. ctx->vpu_header_size[0] +
  544. ctx->vpu_header_size[1] +
  545. ctx->vpu_header_size[2];
  546. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  547. ctx->vpu_header_size[0] -
  548. ctx->vpu_header_size[1] -
  549. ctx->vpu_header_size[2];
  550. memcpy(vb2_plane_vaddr(dst_buf, 0),
  551. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  552. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  553. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  554. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  555. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  556. ctx->vpu_header_size[2]);
  557. } else {
  558. pic_stream_buffer_addr =
  559. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  560. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  561. }
  562. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  563. force_ipicture = 1;
  564. switch (dst_fourcc) {
  565. case V4L2_PIX_FMT_H264:
  566. quant_param = ctx->params.h264_intra_qp;
  567. break;
  568. case V4L2_PIX_FMT_MPEG4:
  569. quant_param = ctx->params.mpeg4_intra_qp;
  570. break;
  571. default:
  572. v4l2_warn(&ctx->dev->v4l2_dev,
  573. "cannot set intra qp, fmt not supported\n");
  574. break;
  575. }
  576. } else {
  577. force_ipicture = 0;
  578. switch (dst_fourcc) {
  579. case V4L2_PIX_FMT_H264:
  580. quant_param = ctx->params.h264_inter_qp;
  581. break;
  582. case V4L2_PIX_FMT_MPEG4:
  583. quant_param = ctx->params.mpeg4_inter_qp;
  584. break;
  585. default:
  586. v4l2_warn(&ctx->dev->v4l2_dev,
  587. "cannot set inter qp, fmt not supported\n");
  588. break;
  589. }
  590. }
  591. /* submit */
  592. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  593. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  594. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  595. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  596. picture_cr = picture_cb + q_data_src->width / 2 *
  597. q_data_src->height / 2;
  598. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  599. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  600. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  601. coda_write(dev, force_ipicture << 1 & 0x2,
  602. CODA_CMD_ENC_PIC_OPTION);
  603. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  604. coda_write(dev, pic_stream_buffer_size / 1024,
  605. CODA_CMD_ENC_PIC_BB_SIZE);
  606. if (dev->devtype->product == CODA_7541) {
  607. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  608. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  609. CODA7_REG_BIT_AXI_SRAM_USE);
  610. }
  611. /* 1 second timeout in case CODA locks up */
  612. schedule_delayed_work(&dev->timeout, HZ);
  613. INIT_COMPLETION(dev->done);
  614. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  615. }
  616. static int coda_job_ready(void *m2m_priv)
  617. {
  618. struct coda_ctx *ctx = m2m_priv;
  619. /*
  620. * For both 'P' and 'key' frame cases 1 picture
  621. * and 1 frame are needed.
  622. */
  623. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
  624. !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  625. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  626. "not ready: not enough video buffers.\n");
  627. return 0;
  628. }
  629. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  630. "job ready\n");
  631. return 1;
  632. }
  633. static void coda_job_abort(void *priv)
  634. {
  635. struct coda_ctx *ctx = priv;
  636. struct coda_dev *dev = ctx->dev;
  637. ctx->aborting = 1;
  638. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  639. "Aborting task\n");
  640. v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
  641. }
  642. static void coda_lock(void *m2m_priv)
  643. {
  644. struct coda_ctx *ctx = m2m_priv;
  645. struct coda_dev *pcdev = ctx->dev;
  646. mutex_lock(&pcdev->dev_mutex);
  647. }
  648. static void coda_unlock(void *m2m_priv)
  649. {
  650. struct coda_ctx *ctx = m2m_priv;
  651. struct coda_dev *pcdev = ctx->dev;
  652. mutex_unlock(&pcdev->dev_mutex);
  653. }
  654. static struct v4l2_m2m_ops coda_m2m_ops = {
  655. .device_run = coda_device_run,
  656. .job_ready = coda_job_ready,
  657. .job_abort = coda_job_abort,
  658. .lock = coda_lock,
  659. .unlock = coda_unlock,
  660. };
  661. static void set_default_params(struct coda_ctx *ctx)
  662. {
  663. struct coda_dev *dev = ctx->dev;
  664. ctx->params.codec_mode = CODA_MODE_INVALID;
  665. ctx->colorspace = V4L2_COLORSPACE_REC709;
  666. ctx->params.framerate = 30;
  667. ctx->aborting = 0;
  668. /* Default formats for output and input queues */
  669. ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
  670. ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
  671. ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
  672. ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
  673. ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
  674. ctx->q_data[V4L2_M2M_DST].width = MAX_W;
  675. ctx->q_data[V4L2_M2M_DST].height = MAX_H;
  676. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  677. }
  678. /*
  679. * Queue operations
  680. */
  681. static int coda_queue_setup(struct vb2_queue *vq,
  682. const struct v4l2_format *fmt,
  683. unsigned int *nbuffers, unsigned int *nplanes,
  684. unsigned int sizes[], void *alloc_ctxs[])
  685. {
  686. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  687. unsigned int size;
  688. if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  689. if (fmt)
  690. size = fmt->fmt.pix.width *
  691. fmt->fmt.pix.height * 3 / 2;
  692. else
  693. size = MAX_W *
  694. MAX_H * 3 / 2;
  695. } else {
  696. size = CODA_MAX_FRAME_SIZE;
  697. }
  698. *nplanes = 1;
  699. sizes[0] = size;
  700. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  701. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  702. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  703. return 0;
  704. }
  705. static int coda_buf_prepare(struct vb2_buffer *vb)
  706. {
  707. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  708. struct coda_q_data *q_data;
  709. q_data = get_q_data(ctx, vb->vb2_queue->type);
  710. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  711. v4l2_warn(&ctx->dev->v4l2_dev,
  712. "%s data will not fit into plane (%lu < %lu)\n",
  713. __func__, vb2_plane_size(vb, 0),
  714. (long)q_data->sizeimage);
  715. return -EINVAL;
  716. }
  717. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  718. return 0;
  719. }
  720. static void coda_buf_queue(struct vb2_buffer *vb)
  721. {
  722. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  723. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  724. }
  725. static void coda_wait_prepare(struct vb2_queue *q)
  726. {
  727. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  728. coda_unlock(ctx);
  729. }
  730. static void coda_wait_finish(struct vb2_queue *q)
  731. {
  732. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  733. coda_lock(ctx);
  734. }
  735. static void coda_free_framebuffers(struct coda_ctx *ctx)
  736. {
  737. int i;
  738. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
  739. if (ctx->internal_frames[i].vaddr) {
  740. dma_free_coherent(&ctx->dev->plat_dev->dev,
  741. ctx->internal_frames[i].size,
  742. ctx->internal_frames[i].vaddr,
  743. ctx->internal_frames[i].paddr);
  744. ctx->internal_frames[i].vaddr = NULL;
  745. }
  746. }
  747. }
  748. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  749. {
  750. struct coda_dev *dev = ctx->dev;
  751. int height = q_data->height;
  752. int width = q_data->width;
  753. u32 *p;
  754. int i;
  755. /* Allocate frame buffers */
  756. ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
  757. for (i = 0; i < ctx->num_internal_frames; i++) {
  758. ctx->internal_frames[i].size = q_data->sizeimage;
  759. if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
  760. ctx->internal_frames[i].size += width / 2 * height / 2;
  761. ctx->internal_frames[i].vaddr = dma_alloc_coherent(
  762. &dev->plat_dev->dev, ctx->internal_frames[i].size,
  763. &ctx->internal_frames[i].paddr, GFP_KERNEL);
  764. if (!ctx->internal_frames[i].vaddr) {
  765. coda_free_framebuffers(ctx);
  766. return -ENOMEM;
  767. }
  768. }
  769. /* Register frame buffers in the parameter buffer */
  770. p = ctx->parabuf.vaddr;
  771. if (dev->devtype->product == CODA_DX6) {
  772. for (i = 0; i < ctx->num_internal_frames; i++) {
  773. p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
  774. p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
  775. p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
  776. }
  777. } else {
  778. for (i = 0; i < ctx->num_internal_frames; i += 2) {
  779. p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
  780. p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
  781. p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
  782. if (fourcc == V4L2_PIX_FMT_H264)
  783. p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
  784. if (i + 1 < ctx->num_internal_frames) {
  785. p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
  786. p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
  787. p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
  788. if (fourcc == V4L2_PIX_FMT_H264)
  789. p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
  790. }
  791. }
  792. }
  793. return 0;
  794. }
  795. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  796. {
  797. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  798. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  799. u32 bitstream_buf, bitstream_size;
  800. struct coda_dev *dev = ctx->dev;
  801. struct coda_q_data *q_data_src, *q_data_dst;
  802. struct vb2_buffer *buf;
  803. u32 dst_fourcc;
  804. u32 value;
  805. int ret;
  806. if (count < 1)
  807. return -EINVAL;
  808. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  809. ctx->rawstreamon = 1;
  810. else
  811. ctx->compstreamon = 1;
  812. /* Don't start the coda unless both queues are on */
  813. if (!(ctx->rawstreamon & ctx->compstreamon))
  814. return 0;
  815. if (coda_isbusy(dev))
  816. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0)
  817. return -EBUSY;
  818. ctx->gopcounter = ctx->params.gop_size - 1;
  819. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  820. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  821. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  822. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  823. bitstream_size = q_data_dst->sizeimage;
  824. dst_fourcc = q_data_dst->fmt->fourcc;
  825. /* Find out whether coda must encode or decode */
  826. if (q_data_src->fmt->type == CODA_FMT_RAW &&
  827. q_data_dst->fmt->type == CODA_FMT_ENC) {
  828. ctx->inst_type = CODA_INST_ENCODER;
  829. } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
  830. q_data_dst->fmt->type == CODA_FMT_RAW) {
  831. ctx->inst_type = CODA_INST_DECODER;
  832. v4l2_err(v4l2_dev, "decoding not supported.\n");
  833. return -EINVAL;
  834. } else {
  835. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  836. return -EINVAL;
  837. }
  838. if (!coda_is_initialized(dev)) {
  839. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  840. return -EFAULT;
  841. }
  842. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  843. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
  844. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
  845. switch (dev->devtype->product) {
  846. case CODA_DX6:
  847. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  848. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  849. break;
  850. default:
  851. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  852. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  853. }
  854. if (dev->devtype->product == CODA_DX6) {
  855. /* Configure the coda */
  856. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  857. }
  858. /* Could set rotation here if needed */
  859. switch (dev->devtype->product) {
  860. case CODA_DX6:
  861. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  862. break;
  863. default:
  864. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  865. }
  866. value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  867. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  868. coda_write(dev, ctx->params.framerate,
  869. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  870. switch (dst_fourcc) {
  871. case V4L2_PIX_FMT_MPEG4:
  872. if (dev->devtype->product == CODA_DX6)
  873. ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
  874. else
  875. ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
  876. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  877. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  878. break;
  879. case V4L2_PIX_FMT_H264:
  880. if (dev->devtype->product == CODA_DX6)
  881. ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
  882. else
  883. ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
  884. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  885. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  886. break;
  887. default:
  888. v4l2_err(v4l2_dev,
  889. "dst format (0x%08x) invalid.\n", dst_fourcc);
  890. return -EINVAL;
  891. }
  892. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  893. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  894. if (ctx->params.slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB)
  895. value |= 1 & CODA_SLICING_MODE_MASK;
  896. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  897. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  898. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  899. if (ctx->params.bitrate) {
  900. /* Rate control enabled */
  901. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  902. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  903. } else {
  904. value = 0;
  905. }
  906. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  907. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  908. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  909. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  910. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  911. /* set default gamma */
  912. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  913. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  914. value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
  915. value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
  916. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  917. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  918. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  919. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  920. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  921. if (dev->devtype->product == CODA_DX6) {
  922. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  923. } else {
  924. coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  925. coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  926. }
  927. }
  928. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  929. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  930. return -ETIMEDOUT;
  931. }
  932. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
  933. return -EFAULT;
  934. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  935. if (ret < 0)
  936. return ret;
  937. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  938. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  939. if (dev->devtype->product != CODA_DX6) {
  940. coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  941. coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  942. coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  943. coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  944. coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  945. coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  946. }
  947. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  948. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  949. return -ETIMEDOUT;
  950. }
  951. /* Save stream headers */
  952. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  953. switch (dst_fourcc) {
  954. case V4L2_PIX_FMT_H264:
  955. /*
  956. * Get SPS in the first frame and copy it to an
  957. * intermediate buffer.
  958. */
  959. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  960. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  961. coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
  962. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  963. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  964. return -ETIMEDOUT;
  965. }
  966. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  967. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  968. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  969. ctx->vpu_header_size[0]);
  970. /*
  971. * Get PPS in the first frame and copy it to an
  972. * intermediate buffer.
  973. */
  974. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  975. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  976. coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
  977. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  978. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  979. return -ETIMEDOUT;
  980. }
  981. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  982. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  983. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  984. ctx->vpu_header_size[1]);
  985. ctx->vpu_header_size[2] = 0;
  986. break;
  987. case V4L2_PIX_FMT_MPEG4:
  988. /*
  989. * Get VOS in the first frame and copy it to an
  990. * intermediate buffer
  991. */
  992. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  993. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  994. coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
  995. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  996. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  997. return -ETIMEDOUT;
  998. }
  999. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1000. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1001. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1002. ctx->vpu_header_size[0]);
  1003. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1004. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1005. coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
  1006. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1007. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1008. return -ETIMEDOUT;
  1009. }
  1010. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1011. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1012. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1013. ctx->vpu_header_size[1]);
  1014. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1015. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1016. coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
  1017. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1018. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1019. return -ETIMEDOUT;
  1020. }
  1021. ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1022. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1023. memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
  1024. ctx->vpu_header_size[2]);
  1025. break;
  1026. default:
  1027. /* No more formats need to save headers at the moment */
  1028. break;
  1029. }
  1030. return 0;
  1031. }
  1032. static int coda_stop_streaming(struct vb2_queue *q)
  1033. {
  1034. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1035. struct coda_dev *dev = ctx->dev;
  1036. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1037. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1038. "%s: output\n", __func__);
  1039. ctx->rawstreamon = 0;
  1040. } else {
  1041. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1042. "%s: capture\n", __func__);
  1043. ctx->compstreamon = 0;
  1044. }
  1045. /* Don't stop the coda unless both queues are off */
  1046. if (ctx->rawstreamon || ctx->compstreamon)
  1047. return 0;
  1048. if (coda_isbusy(dev)) {
  1049. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0) {
  1050. v4l2_warn(&dev->v4l2_dev,
  1051. "%s: timeout, sending SEQ_END anyway\n", __func__);
  1052. }
  1053. }
  1054. cancel_delayed_work(&dev->timeout);
  1055. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1056. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1057. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1058. v4l2_err(&dev->v4l2_dev,
  1059. "CODA_COMMAND_SEQ_END failed\n");
  1060. return -ETIMEDOUT;
  1061. }
  1062. coda_free_framebuffers(ctx);
  1063. return 0;
  1064. }
  1065. static struct vb2_ops coda_qops = {
  1066. .queue_setup = coda_queue_setup,
  1067. .buf_prepare = coda_buf_prepare,
  1068. .buf_queue = coda_buf_queue,
  1069. .wait_prepare = coda_wait_prepare,
  1070. .wait_finish = coda_wait_finish,
  1071. .start_streaming = coda_start_streaming,
  1072. .stop_streaming = coda_stop_streaming,
  1073. };
  1074. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1075. {
  1076. struct coda_ctx *ctx =
  1077. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1078. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1079. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1080. switch (ctrl->id) {
  1081. case V4L2_CID_HFLIP:
  1082. if (ctrl->val)
  1083. ctx->params.rot_mode |= CODA_MIR_HOR;
  1084. else
  1085. ctx->params.rot_mode &= ~CODA_MIR_HOR;
  1086. break;
  1087. case V4L2_CID_VFLIP:
  1088. if (ctrl->val)
  1089. ctx->params.rot_mode |= CODA_MIR_VER;
  1090. else
  1091. ctx->params.rot_mode &= ~CODA_MIR_VER;
  1092. break;
  1093. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1094. ctx->params.bitrate = ctrl->val / 1000;
  1095. break;
  1096. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1097. ctx->params.gop_size = ctrl->val;
  1098. break;
  1099. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1100. ctx->params.h264_intra_qp = ctrl->val;
  1101. break;
  1102. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1103. ctx->params.h264_inter_qp = ctrl->val;
  1104. break;
  1105. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1106. ctx->params.mpeg4_intra_qp = ctrl->val;
  1107. break;
  1108. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1109. ctx->params.mpeg4_inter_qp = ctrl->val;
  1110. break;
  1111. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1112. ctx->params.slice_mode = ctrl->val;
  1113. break;
  1114. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1115. ctx->params.slice_max_mb = ctrl->val;
  1116. break;
  1117. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1118. break;
  1119. default:
  1120. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1121. "Invalid control, id=%d, val=%d\n",
  1122. ctrl->id, ctrl->val);
  1123. return -EINVAL;
  1124. }
  1125. return 0;
  1126. }
  1127. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1128. .s_ctrl = coda_s_ctrl,
  1129. };
  1130. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1131. {
  1132. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1133. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1134. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1135. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1136. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1137. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1138. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1139. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1140. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1141. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1142. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1143. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1144. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1145. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1146. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1147. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1148. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1149. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1150. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1151. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB, 0,
  1152. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB);
  1153. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1154. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1155. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1156. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1157. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1158. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1159. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1160. if (ctx->ctrls.error) {
  1161. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1162. ctx->ctrls.error);
  1163. return -EINVAL;
  1164. }
  1165. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1166. }
  1167. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1168. struct vb2_queue *dst_vq)
  1169. {
  1170. struct coda_ctx *ctx = priv;
  1171. int ret;
  1172. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1173. src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1174. src_vq->drv_priv = ctx;
  1175. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1176. src_vq->ops = &coda_qops;
  1177. src_vq->mem_ops = &vb2_dma_contig_memops;
  1178. ret = vb2_queue_init(src_vq);
  1179. if (ret)
  1180. return ret;
  1181. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1182. dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1183. dst_vq->drv_priv = ctx;
  1184. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1185. dst_vq->ops = &coda_qops;
  1186. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1187. return vb2_queue_init(dst_vq);
  1188. }
  1189. static int coda_next_free_instance(struct coda_dev *dev)
  1190. {
  1191. return ffz(dev->instance_mask);
  1192. }
  1193. static int coda_open(struct file *file)
  1194. {
  1195. struct coda_dev *dev = video_drvdata(file);
  1196. struct coda_ctx *ctx = NULL;
  1197. int ret = 0;
  1198. int idx;
  1199. idx = coda_next_free_instance(dev);
  1200. if (idx >= CODA_MAX_INSTANCES)
  1201. return -EBUSY;
  1202. set_bit(idx, &dev->instance_mask);
  1203. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1204. if (!ctx)
  1205. return -ENOMEM;
  1206. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1207. file->private_data = &ctx->fh;
  1208. v4l2_fh_add(&ctx->fh);
  1209. ctx->dev = dev;
  1210. ctx->idx = idx;
  1211. set_default_params(ctx);
  1212. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1213. &coda_queue_init);
  1214. if (IS_ERR(ctx->m2m_ctx)) {
  1215. int ret = PTR_ERR(ctx->m2m_ctx);
  1216. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1217. __func__, ret);
  1218. goto err;
  1219. }
  1220. ret = coda_ctrls_setup(ctx);
  1221. if (ret) {
  1222. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1223. goto err;
  1224. }
  1225. ctx->fh.ctrl_handler = &ctx->ctrls;
  1226. ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
  1227. CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
  1228. if (!ctx->parabuf.vaddr) {
  1229. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1230. ret = -ENOMEM;
  1231. goto err;
  1232. }
  1233. coda_lock(ctx);
  1234. list_add(&ctx->list, &dev->instances);
  1235. coda_unlock(ctx);
  1236. clk_prepare_enable(dev->clk_per);
  1237. clk_prepare_enable(dev->clk_ahb);
  1238. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1239. ctx->idx, ctx);
  1240. return 0;
  1241. err:
  1242. v4l2_fh_del(&ctx->fh);
  1243. v4l2_fh_exit(&ctx->fh);
  1244. kfree(ctx);
  1245. return ret;
  1246. }
  1247. static int coda_release(struct file *file)
  1248. {
  1249. struct coda_dev *dev = video_drvdata(file);
  1250. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1251. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1252. ctx);
  1253. coda_lock(ctx);
  1254. list_del(&ctx->list);
  1255. coda_unlock(ctx);
  1256. dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
  1257. ctx->parabuf.vaddr, ctx->parabuf.paddr);
  1258. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1259. v4l2_ctrl_handler_free(&ctx->ctrls);
  1260. clk_disable_unprepare(dev->clk_per);
  1261. clk_disable_unprepare(dev->clk_ahb);
  1262. v4l2_fh_del(&ctx->fh);
  1263. v4l2_fh_exit(&ctx->fh);
  1264. clear_bit(ctx->idx, &dev->instance_mask);
  1265. kfree(ctx);
  1266. return 0;
  1267. }
  1268. static unsigned int coda_poll(struct file *file,
  1269. struct poll_table_struct *wait)
  1270. {
  1271. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1272. int ret;
  1273. coda_lock(ctx);
  1274. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1275. coda_unlock(ctx);
  1276. return ret;
  1277. }
  1278. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1279. {
  1280. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1281. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1282. }
  1283. static const struct v4l2_file_operations coda_fops = {
  1284. .owner = THIS_MODULE,
  1285. .open = coda_open,
  1286. .release = coda_release,
  1287. .poll = coda_poll,
  1288. .unlocked_ioctl = video_ioctl2,
  1289. .mmap = coda_mmap,
  1290. };
  1291. static irqreturn_t coda_irq_handler(int irq, void *data)
  1292. {
  1293. struct vb2_buffer *src_buf, *dst_buf;
  1294. struct coda_dev *dev = data;
  1295. u32 wr_ptr, start_ptr;
  1296. struct coda_ctx *ctx;
  1297. __cancel_delayed_work(&dev->timeout);
  1298. /* read status register to attend the IRQ */
  1299. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1300. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1301. CODA_REG_BIT_INT_CLEAR);
  1302. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1303. if (ctx == NULL) {
  1304. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1305. return IRQ_HANDLED;
  1306. }
  1307. if (ctx->aborting) {
  1308. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1309. "task has been aborted\n");
  1310. return IRQ_HANDLED;
  1311. }
  1312. if (coda_isbusy(ctx->dev)) {
  1313. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1314. "coda is still busy!!!!\n");
  1315. return IRQ_NONE;
  1316. }
  1317. complete(&dev->done);
  1318. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1319. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1320. /* Get results from the coda */
  1321. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1322. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1323. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
  1324. /* Calculate bytesused field */
  1325. if (dst_buf->v4l2_buf.sequence == 0) {
  1326. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
  1327. ctx->vpu_header_size[0] +
  1328. ctx->vpu_header_size[1] +
  1329. ctx->vpu_header_size[2];
  1330. } else {
  1331. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
  1332. }
  1333. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1334. wr_ptr - start_ptr);
  1335. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1336. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1337. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1338. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1339. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1340. } else {
  1341. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1342. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1343. }
  1344. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1345. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1346. ctx->gopcounter--;
  1347. if (ctx->gopcounter < 0)
  1348. ctx->gopcounter = ctx->params.gop_size - 1;
  1349. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1350. "job finished: encoding frame (%d) (%s)\n",
  1351. dst_buf->v4l2_buf.sequence,
  1352. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1353. "KEYFRAME" : "PFRAME");
  1354. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1355. return IRQ_HANDLED;
  1356. }
  1357. static void coda_timeout(struct work_struct *work)
  1358. {
  1359. struct coda_ctx *ctx;
  1360. struct coda_dev *dev = container_of(to_delayed_work(work),
  1361. struct coda_dev, timeout);
  1362. if (completion_done(&dev->done))
  1363. return;
  1364. complete(&dev->done);
  1365. v4l2_err(&dev->v4l2_dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1366. mutex_lock(&dev->dev_mutex);
  1367. list_for_each_entry(ctx, &dev->instances, list) {
  1368. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1369. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1370. }
  1371. mutex_unlock(&dev->dev_mutex);
  1372. }
  1373. static u32 coda_supported_firmwares[] = {
  1374. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1375. CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
  1376. };
  1377. static bool coda_firmware_supported(u32 vernum)
  1378. {
  1379. int i;
  1380. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1381. if (vernum == coda_supported_firmwares[i])
  1382. return true;
  1383. return false;
  1384. }
  1385. static char *coda_product_name(int product)
  1386. {
  1387. static char buf[9];
  1388. switch (product) {
  1389. case CODA_DX6:
  1390. return "CodaDx6";
  1391. case CODA_7541:
  1392. return "CODA7541";
  1393. default:
  1394. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1395. return buf;
  1396. }
  1397. }
  1398. static int coda_hw_init(struct coda_dev *dev)
  1399. {
  1400. u16 product, major, minor, release;
  1401. u32 data;
  1402. u16 *p;
  1403. int i;
  1404. clk_prepare_enable(dev->clk_per);
  1405. clk_prepare_enable(dev->clk_ahb);
  1406. /*
  1407. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1408. * The 16-bit chars in the code buffer are in memory access
  1409. * order, re-sort them to CODA order for register download.
  1410. * Data in this SRAM survives a reboot.
  1411. */
  1412. p = (u16 *)dev->codebuf.vaddr;
  1413. if (dev->devtype->product == CODA_DX6) {
  1414. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1415. data = CODA_DOWN_ADDRESS_SET(i) |
  1416. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1417. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1418. }
  1419. } else {
  1420. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1421. data = CODA_DOWN_ADDRESS_SET(i) |
  1422. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1423. 3 - (i % 4)]);
  1424. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1425. }
  1426. }
  1427. /* Tell the BIT where to find everything it needs */
  1428. coda_write(dev, dev->workbuf.paddr,
  1429. CODA_REG_BIT_WORK_BUF_ADDR);
  1430. coda_write(dev, dev->codebuf.paddr,
  1431. CODA_REG_BIT_CODE_BUF_ADDR);
  1432. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1433. /* Set default values */
  1434. switch (dev->devtype->product) {
  1435. case CODA_DX6:
  1436. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1437. break;
  1438. default:
  1439. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1440. }
  1441. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1442. if (dev->devtype->product != CODA_DX6)
  1443. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1444. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1445. CODA_REG_BIT_INT_ENABLE);
  1446. /* Reset VPU and start processor */
  1447. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1448. data |= CODA_REG_RESET_ENABLE;
  1449. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1450. udelay(10);
  1451. data &= ~CODA_REG_RESET_ENABLE;
  1452. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1453. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1454. /* Load firmware */
  1455. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1456. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1457. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1458. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1459. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1460. if (coda_wait_timeout(dev)) {
  1461. clk_disable_unprepare(dev->clk_per);
  1462. clk_disable_unprepare(dev->clk_ahb);
  1463. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1464. return -EIO;
  1465. }
  1466. /* Check we are compatible with the loaded firmware */
  1467. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1468. product = CODA_FIRMWARE_PRODUCT(data);
  1469. major = CODA_FIRMWARE_MAJOR(data);
  1470. minor = CODA_FIRMWARE_MINOR(data);
  1471. release = CODA_FIRMWARE_RELEASE(data);
  1472. clk_disable_unprepare(dev->clk_per);
  1473. clk_disable_unprepare(dev->clk_ahb);
  1474. if (product != dev->devtype->product) {
  1475. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1476. " Version: %u.%u.%u\n",
  1477. coda_product_name(dev->devtype->product),
  1478. coda_product_name(product), major, minor, release);
  1479. return -EINVAL;
  1480. }
  1481. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1482. coda_product_name(product));
  1483. if (coda_firmware_supported(data)) {
  1484. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1485. major, minor, release);
  1486. } else {
  1487. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1488. "%u.%u.%u\n", major, minor, release);
  1489. }
  1490. return 0;
  1491. }
  1492. static void coda_fw_callback(const struct firmware *fw, void *context)
  1493. {
  1494. struct coda_dev *dev = context;
  1495. struct platform_device *pdev = dev->plat_dev;
  1496. int ret;
  1497. if (!fw) {
  1498. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1499. return;
  1500. }
  1501. /* allocate auxiliary per-device code buffer for the BIT processor */
  1502. dev->codebuf.size = fw->size;
  1503. dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
  1504. &dev->codebuf.paddr,
  1505. GFP_KERNEL);
  1506. if (!dev->codebuf.vaddr) {
  1507. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1508. return;
  1509. }
  1510. /* Copy the whole firmware image to the code buffer */
  1511. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1512. release_firmware(fw);
  1513. ret = coda_hw_init(dev);
  1514. if (ret) {
  1515. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1516. return;
  1517. }
  1518. dev->vfd.fops = &coda_fops,
  1519. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1520. dev->vfd.release = video_device_release_empty,
  1521. dev->vfd.lock = &dev->dev_mutex;
  1522. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1523. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1524. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1525. video_set_drvdata(&dev->vfd, dev);
  1526. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1527. if (IS_ERR(dev->alloc_ctx)) {
  1528. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1529. return;
  1530. }
  1531. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1532. if (IS_ERR(dev->m2m_dev)) {
  1533. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1534. goto rel_ctx;
  1535. }
  1536. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1537. if (ret) {
  1538. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1539. goto rel_m2m;
  1540. }
  1541. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1542. dev->vfd.num);
  1543. return;
  1544. rel_m2m:
  1545. v4l2_m2m_release(dev->m2m_dev);
  1546. rel_ctx:
  1547. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1548. }
  1549. static int coda_firmware_request(struct coda_dev *dev)
  1550. {
  1551. char *fw = dev->devtype->firmware;
  1552. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1553. coda_product_name(dev->devtype->product));
  1554. return request_firmware_nowait(THIS_MODULE, true,
  1555. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1556. }
  1557. enum coda_platform {
  1558. CODA_IMX27,
  1559. CODA_IMX53,
  1560. };
  1561. static const struct coda_devtype coda_devdata[] = {
  1562. [CODA_IMX27] = {
  1563. .firmware = "v4l-codadx6-imx27.bin",
  1564. .product = CODA_DX6,
  1565. .formats = codadx6_formats,
  1566. .num_formats = ARRAY_SIZE(codadx6_formats),
  1567. },
  1568. [CODA_IMX53] = {
  1569. .firmware = "v4l-coda7541-imx53.bin",
  1570. .product = CODA_7541,
  1571. .formats = coda7_formats,
  1572. .num_formats = ARRAY_SIZE(coda7_formats),
  1573. },
  1574. };
  1575. static struct platform_device_id coda_platform_ids[] = {
  1576. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  1577. { .name = "coda-imx53", .driver_data = CODA_7541 },
  1578. { /* sentinel */ }
  1579. };
  1580. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  1581. #ifdef CONFIG_OF
  1582. static const struct of_device_id coda_dt_ids[] = {
  1583. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  1584. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  1585. { /* sentinel */ }
  1586. };
  1587. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  1588. #endif
  1589. static int __devinit coda_probe(struct platform_device *pdev)
  1590. {
  1591. const struct of_device_id *of_id =
  1592. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  1593. const struct platform_device_id *pdev_id;
  1594. struct coda_dev *dev;
  1595. struct resource *res;
  1596. int ret, irq;
  1597. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  1598. if (!dev) {
  1599. dev_err(&pdev->dev, "Not enough memory for %s\n",
  1600. CODA_NAME);
  1601. return -ENOMEM;
  1602. }
  1603. spin_lock_init(&dev->irqlock);
  1604. INIT_LIST_HEAD(&dev->instances);
  1605. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  1606. init_completion(&dev->done);
  1607. complete(&dev->done);
  1608. dev->plat_dev = pdev;
  1609. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  1610. if (IS_ERR(dev->clk_per)) {
  1611. dev_err(&pdev->dev, "Could not get per clock\n");
  1612. return PTR_ERR(dev->clk_per);
  1613. }
  1614. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1615. if (IS_ERR(dev->clk_ahb)) {
  1616. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1617. return PTR_ERR(dev->clk_ahb);
  1618. }
  1619. /* Get memory for physical registers */
  1620. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1621. if (res == NULL) {
  1622. dev_err(&pdev->dev, "failed to get memory region resource\n");
  1623. return -ENOENT;
  1624. }
  1625. if (devm_request_mem_region(&pdev->dev, res->start,
  1626. resource_size(res), CODA_NAME) == NULL) {
  1627. dev_err(&pdev->dev, "failed to request memory region\n");
  1628. return -ENOENT;
  1629. }
  1630. dev->regs_base = devm_ioremap(&pdev->dev, res->start,
  1631. resource_size(res));
  1632. if (!dev->regs_base) {
  1633. dev_err(&pdev->dev, "failed to ioremap address region\n");
  1634. return -ENOENT;
  1635. }
  1636. /* IRQ */
  1637. irq = platform_get_irq(pdev, 0);
  1638. if (irq < 0) {
  1639. dev_err(&pdev->dev, "failed to get irq resource\n");
  1640. return -ENOENT;
  1641. }
  1642. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  1643. 0, CODA_NAME, dev) < 0) {
  1644. dev_err(&pdev->dev, "failed to request irq\n");
  1645. return -ENOENT;
  1646. }
  1647. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1648. if (ret)
  1649. return ret;
  1650. mutex_init(&dev->dev_mutex);
  1651. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  1652. if (of_id) {
  1653. dev->devtype = of_id->data;
  1654. } else if (pdev_id) {
  1655. dev->devtype = &coda_devdata[pdev_id->driver_data];
  1656. } else {
  1657. v4l2_device_unregister(&dev->v4l2_dev);
  1658. return -EINVAL;
  1659. }
  1660. /* allocate auxiliary per-device buffers for the BIT processor */
  1661. switch (dev->devtype->product) {
  1662. case CODA_DX6:
  1663. dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
  1664. break;
  1665. default:
  1666. dev->workbuf.size = CODA7_WORK_BUF_SIZE;
  1667. }
  1668. dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
  1669. &dev->workbuf.paddr,
  1670. GFP_KERNEL);
  1671. if (!dev->workbuf.vaddr) {
  1672. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  1673. v4l2_device_unregister(&dev->v4l2_dev);
  1674. return -ENOMEM;
  1675. }
  1676. if (dev->devtype->product == CODA_DX6) {
  1677. dev->iram_paddr = 0xffff4c00;
  1678. } else {
  1679. void __iomem *iram_vaddr;
  1680. iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
  1681. &dev->iram_paddr);
  1682. if (!iram_vaddr) {
  1683. dev_err(&pdev->dev, "unable to alloc iram\n");
  1684. return -ENOMEM;
  1685. }
  1686. }
  1687. platform_set_drvdata(pdev, dev);
  1688. return coda_firmware_request(dev);
  1689. }
  1690. static int coda_remove(struct platform_device *pdev)
  1691. {
  1692. struct coda_dev *dev = platform_get_drvdata(pdev);
  1693. video_unregister_device(&dev->vfd);
  1694. if (dev->m2m_dev)
  1695. v4l2_m2m_release(dev->m2m_dev);
  1696. if (dev->alloc_ctx)
  1697. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1698. v4l2_device_unregister(&dev->v4l2_dev);
  1699. if (dev->iram_paddr)
  1700. iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
  1701. if (dev->codebuf.vaddr)
  1702. dma_free_coherent(&pdev->dev, dev->codebuf.size,
  1703. &dev->codebuf.vaddr, dev->codebuf.paddr);
  1704. if (dev->workbuf.vaddr)
  1705. dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
  1706. dev->workbuf.paddr);
  1707. return 0;
  1708. }
  1709. static struct platform_driver coda_driver = {
  1710. .probe = coda_probe,
  1711. .remove = __devexit_p(coda_remove),
  1712. .driver = {
  1713. .name = CODA_NAME,
  1714. .owner = THIS_MODULE,
  1715. .of_match_table = of_match_ptr(coda_dt_ids),
  1716. },
  1717. .id_table = coda_platform_ids,
  1718. };
  1719. module_platform_driver(coda_driver);
  1720. MODULE_LICENSE("GPL");
  1721. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  1722. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");