mpc5200_dma.c 16 KB

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  1. /*
  2. * Freescale MPC5200 PSC DMA
  3. * ALSA SoC Platform driver
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. * Copyright (C) 2009 Jon Smirl, Digispeaker
  7. */
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <sound/soc.h>
  11. #include <sysdev/bestcomm/bestcomm.h>
  12. #include <sysdev/bestcomm/gen_bd.h>
  13. #include <asm/mpc52xx_psc.h>
  14. #include "mpc5200_dma.h"
  15. /*
  16. * Interrupt handlers
  17. */
  18. static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
  19. {
  20. struct psc_dma *psc_dma = _psc_dma;
  21. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  22. u16 isr;
  23. isr = in_be16(&regs->mpc52xx_psc_isr);
  24. /* Playback underrun error */
  25. if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
  26. psc_dma->stats.underrun_count++;
  27. /* Capture overrun error */
  28. if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
  29. psc_dma->stats.overrun_count++;
  30. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  31. return IRQ_HANDLED;
  32. }
  33. /**
  34. * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
  35. * @s: pointer to stream private data structure
  36. *
  37. * Enqueues another audio period buffer into the bestcomm queue.
  38. *
  39. * Note: The routine must only be called when there is space available in
  40. * the queue. Otherwise the enqueue will fail and the audio ring buffer
  41. * will get out of sync
  42. */
  43. static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
  44. {
  45. struct bcom_bd *bd;
  46. /* Prepare and enqueue the next buffer descriptor */
  47. bd = bcom_prepare_next_buffer(s->bcom_task);
  48. bd->status = s->period_bytes;
  49. bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
  50. bcom_submit_next_buffer(s->bcom_task, NULL);
  51. /* Update for next period */
  52. s->period_next = (s->period_next + 1) % s->runtime->periods;
  53. }
  54. static void psc_dma_bcom_enqueue_tx(struct psc_dma_stream *s)
  55. {
  56. if (s->appl_ptr > s->runtime->control->appl_ptr) {
  57. /*
  58. * In this case s->runtime->control->appl_ptr has wrapped around.
  59. * Play the data to the end of the boundary, then wrap our own
  60. * appl_ptr back around.
  61. */
  62. while (s->appl_ptr < s->runtime->boundary) {
  63. if (bcom_queue_full(s->bcom_task))
  64. return;
  65. s->appl_ptr += s->runtime->period_size;
  66. psc_dma_bcom_enqueue_next_buffer(s);
  67. }
  68. s->appl_ptr -= s->runtime->boundary;
  69. }
  70. while (s->appl_ptr < s->runtime->control->appl_ptr) {
  71. if (bcom_queue_full(s->bcom_task))
  72. return;
  73. s->appl_ptr += s->runtime->period_size;
  74. psc_dma_bcom_enqueue_next_buffer(s);
  75. }
  76. }
  77. /* Bestcomm DMA irq handler */
  78. static irqreturn_t psc_dma_bcom_irq_tx(int irq, void *_psc_dma_stream)
  79. {
  80. struct psc_dma_stream *s = _psc_dma_stream;
  81. spin_lock(&s->psc_dma->lock);
  82. /* For each finished period, dequeue the completed period buffer
  83. * and enqueue a new one in it's place. */
  84. while (bcom_buffer_done(s->bcom_task)) {
  85. bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
  86. s->period_current = (s->period_current+1) % s->runtime->periods;
  87. }
  88. psc_dma_bcom_enqueue_tx(s);
  89. spin_unlock(&s->psc_dma->lock);
  90. /* If the stream is active, then also inform the PCM middle layer
  91. * of the period finished event. */
  92. if (s->active)
  93. snd_pcm_period_elapsed(s->stream);
  94. return IRQ_HANDLED;
  95. }
  96. static irqreturn_t psc_dma_bcom_irq_rx(int irq, void *_psc_dma_stream)
  97. {
  98. struct psc_dma_stream *s = _psc_dma_stream;
  99. spin_lock(&s->psc_dma->lock);
  100. /* For each finished period, dequeue the completed period buffer
  101. * and enqueue a new one in it's place. */
  102. while (bcom_buffer_done(s->bcom_task)) {
  103. bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
  104. s->period_current = (s->period_current+1) % s->runtime->periods;
  105. psc_dma_bcom_enqueue_next_buffer(s);
  106. }
  107. spin_unlock(&s->psc_dma->lock);
  108. /* If the stream is active, then also inform the PCM middle layer
  109. * of the period finished event. */
  110. if (s->active)
  111. snd_pcm_period_elapsed(s->stream);
  112. return IRQ_HANDLED;
  113. }
  114. static int psc_dma_hw_free(struct snd_pcm_substream *substream)
  115. {
  116. snd_pcm_set_runtime_buffer(substream, NULL);
  117. return 0;
  118. }
  119. /**
  120. * psc_dma_trigger: start and stop the DMA transfer.
  121. *
  122. * This function is called by ALSA to start, stop, pause, and resume the DMA
  123. * transfer of data.
  124. */
  125. static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
  126. {
  127. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  128. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  129. struct snd_pcm_runtime *runtime = substream->runtime;
  130. struct psc_dma_stream *s;
  131. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  132. u16 imr;
  133. unsigned long flags;
  134. int i;
  135. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  136. s = &psc_dma->capture;
  137. else
  138. s = &psc_dma->playback;
  139. dev_dbg(psc_dma->dev, "psc_dma_trigger(substream=%p, cmd=%i)"
  140. " stream_id=%i\n",
  141. substream, cmd, substream->pstr->stream);
  142. switch (cmd) {
  143. case SNDRV_PCM_TRIGGER_START:
  144. s->period_bytes = frames_to_bytes(runtime,
  145. runtime->period_size);
  146. s->period_next = 0;
  147. s->period_current = 0;
  148. s->active = 1;
  149. /* track appl_ptr so that we have a better chance of detecting
  150. * end of stream and not over running it.
  151. */
  152. s->runtime = runtime;
  153. s->appl_ptr = s->runtime->control->appl_ptr -
  154. (runtime->period_size * runtime->periods);
  155. /* Fill up the bestcomm bd queue and enable DMA.
  156. * This will begin filling the PSC's fifo.
  157. */
  158. spin_lock_irqsave(&psc_dma->lock, flags);
  159. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
  160. bcom_gen_bd_rx_reset(s->bcom_task);
  161. for (i = 0; i < runtime->periods; i++)
  162. if (!bcom_queue_full(s->bcom_task))
  163. psc_dma_bcom_enqueue_next_buffer(s);
  164. } else {
  165. bcom_gen_bd_tx_reset(s->bcom_task);
  166. psc_dma_bcom_enqueue_tx(s);
  167. }
  168. bcom_enable(s->bcom_task);
  169. spin_unlock_irqrestore(&psc_dma->lock, flags);
  170. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  171. break;
  172. case SNDRV_PCM_TRIGGER_STOP:
  173. s->active = 0;
  174. spin_lock_irqsave(&psc_dma->lock, flags);
  175. bcom_disable(s->bcom_task);
  176. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  177. bcom_gen_bd_rx_reset(s->bcom_task);
  178. else
  179. bcom_gen_bd_tx_reset(s->bcom_task);
  180. spin_unlock_irqrestore(&psc_dma->lock, flags);
  181. break;
  182. default:
  183. dev_dbg(psc_dma->dev, "invalid command\n");
  184. return -EINVAL;
  185. }
  186. /* Update interrupt enable settings */
  187. imr = 0;
  188. if (psc_dma->playback.active)
  189. imr |= MPC52xx_PSC_IMR_TXEMP;
  190. if (psc_dma->capture.active)
  191. imr |= MPC52xx_PSC_IMR_ORERR;
  192. out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
  193. return 0;
  194. }
  195. /* ---------------------------------------------------------------------
  196. * The PSC DMA 'ASoC platform' driver
  197. *
  198. * Can be referenced by an 'ASoC machine' driver
  199. * This driver only deals with the audio bus; it doesn't have any
  200. * interaction with the attached codec
  201. */
  202. static const struct snd_pcm_hardware psc_dma_hardware = {
  203. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
  204. SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
  205. SNDRV_PCM_INFO_BATCH,
  206. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
  207. SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
  208. .rate_min = 8000,
  209. .rate_max = 48000,
  210. .channels_min = 1,
  211. .channels_max = 2,
  212. .period_bytes_max = 1024 * 1024,
  213. .period_bytes_min = 32,
  214. .periods_min = 2,
  215. .periods_max = 256,
  216. .buffer_bytes_max = 2 * 1024 * 1024,
  217. .fifo_size = 512,
  218. };
  219. static int psc_dma_open(struct snd_pcm_substream *substream)
  220. {
  221. struct snd_pcm_runtime *runtime = substream->runtime;
  222. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  223. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  224. struct psc_dma_stream *s;
  225. int rc;
  226. dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
  227. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  228. s = &psc_dma->capture;
  229. else
  230. s = &psc_dma->playback;
  231. snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
  232. rc = snd_pcm_hw_constraint_integer(runtime,
  233. SNDRV_PCM_HW_PARAM_PERIODS);
  234. if (rc < 0) {
  235. dev_err(substream->pcm->card->dev, "invalid buffer size\n");
  236. return rc;
  237. }
  238. s->stream = substream;
  239. return 0;
  240. }
  241. static int psc_dma_close(struct snd_pcm_substream *substream)
  242. {
  243. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  244. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  245. struct psc_dma_stream *s;
  246. dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
  247. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  248. s = &psc_dma->capture;
  249. else
  250. s = &psc_dma->playback;
  251. if (!psc_dma->playback.active &&
  252. !psc_dma->capture.active) {
  253. /* Disable all interrupts and reset the PSC */
  254. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  255. out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
  256. }
  257. s->stream = NULL;
  258. return 0;
  259. }
  260. static snd_pcm_uframes_t
  261. psc_dma_pointer(struct snd_pcm_substream *substream)
  262. {
  263. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  264. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  265. struct psc_dma_stream *s;
  266. dma_addr_t count;
  267. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  268. s = &psc_dma->capture;
  269. else
  270. s = &psc_dma->playback;
  271. count = s->period_current * s->period_bytes;
  272. return bytes_to_frames(substream->runtime, count);
  273. }
  274. static int
  275. psc_dma_hw_params(struct snd_pcm_substream *substream,
  276. struct snd_pcm_hw_params *params)
  277. {
  278. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  279. return 0;
  280. }
  281. static struct snd_pcm_ops psc_dma_ops = {
  282. .open = psc_dma_open,
  283. .close = psc_dma_close,
  284. .hw_free = psc_dma_hw_free,
  285. .ioctl = snd_pcm_lib_ioctl,
  286. .pointer = psc_dma_pointer,
  287. .trigger = psc_dma_trigger,
  288. .hw_params = psc_dma_hw_params,
  289. };
  290. static u64 psc_dma_dmamask = 0xffffffff;
  291. static int psc_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
  292. struct snd_pcm *pcm)
  293. {
  294. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  295. struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
  296. size_t size = psc_dma_hardware.buffer_bytes_max;
  297. int rc = 0;
  298. dev_dbg(rtd->socdev->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
  299. card, dai, pcm);
  300. if (!card->dev->dma_mask)
  301. card->dev->dma_mask = &psc_dma_dmamask;
  302. if (!card->dev->coherent_dma_mask)
  303. card->dev->coherent_dma_mask = 0xffffffff;
  304. if (pcm->streams[0].substream) {
  305. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  306. size, &pcm->streams[0].substream->dma_buffer);
  307. if (rc)
  308. goto playback_alloc_err;
  309. }
  310. if (pcm->streams[1].substream) {
  311. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  312. size, &pcm->streams[1].substream->dma_buffer);
  313. if (rc)
  314. goto capture_alloc_err;
  315. }
  316. if (rtd->socdev->card->codec->ac97)
  317. rtd->socdev->card->codec->ac97->private_data = psc_dma;
  318. return 0;
  319. capture_alloc_err:
  320. if (pcm->streams[0].substream)
  321. snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
  322. playback_alloc_err:
  323. dev_err(card->dev, "Cannot allocate buffer(s)\n");
  324. return -ENOMEM;
  325. }
  326. static void psc_dma_free(struct snd_pcm *pcm)
  327. {
  328. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  329. struct snd_pcm_substream *substream;
  330. int stream;
  331. dev_dbg(rtd->socdev->dev, "psc_dma_free(pcm=%p)\n", pcm);
  332. for (stream = 0; stream < 2; stream++) {
  333. substream = pcm->streams[stream].substream;
  334. if (substream) {
  335. snd_dma_free_pages(&substream->dma_buffer);
  336. substream->dma_buffer.area = NULL;
  337. substream->dma_buffer.addr = 0;
  338. }
  339. }
  340. }
  341. struct snd_soc_platform mpc5200_audio_dma_platform = {
  342. .name = "mpc5200-psc-audio",
  343. .pcm_ops = &psc_dma_ops,
  344. .pcm_new = &psc_dma_new,
  345. .pcm_free = &psc_dma_free,
  346. };
  347. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_platform);
  348. int mpc5200_audio_dma_create(struct of_device *op)
  349. {
  350. phys_addr_t fifo;
  351. struct psc_dma *psc_dma;
  352. struct resource res;
  353. int size, irq, rc;
  354. const __be32 *prop;
  355. void __iomem *regs;
  356. int ret;
  357. /* Fetch the registers and IRQ of the PSC */
  358. irq = irq_of_parse_and_map(op->node, 0);
  359. if (of_address_to_resource(op->node, 0, &res)) {
  360. dev_err(&op->dev, "Missing reg property\n");
  361. return -ENODEV;
  362. }
  363. regs = ioremap(res.start, 1 + res.end - res.start);
  364. if (!regs) {
  365. dev_err(&op->dev, "Could not map registers\n");
  366. return -ENODEV;
  367. }
  368. /* Allocate and initialize the driver private data */
  369. psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
  370. if (!psc_dma) {
  371. ret = -ENOMEM;
  372. goto out_unmap;
  373. }
  374. /* Get the PSC ID */
  375. prop = of_get_property(op->node, "cell-index", &size);
  376. if (!prop || size < sizeof *prop) {
  377. ret = -ENODEV;
  378. goto out_free;
  379. }
  380. spin_lock_init(&psc_dma->lock);
  381. mutex_init(&psc_dma->mutex);
  382. psc_dma->id = be32_to_cpu(*prop);
  383. psc_dma->irq = irq;
  384. psc_dma->psc_regs = regs;
  385. psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
  386. psc_dma->dev = &op->dev;
  387. psc_dma->playback.psc_dma = psc_dma;
  388. psc_dma->capture.psc_dma = psc_dma;
  389. snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
  390. /* Find the address of the fifo data registers and setup the
  391. * DMA tasks */
  392. fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
  393. psc_dma->capture.bcom_task =
  394. bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
  395. psc_dma->playback.bcom_task =
  396. bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
  397. if (!psc_dma->capture.bcom_task ||
  398. !psc_dma->playback.bcom_task) {
  399. dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
  400. ret = -ENODEV;
  401. goto out_free;
  402. }
  403. /* Disable all interrupts and reset the PSC */
  404. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  405. /* reset receiver */
  406. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
  407. /* reset transmitter */
  408. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
  409. /* reset error */
  410. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
  411. /* reset mode */
  412. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
  413. /* Set up mode register;
  414. * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
  415. * Second write: register Normal mode for non loopback
  416. */
  417. out_8(&psc_dma->psc_regs->mode, 0);
  418. out_8(&psc_dma->psc_regs->mode, 0);
  419. /* Set the TX and RX fifo alarm thresholds */
  420. out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
  421. out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
  422. out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
  423. out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
  424. /* Lookup the IRQ numbers */
  425. psc_dma->playback.irq =
  426. bcom_get_task_irq(psc_dma->playback.bcom_task);
  427. psc_dma->capture.irq =
  428. bcom_get_task_irq(psc_dma->capture.bcom_task);
  429. rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
  430. "psc-dma-status", psc_dma);
  431. rc |= request_irq(psc_dma->capture.irq,
  432. &psc_dma_bcom_irq_rx, IRQF_SHARED,
  433. "psc-dma-capture", &psc_dma->capture);
  434. rc |= request_irq(psc_dma->playback.irq,
  435. &psc_dma_bcom_irq_tx, IRQF_SHARED,
  436. "psc-dma-playback", &psc_dma->playback);
  437. if (rc) {
  438. ret = -ENODEV;
  439. goto out_irq;
  440. }
  441. /* Save what we've done so it can be found again later */
  442. dev_set_drvdata(&op->dev, psc_dma);
  443. /* Tell the ASoC OF helpers about it */
  444. return snd_soc_register_platform(&mpc5200_audio_dma_platform);
  445. out_irq:
  446. free_irq(psc_dma->irq, psc_dma);
  447. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  448. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  449. out_free:
  450. kfree(psc_dma);
  451. out_unmap:
  452. iounmap(regs);
  453. return ret;
  454. }
  455. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
  456. int mpc5200_audio_dma_destroy(struct of_device *op)
  457. {
  458. struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
  459. dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
  460. snd_soc_unregister_platform(&mpc5200_audio_dma_platform);
  461. bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
  462. bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
  463. /* Release irqs */
  464. free_irq(psc_dma->irq, psc_dma);
  465. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  466. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  467. iounmap(psc_dma->psc_regs);
  468. kfree(psc_dma);
  469. dev_set_drvdata(&op->dev, NULL);
  470. return 0;
  471. }
  472. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
  473. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  474. MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
  475. MODULE_LICENSE("GPL");