superio.c 14 KB

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  1. /* National Semiconductor NS87560UBD Super I/O controller used in
  2. * HP [BCJ]x000 workstations.
  3. *
  4. * This chip is a horrid piece of engineering, and National
  5. * denies any knowledge of its existence. Thus no datasheet is
  6. * available off www.national.com.
  7. *
  8. * (C) Copyright 2000 Linuxcare, Inc.
  9. * (C) Copyright 2000 Linuxcare Canada, Inc.
  10. * (C) Copyright 2000 Martin K. Petersen <mkp@linuxcare.com>
  11. * (C) Copyright 2000 Alex deVries <alex@onefishtwo.ca>
  12. * (C) Copyright 2001 John Marvin <jsm fc hp com>
  13. * (C) Copyright 2003 Grant Grundler <grundler parisc-linux org>
  14. * (C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org>
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * The initial version of this is by Martin Peterson. Alex deVries
  22. * has spent a bit of time trying to coax it into working.
  23. *
  24. * Major changes to get basic interrupt infrastructure working to
  25. * hopefully be able to support all SuperIO devices. Currently
  26. * works with serial. -- John Marvin <jsm@fc.hp.com>
  27. */
  28. /* NOTES:
  29. *
  30. * Function 0 is an IDE controller. It is identical to a PC87415 IDE
  31. * controller (and identifies itself as such).
  32. *
  33. * Function 1 is a "Legacy I/O" controller. Under this function is a
  34. * whole mess of legacy I/O peripherals. Of course, HP hasn't enabled
  35. * all the functionality in hardware, but the following is available:
  36. *
  37. * Two 16550A compatible serial controllers
  38. * An IEEE 1284 compatible parallel port
  39. * A floppy disk controller
  40. *
  41. * Function 2 is a USB controller.
  42. *
  43. * We must be incredibly careful during initialization. Since all
  44. * interrupts are routed through function 1 (which is not allowed by
  45. * the PCI spec), we need to program the PICs on the legacy I/O port
  46. * *before* we attempt to set up IDE and USB. @#$!&
  47. *
  48. * According to HP, devices are only enabled by firmware if they have
  49. * a physical device connected.
  50. *
  51. * Configuration register bits:
  52. * 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
  53. * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
  54. *
  55. */
  56. #include <linux/errno.h>
  57. #include <linux/init.h>
  58. #include <linux/module.h>
  59. #include <linux/types.h>
  60. #include <linux/interrupt.h>
  61. #include <linux/ioport.h>
  62. #include <linux/serial.h>
  63. #include <linux/pci.h>
  64. #include <linux/parport.h>
  65. #include <linux/parport_pc.h>
  66. #include <linux/termios.h>
  67. #include <linux/tty.h>
  68. #include <linux/serial_core.h>
  69. #include <linux/delay.h>
  70. #include <asm/io.h>
  71. #include <asm/hardware.h>
  72. #include <asm/superio.h>
  73. static struct superio_device sio_dev;
  74. #undef DEBUG_SUPERIO_INIT
  75. #ifdef DEBUG_SUPERIO_INIT
  76. #define DBG_INIT(x...) printk(x)
  77. #else
  78. #define DBG_INIT(x...)
  79. #endif
  80. static irqreturn_t
  81. superio_interrupt(int parent_irq, void *devp, struct pt_regs *regs)
  82. {
  83. u8 results;
  84. u8 local_irq;
  85. /* Poll the 8259 to see if there's an interrupt. */
  86. outb (OCW3_POLL,IC_PIC1+0);
  87. results = inb(IC_PIC1+0);
  88. /*
  89. * Bit 7: 1 = active Interrupt; 0 = no Interrupt pending
  90. * Bits 6-3: zero
  91. * Bits 2-0: highest priority, active requesting interrupt ID (0-7)
  92. */
  93. if ((results & 0x80) == 0) {
  94. /* I suspect "spurious" interrupts are from unmasking an IRQ.
  95. * We don't know if an interrupt was/is pending and thus
  96. * just call the handler for that IRQ as if it were pending.
  97. */
  98. return IRQ_NONE;
  99. }
  100. /* Check to see which device is interrupting */
  101. local_irq = results & 0x0f;
  102. if (local_irq == 2 || local_irq > 7) {
  103. printk(KERN_ERR "SuperIO: slave interrupted!\n");
  104. return IRQ_HANDLED;
  105. }
  106. if (local_irq == 7) {
  107. /* Could be spurious. Check in service bits */
  108. outb(OCW3_ISR,IC_PIC1+0);
  109. results = inb(IC_PIC1+0);
  110. if ((results & 0x80) == 0) { /* if ISR7 not set: spurious */
  111. printk(KERN_WARNING "SuperIO: spurious interrupt!\n");
  112. return IRQ_HANDLED;
  113. }
  114. }
  115. /* Call the appropriate device's interrupt */
  116. __do_IRQ(local_irq, regs);
  117. /* set EOI - forces a new interrupt if a lower priority device
  118. * still needs service.
  119. */
  120. outb((OCW2_SEOI|local_irq),IC_PIC1 + 0);
  121. return IRQ_HANDLED;
  122. }
  123. /* Initialize Super I/O device */
  124. static void __devinit
  125. superio_init(struct superio_device *sio)
  126. {
  127. struct pci_dev *pdev = sio->lio_pdev;
  128. u16 word;
  129. if (sio->suckyio_irq_enabled)
  130. return;
  131. if (!pdev) BUG();
  132. if (!sio->usb_pdev) BUG();
  133. /* use the IRQ iosapic found for USB INT D... */
  134. pdev->irq = sio->usb_pdev->irq;
  135. /* ...then properly fixup the USB to point at suckyio PIC */
  136. sio->usb_pdev->irq = superio_fixup_irq(sio->usb_pdev);
  137. printk (KERN_INFO "SuperIO: Found NS87560 Legacy I/O device at %s (IRQ %i) \n",
  138. pci_name(pdev),pdev->irq);
  139. pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base);
  140. sio->sp1_base &= ~1;
  141. printk (KERN_INFO "SuperIO: Serial port 1 at 0x%x\n", sio->sp1_base);
  142. pci_read_config_dword (pdev, SIO_SP2BAR, &sio->sp2_base);
  143. sio->sp2_base &= ~1;
  144. printk (KERN_INFO "SuperIO: Serial port 2 at 0x%x\n", sio->sp2_base);
  145. pci_read_config_dword (pdev, SIO_PPBAR, &sio->pp_base);
  146. sio->pp_base &= ~1;
  147. printk (KERN_INFO "SuperIO: Parallel port at 0x%x\n", sio->pp_base);
  148. pci_read_config_dword (pdev, SIO_FDCBAR, &sio->fdc_base);
  149. sio->fdc_base &= ~1;
  150. printk (KERN_INFO "SuperIO: Floppy controller at 0x%x\n", sio->fdc_base);
  151. pci_read_config_dword (pdev, SIO_ACPIBAR, &sio->acpi_base);
  152. sio->acpi_base &= ~1;
  153. printk (KERN_INFO "SuperIO: ACPI at 0x%x\n", sio->acpi_base);
  154. request_region (IC_PIC1, 0x1f, "pic1");
  155. request_region (IC_PIC2, 0x1f, "pic2");
  156. request_region (sio->acpi_base, 0x1f, "acpi");
  157. /* Enable the legacy I/O function */
  158. pci_read_config_word (pdev, PCI_COMMAND, &word);
  159. word |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_IO;
  160. pci_write_config_word (pdev, PCI_COMMAND, word);
  161. pci_set_master (pdev);
  162. pci_enable_device(pdev);
  163. /*
  164. * Next project is programming the onboard interrupt controllers.
  165. * PDC hasn't done this for us, since it's using polled I/O.
  166. *
  167. * XXX Use dword writes to avoid bugs in Elroy or Suckyio Config
  168. * space access. PCI is by nature a 32-bit bus and config
  169. * space can be sensitive to that.
  170. */
  171. /* 0x64 - 0x67 :
  172. DMA Rtg 2
  173. DMA Rtg 3
  174. DMA Chan Ctl
  175. TRIGGER_1 == 0x82 USB & IDE level triggered, rest to edge
  176. */
  177. pci_write_config_dword (pdev, 0x64, 0x82000000U);
  178. /* 0x68 - 0x6b :
  179. TRIGGER_2 == 0x00 all edge triggered (not used)
  180. CFG_IR_SER == 0x43 SerPort1 = IRQ3, SerPort2 = IRQ4
  181. CFG_IR_PF == 0x65 ParPort = IRQ5, FloppyCtlr = IRQ6
  182. CFG_IR_IDE == 0x07 IDE1 = IRQ7, reserved
  183. */
  184. pci_write_config_dword (pdev, TRIGGER_2, 0x07654300U);
  185. /* 0x6c - 0x6f :
  186. CFG_IR_INTAB == 0x00
  187. CFG_IR_INTCD == 0x10 USB = IRQ1
  188. CFG_IR_PS2 == 0x00
  189. CFG_IR_FXBUS == 0x00
  190. */
  191. pci_write_config_dword (pdev, CFG_IR_INTAB, 0x00001000U);
  192. /* 0x70 - 0x73 :
  193. CFG_IR_USB == 0x00 not used. USB is connected to INTD.
  194. CFG_IR_ACPI == 0x00 not used.
  195. DMA Priority == 0x4c88 Power on default value. NFC.
  196. */
  197. pci_write_config_dword (pdev, CFG_IR_USB, 0x4c880000U);
  198. /* PIC1 Initialization Command Word register programming */
  199. outb (0x11,IC_PIC1+0); /* ICW1: ICW4 write req | ICW1 */
  200. outb (0x00,IC_PIC1+1); /* ICW2: interrupt vector table - not used */
  201. outb (0x04,IC_PIC1+1); /* ICW3: Cascade */
  202. outb (0x01,IC_PIC1+1); /* ICW4: x86 mode */
  203. /* PIC1 Program Operational Control Words */
  204. outb (0xff,IC_PIC1+1); /* OCW1: Mask all interrupts */
  205. outb (0xc2,IC_PIC1+0); /* OCW2: priority (3-7,0-2) */
  206. /* PIC2 Initialization Command Word register programming */
  207. outb (0x11,IC_PIC2+0); /* ICW1: ICW4 write req | ICW1 */
  208. outb (0x00,IC_PIC2+1); /* ICW2: N/A */
  209. outb (0x02,IC_PIC2+1); /* ICW3: Slave ID code */
  210. outb (0x01,IC_PIC2+1); /* ICW4: x86 mode */
  211. /* Program Operational Control Words */
  212. outb (0xff,IC_PIC1+1); /* OCW1: Mask all interrupts */
  213. outb (0x68,IC_PIC1+0); /* OCW3: OCW3 select | ESMM | SMM */
  214. /* Write master mask reg */
  215. outb (0xff,IC_PIC1+1);
  216. /* Setup USB power regulation */
  217. outb(1, sio->acpi_base + USB_REG_CR);
  218. if (inb(sio->acpi_base + USB_REG_CR) & 1)
  219. printk(KERN_INFO "SuperIO: USB regulator enabled\n");
  220. else
  221. printk(KERN_ERR "USB regulator not initialized!\n");
  222. if (request_irq(pdev->irq, superio_interrupt, SA_INTERRUPT,
  223. "SuperIO", (void *)sio)) {
  224. printk(KERN_ERR "SuperIO: could not get irq\n");
  225. BUG();
  226. return;
  227. }
  228. sio->suckyio_irq_enabled = 1;
  229. }
  230. static void superio_disable_irq(unsigned int irq)
  231. {
  232. u8 r8;
  233. if ((irq < 1) || (irq == 2) || (irq > 7)) {
  234. printk(KERN_ERR "SuperIO: Illegal irq number.\n");
  235. BUG();
  236. return;
  237. }
  238. /* Mask interrupt */
  239. r8 = inb(IC_PIC1+1);
  240. r8 |= (1 << irq);
  241. outb (r8,IC_PIC1+1);
  242. }
  243. static void superio_enable_irq(unsigned int irq)
  244. {
  245. u8 r8;
  246. if ((irq < 1) || (irq == 2) || (irq > 7)) {
  247. printk(KERN_ERR "SuperIO: Illegal irq number (%d).\n", irq);
  248. BUG();
  249. return;
  250. }
  251. /* Unmask interrupt */
  252. r8 = inb(IC_PIC1+1);
  253. r8 &= ~(1 << irq);
  254. outb (r8,IC_PIC1+1);
  255. }
  256. static unsigned int superio_startup_irq(unsigned int irq)
  257. {
  258. superio_enable_irq(irq);
  259. return 0;
  260. }
  261. static struct hw_interrupt_type superio_interrupt_type = {
  262. .typename = "SuperIO",
  263. .startup = superio_startup_irq,
  264. .shutdown = superio_disable_irq,
  265. .enable = superio_enable_irq,
  266. .disable = superio_disable_irq,
  267. .ack = no_ack_irq,
  268. .end = no_end_irq,
  269. };
  270. #ifdef DEBUG_SUPERIO_INIT
  271. static unsigned short expected_device[3] = {
  272. PCI_DEVICE_ID_NS_87415,
  273. PCI_DEVICE_ID_NS_87560_LIO,
  274. PCI_DEVICE_ID_NS_87560_USB
  275. };
  276. #endif
  277. int superio_fixup_irq(struct pci_dev *pcidev)
  278. {
  279. int local_irq, i;
  280. #ifdef DEBUG_SUPERIO_INIT
  281. int fn;
  282. fn = PCI_FUNC(pcidev->devfn);
  283. /* Verify the function number matches the expected device id. */
  284. if (expected_device[fn] != pcidev->device) {
  285. BUG();
  286. return -1;
  287. }
  288. printk("superio_fixup_irq(%s) ven 0x%x dev 0x%x from %p\n",
  289. pci_name(pcidev),
  290. pcidev->vendor, pcidev->device,
  291. __builtin_return_address(0));
  292. #endif
  293. for (i = 0; i < 16; i++) {
  294. irq_desc[i].handler = &superio_interrupt_type;
  295. }
  296. /*
  297. * We don't allocate a SuperIO irq for the legacy IO function,
  298. * since it is a "bridge". Instead, we will allocate irq's for
  299. * each legacy device as they are initialized.
  300. */
  301. switch(pcidev->device) {
  302. case PCI_DEVICE_ID_NS_87415: /* Function 0 */
  303. local_irq = IDE_IRQ;
  304. break;
  305. case PCI_DEVICE_ID_NS_87560_LIO: /* Function 1 */
  306. sio_dev.lio_pdev = pcidev; /* save for superio_init() */
  307. return -1;
  308. case PCI_DEVICE_ID_NS_87560_USB: /* Function 2 */
  309. sio_dev.usb_pdev = pcidev; /* save for superio_init() */
  310. local_irq = USB_IRQ;
  311. break;
  312. default:
  313. local_irq = -1;
  314. BUG();
  315. break;
  316. }
  317. return local_irq;
  318. }
  319. static struct uart_port serial[] = {
  320. {
  321. .iotype = UPIO_PORT,
  322. .line = 0,
  323. .type = PORT_16550A,
  324. .uartclk = 115200*16,
  325. .fifosize = 16,
  326. },
  327. {
  328. .iotype = UPIO_PORT,
  329. .line = 1,
  330. .type = PORT_16550A,
  331. .uartclk = 115200*16,
  332. .fifosize = 16,
  333. }
  334. };
  335. static void __devinit superio_serial_init(void)
  336. {
  337. #ifdef CONFIG_SERIAL_8250
  338. int retval;
  339. serial[0].iobase = sio_dev.sp1_base;
  340. serial[0].irq = SP1_IRQ;
  341. spin_lock_init(&serial[0].lock);
  342. retval = early_serial_setup(&serial[0]);
  343. if (retval < 0) {
  344. printk(KERN_WARNING "SuperIO: Register Serial #0 failed.\n");
  345. return;
  346. }
  347. serial[1].iobase = sio_dev.sp2_base;
  348. serial[1].irq = SP2_IRQ;
  349. spin_lock_init(&serial[1].lock);
  350. retval = early_serial_setup(&serial[1]);
  351. if (retval < 0)
  352. printk(KERN_WARNING "SuperIO: Register Serial #1 failed.\n");
  353. #endif /* CONFIG_SERIAL_8250 */
  354. }
  355. static void __devinit superio_parport_init(void)
  356. {
  357. #ifdef CONFIG_PARPORT_PC
  358. if (!parport_pc_probe_port(sio_dev.pp_base,
  359. 0 /*base_hi*/,
  360. PAR_IRQ,
  361. PARPORT_DMA_NONE /* dma */,
  362. NULL /*struct pci_dev* */) )
  363. printk(KERN_WARNING "SuperIO: Probing parallel port failed.\n");
  364. #endif /* CONFIG_PARPORT_PC */
  365. }
  366. static void superio_fixup_pci(struct pci_dev *pdev)
  367. {
  368. u8 prog;
  369. pdev->class |= 0x5;
  370. pci_write_config_byte(pdev, PCI_CLASS_PROG, pdev->class);
  371. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  372. printk("PCI: Enabled native mode for NS87415 (pif=0x%x)\n", prog);
  373. }
  374. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, superio_fixup_pci);
  375. static int __devinit superio_probe(struct pci_dev *dev, const struct pci_device_id *id)
  376. {
  377. /*
  378. ** superio_probe(00:0e.0) ven 0x100b dev 0x2 sv 0x0 sd 0x0 class 0x1018a
  379. ** superio_probe(00:0e.1) ven 0x100b dev 0xe sv 0x0 sd 0x0 class 0x68000
  380. ** superio_probe(00:0e.2) ven 0x100b dev 0x12 sv 0x0 sd 0x0 class 0xc0310
  381. */
  382. DBG_INIT("superio_probe(%s) ven 0x%x dev 0x%x sv 0x%x sd 0x%x class 0x%x\n",
  383. pci_name(dev),
  384. dev->vendor, dev->device,
  385. dev->subsystem_vendor, dev->subsystem_device,
  386. dev->class);
  387. superio_init(&sio_dev);
  388. if (dev->device == PCI_DEVICE_ID_NS_87560_LIO) { /* Function 1 */
  389. superio_parport_init();
  390. superio_serial_init();
  391. /* REVISIT XXX : superio_fdc_init() ? */
  392. return 0;
  393. } else if (dev->device == PCI_DEVICE_ID_NS_87415) { /* Function 0 */
  394. DBG_INIT("superio_probe: ignoring IDE 87415\n");
  395. } else if (dev->device == PCI_DEVICE_ID_NS_87560_USB) { /* Function 2 */
  396. DBG_INIT("superio_probe: ignoring USB OHCI controller\n");
  397. } else {
  398. DBG_INIT("superio_probe: WTF? Fire Extinguisher?\n");
  399. }
  400. /* Let appropriate other driver claim this device. */
  401. return -ENODEV;
  402. }
  403. static struct pci_device_id superio_tbl[] = {
  404. { PCI_VENDOR_ID_NS, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  405. { 0, }
  406. };
  407. static struct pci_driver superio_driver = {
  408. .name = "SuperIO",
  409. .id_table = superio_tbl,
  410. .probe = superio_probe,
  411. };
  412. static int __init superio_modinit(void)
  413. {
  414. return pci_register_driver(&superio_driver);
  415. }
  416. static void __exit superio_exit(void)
  417. {
  418. pci_unregister_driver(&superio_driver);
  419. }
  420. module_init(superio_modinit);
  421. module_exit(superio_exit);