pcibr_provider.c 6.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. #include <linux/interrupt.h>
  9. #include <linux/types.h>
  10. #include <linux/pci.h>
  11. #include <asm/sn/addrs.h>
  12. #include <asm/sn/geo.h>
  13. #include <asm/sn/pcibr_provider.h>
  14. #include <asm/sn/pcibus_provider_defs.h>
  15. #include <asm/sn/pcidev.h>
  16. #include <asm/sn/sn_sal.h>
  17. #include <asm/sn/sn2/sn_hwperf.h>
  18. #include "xtalk/xwidgetdev.h"
  19. #include "xtalk/hubdev.h"
  20. int
  21. sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
  22. {
  23. struct ia64_sal_retval ret_stuff;
  24. u64 busnum;
  25. u64 segment;
  26. ret_stuff.status = 0;
  27. ret_stuff.v0 = 0;
  28. segment = soft->pbi_buscommon.bs_persist_segment;
  29. busnum = soft->pbi_buscommon.bs_persist_busnum;
  30. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
  31. busnum, (u64) device, (u64) resp, 0, 0, 0);
  32. return (int)ret_stuff.v0;
  33. }
  34. int
  35. sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
  36. void *resp)
  37. {
  38. struct ia64_sal_retval ret_stuff;
  39. u64 busnum;
  40. u64 segment;
  41. ret_stuff.status = 0;
  42. ret_stuff.v0 = 0;
  43. segment = soft->pbi_buscommon.bs_persist_segment;
  44. busnum = soft->pbi_buscommon.bs_persist_busnum;
  45. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
  46. segment, busnum, (u64) device, (u64) action,
  47. (u64) resp, 0, 0);
  48. return (int)ret_stuff.v0;
  49. }
  50. static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
  51. {
  52. struct ia64_sal_retval ret_stuff;
  53. u64 busnum;
  54. int segment;
  55. ret_stuff.status = 0;
  56. ret_stuff.v0 = 0;
  57. segment = soft->pbi_buscommon.bs_persist_segment;
  58. busnum = soft->pbi_buscommon.bs_persist_busnum;
  59. SAL_CALL_NOLOCK(ret_stuff,
  60. (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
  61. (u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
  62. return (int)ret_stuff.v0;
  63. }
  64. u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
  65. {
  66. s64 rc;
  67. u16 ioboard;
  68. nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
  69. rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
  70. if (rc) {
  71. printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
  72. rc);
  73. return 0;
  74. }
  75. return ioboard;
  76. }
  77. /*
  78. * PCI Bridge Error interrupt handler. Gets invoked whenever a PCI
  79. * bridge sends an error interrupt.
  80. */
  81. static irqreturn_t
  82. pcibr_error_intr_handler(int irq, void *arg)
  83. {
  84. struct pcibus_info *soft = (struct pcibus_info *)arg;
  85. if (sal_pcibr_error_interrupt(soft) < 0) {
  86. panic("pcibr_error_intr_handler(): Fatal Bridge Error");
  87. }
  88. return IRQ_HANDLED;
  89. }
  90. void *
  91. pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
  92. {
  93. int nasid, cnode, j;
  94. struct hubdev_info *hubdev_info;
  95. struct pcibus_info *soft;
  96. struct sn_flush_device_kernel *sn_flush_device_kernel;
  97. struct sn_flush_device_common *common;
  98. if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
  99. return NULL;
  100. }
  101. /*
  102. * Allocate kernel bus soft and copy from prom.
  103. */
  104. soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
  105. if (!soft) {
  106. return NULL;
  107. }
  108. memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
  109. soft->pbi_buscommon.bs_base =
  110. (((u64) soft->pbi_buscommon.
  111. bs_base << 4) >> 4) | __IA64_UNCACHED_OFFSET;
  112. spin_lock_init(&soft->pbi_lock);
  113. /*
  114. * register the bridge's error interrupt handler
  115. */
  116. if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
  117. IRQF_SHARED, "PCIBR error", (void *)(soft))) {
  118. printk(KERN_WARNING
  119. "pcibr cannot allocate interrupt for error handler\n");
  120. }
  121. /*
  122. * Update the Bridge with the "kernel" pagesize
  123. */
  124. if (PAGE_SIZE < 16384) {
  125. pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
  126. } else {
  127. pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
  128. }
  129. nasid = NASID_GET(soft->pbi_buscommon.bs_base);
  130. cnode = nasid_to_cnodeid(nasid);
  131. hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
  132. if (hubdev_info->hdi_flush_nasid_list.widget_p) {
  133. sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
  134. widget_p[(int)soft->pbi_buscommon.bs_xid];
  135. if (sn_flush_device_kernel) {
  136. for (j = 0; j < DEV_PER_WIDGET;
  137. j++, sn_flush_device_kernel++) {
  138. common = sn_flush_device_kernel->common;
  139. if (common->sfdl_slot == -1)
  140. continue;
  141. if ((common->sfdl_persistent_segment ==
  142. soft->pbi_buscommon.bs_persist_segment) &&
  143. (common->sfdl_persistent_busnum ==
  144. soft->pbi_buscommon.bs_persist_busnum))
  145. common->sfdl_pcibus_info =
  146. soft;
  147. }
  148. }
  149. }
  150. /* Setup the PMU ATE map */
  151. soft->pbi_int_ate_resource.lowest_free_index = 0;
  152. soft->pbi_int_ate_resource.ate =
  153. kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
  154. if (!soft->pbi_int_ate_resource.ate) {
  155. kfree(soft);
  156. return NULL;
  157. }
  158. return soft;
  159. }
  160. void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
  161. {
  162. struct pcidev_info *pcidev_info;
  163. struct pcibus_info *pcibus_info;
  164. int bit = sn_irq_info->irq_int_bit;
  165. if (! sn_irq_info->irq_bridge)
  166. return;
  167. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  168. if (pcidev_info) {
  169. pcibus_info =
  170. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  171. pdi_pcibus_info;
  172. pcireg_force_intr_set(pcibus_info, bit);
  173. }
  174. }
  175. void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
  176. {
  177. struct pcidev_info *pcidev_info;
  178. struct pcibus_info *pcibus_info;
  179. int bit = sn_irq_info->irq_int_bit;
  180. u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
  181. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  182. if (pcidev_info) {
  183. pcibus_info =
  184. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  185. pdi_pcibus_info;
  186. /* Disable the device's IRQ */
  187. pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
  188. /* Change the device's IRQ */
  189. pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
  190. /* Re-enable the device's IRQ */
  191. pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
  192. pcibr_force_interrupt(sn_irq_info);
  193. }
  194. }
  195. /*
  196. * Provider entries for PIC/CP
  197. */
  198. struct sn_pcibus_provider pcibr_provider = {
  199. .dma_map = pcibr_dma_map,
  200. .dma_map_consistent = pcibr_dma_map_consistent,
  201. .dma_unmap = pcibr_dma_unmap,
  202. .bus_fixup = pcibr_bus_fixup,
  203. .force_interrupt = pcibr_force_interrupt,
  204. .target_interrupt = pcibr_target_interrupt
  205. };
  206. int
  207. pcibr_init_provider(void)
  208. {
  209. sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
  210. sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
  211. return 0;
  212. }
  213. EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
  214. EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
  215. EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);