iwl-core.c 82 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915
  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO2_##s##M_PLCP,\
  48. IWL_RATE_MIMO3_##s##M_PLCP,\
  49. IWL_RATE_##r##M_IEEE, \
  50. IWL_RATE_##ip##M_INDEX, \
  51. IWL_RATE_##in##M_INDEX, \
  52. IWL_RATE_##rp##M_INDEX, \
  53. IWL_RATE_##rn##M_INDEX, \
  54. IWL_RATE_##pp##M_INDEX, \
  55. IWL_RATE_##np##M_INDEX }
  56. static irqreturn_t iwl_isr(int irq, void *data);
  57. /*
  58. * Parameter order:
  59. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  60. *
  61. * If there isn't a valid next or previous rate then INV is used which
  62. * maps to IWL_RATE_INVALID
  63. *
  64. */
  65. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  66. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  67. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  68. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  69. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  70. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  71. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  72. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  73. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  74. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  75. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  76. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  77. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  78. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  79. /* FIXME:RS: ^^ should be INV (legacy) */
  80. };
  81. EXPORT_SYMBOL(iwl_rates);
  82. /**
  83. * translate ucode response to mac80211 tx status control values
  84. */
  85. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  86. struct ieee80211_tx_info *info)
  87. {
  88. int rate_index;
  89. struct ieee80211_tx_rate *r = &info->control.rates[0];
  90. info->antenna_sel_tx =
  91. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  92. if (rate_n_flags & RATE_MCS_HT_MSK)
  93. r->flags |= IEEE80211_TX_RC_MCS;
  94. if (rate_n_flags & RATE_MCS_GF_MSK)
  95. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  96. if (rate_n_flags & RATE_MCS_FAT_MSK)
  97. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  98. if (rate_n_flags & RATE_MCS_DUP_MSK)
  99. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  100. if (rate_n_flags & RATE_MCS_SGI_MSK)
  101. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  102. rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
  103. if (info->band == IEEE80211_BAND_5GHZ)
  104. rate_index -= IWL_FIRST_OFDM_RATE;
  105. r->idx = rate_index;
  106. }
  107. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  108. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  109. {
  110. int idx = 0;
  111. /* HT rate format */
  112. if (rate_n_flags & RATE_MCS_HT_MSK) {
  113. idx = (rate_n_flags & 0xff);
  114. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  115. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  116. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  117. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  118. idx += IWL_FIRST_OFDM_RATE;
  119. /* skip 9M not supported in ht*/
  120. if (idx >= IWL_RATE_9M_INDEX)
  121. idx += 1;
  122. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  123. return idx;
  124. /* legacy rate format, search for match in table */
  125. } else {
  126. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  127. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  128. return idx;
  129. }
  130. return -1;
  131. }
  132. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  133. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  134. {
  135. int i;
  136. u8 ind = ant;
  137. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  138. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  139. if (priv->hw_params.valid_tx_ant & BIT(ind))
  140. return ind;
  141. }
  142. return ant;
  143. }
  144. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  145. EXPORT_SYMBOL(iwl_bcast_addr);
  146. /* This function both allocates and initializes hw and priv. */
  147. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  148. struct ieee80211_ops *hw_ops)
  149. {
  150. struct iwl_priv *priv;
  151. /* mac80211 allocates memory for this device instance, including
  152. * space for this driver's private structure */
  153. struct ieee80211_hw *hw =
  154. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  155. if (hw == NULL) {
  156. printk(KERN_ERR "%s: Can not allocate network device\n",
  157. cfg->name);
  158. goto out;
  159. }
  160. priv = hw->priv;
  161. priv->hw = hw;
  162. out:
  163. return hw;
  164. }
  165. EXPORT_SYMBOL(iwl_alloc_all);
  166. void iwl_hw_detect(struct iwl_priv *priv)
  167. {
  168. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  169. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  170. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  171. }
  172. EXPORT_SYMBOL(iwl_hw_detect);
  173. int iwl_hw_nic_init(struct iwl_priv *priv)
  174. {
  175. unsigned long flags;
  176. struct iwl_rx_queue *rxq = &priv->rxq;
  177. int ret;
  178. /* nic_init */
  179. spin_lock_irqsave(&priv->lock, flags);
  180. priv->cfg->ops->lib->apm_ops.init(priv);
  181. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  182. spin_unlock_irqrestore(&priv->lock, flags);
  183. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  184. priv->cfg->ops->lib->apm_ops.config(priv);
  185. /* Allocate the RX queue, or reset if it is already allocated */
  186. if (!rxq->bd) {
  187. ret = iwl_rx_queue_alloc(priv);
  188. if (ret) {
  189. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  190. return -ENOMEM;
  191. }
  192. } else
  193. iwl_rx_queue_reset(priv, rxq);
  194. iwl_rx_replenish(priv);
  195. iwl_rx_init(priv, rxq);
  196. spin_lock_irqsave(&priv->lock, flags);
  197. rxq->need_update = 1;
  198. iwl_rx_queue_update_write_ptr(priv, rxq);
  199. spin_unlock_irqrestore(&priv->lock, flags);
  200. /* Allocate and init all Tx and Command queues */
  201. ret = iwl_txq_ctx_reset(priv);
  202. if (ret)
  203. return ret;
  204. set_bit(STATUS_INIT, &priv->status);
  205. return 0;
  206. }
  207. EXPORT_SYMBOL(iwl_hw_nic_init);
  208. /*
  209. * QoS support
  210. */
  211. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  212. {
  213. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  214. return;
  215. priv->qos_data.def_qos_parm.qos_flags = 0;
  216. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  217. !priv->qos_data.qos_cap.q_AP.txop_request)
  218. priv->qos_data.def_qos_parm.qos_flags |=
  219. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  220. if (priv->qos_data.qos_active)
  221. priv->qos_data.def_qos_parm.qos_flags |=
  222. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  223. if (priv->current_ht_config.is_ht)
  224. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  225. if (force || iwl_is_associated(priv)) {
  226. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  227. priv->qos_data.qos_active,
  228. priv->qos_data.def_qos_parm.qos_flags);
  229. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  230. sizeof(struct iwl_qosparam_cmd),
  231. &priv->qos_data.def_qos_parm, NULL);
  232. }
  233. }
  234. EXPORT_SYMBOL(iwl_activate_qos);
  235. /*
  236. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  237. * (802.11b) (802.11a/g)
  238. * AC_BK 15 1023 7 0 0
  239. * AC_BE 15 1023 3 0 0
  240. * AC_VI 7 15 2 6.016ms 3.008ms
  241. * AC_VO 3 7 2 3.264ms 1.504ms
  242. */
  243. void iwl_reset_qos(struct iwl_priv *priv)
  244. {
  245. u16 cw_min = 15;
  246. u16 cw_max = 1023;
  247. u8 aifs = 2;
  248. bool is_legacy = false;
  249. unsigned long flags;
  250. int i;
  251. spin_lock_irqsave(&priv->lock, flags);
  252. /* QoS always active in AP and ADHOC mode
  253. * In STA mode wait for association
  254. */
  255. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  256. priv->iw_mode == NL80211_IFTYPE_AP)
  257. priv->qos_data.qos_active = 1;
  258. else
  259. priv->qos_data.qos_active = 0;
  260. /* check for legacy mode */
  261. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  262. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  263. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  264. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  265. cw_min = 31;
  266. is_legacy = 1;
  267. }
  268. if (priv->qos_data.qos_active)
  269. aifs = 3;
  270. /* AC_BE */
  271. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  272. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  273. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  274. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  275. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  276. if (priv->qos_data.qos_active) {
  277. /* AC_BK */
  278. i = 1;
  279. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  280. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  281. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  282. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  283. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  284. /* AC_VI */
  285. i = 2;
  286. priv->qos_data.def_qos_parm.ac[i].cw_min =
  287. cpu_to_le16((cw_min + 1) / 2 - 1);
  288. priv->qos_data.def_qos_parm.ac[i].cw_max =
  289. cpu_to_le16(cw_min);
  290. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  291. if (is_legacy)
  292. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  293. cpu_to_le16(6016);
  294. else
  295. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  296. cpu_to_le16(3008);
  297. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  298. /* AC_VO */
  299. i = 3;
  300. priv->qos_data.def_qos_parm.ac[i].cw_min =
  301. cpu_to_le16((cw_min + 1) / 4 - 1);
  302. priv->qos_data.def_qos_parm.ac[i].cw_max =
  303. cpu_to_le16((cw_min + 1) / 2 - 1);
  304. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  305. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  306. if (is_legacy)
  307. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  308. cpu_to_le16(3264);
  309. else
  310. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  311. cpu_to_le16(1504);
  312. } else {
  313. for (i = 1; i < 4; i++) {
  314. priv->qos_data.def_qos_parm.ac[i].cw_min =
  315. cpu_to_le16(cw_min);
  316. priv->qos_data.def_qos_parm.ac[i].cw_max =
  317. cpu_to_le16(cw_max);
  318. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  319. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  320. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  321. }
  322. }
  323. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  324. spin_unlock_irqrestore(&priv->lock, flags);
  325. }
  326. EXPORT_SYMBOL(iwl_reset_qos);
  327. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  328. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  329. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  330. struct ieee80211_sta_ht_cap *ht_info,
  331. enum ieee80211_band band)
  332. {
  333. u16 max_bit_rate = 0;
  334. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  335. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  336. ht_info->cap = 0;
  337. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  338. ht_info->ht_supported = true;
  339. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  340. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  341. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  342. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  343. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  344. if (priv->hw_params.fat_channel & BIT(band)) {
  345. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  346. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  347. ht_info->mcs.rx_mask[4] = 0x01;
  348. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  349. }
  350. if (priv->cfg->mod_params->amsdu_size_8K)
  351. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  352. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  353. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  354. ht_info->mcs.rx_mask[0] = 0xFF;
  355. if (rx_chains_num >= 2)
  356. ht_info->mcs.rx_mask[1] = 0xFF;
  357. if (rx_chains_num >= 3)
  358. ht_info->mcs.rx_mask[2] = 0xFF;
  359. /* Highest supported Rx data rate */
  360. max_bit_rate *= rx_chains_num;
  361. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  362. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  363. /* Tx MCS capabilities */
  364. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  365. if (tx_chains_num != rx_chains_num) {
  366. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  367. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  368. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  369. }
  370. }
  371. static void iwlcore_init_hw_rates(struct iwl_priv *priv,
  372. struct ieee80211_rate *rates)
  373. {
  374. int i;
  375. for (i = 0; i < IWL_RATE_COUNT; i++) {
  376. rates[i].bitrate = iwl_rates[i].ieee * 5;
  377. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  378. rates[i].hw_value_short = i;
  379. rates[i].flags = 0;
  380. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  381. /*
  382. * If CCK != 1M then set short preamble rate flag.
  383. */
  384. rates[i].flags |=
  385. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  386. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  387. }
  388. }
  389. }
  390. /**
  391. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  392. */
  393. int iwlcore_init_geos(struct iwl_priv *priv)
  394. {
  395. struct iwl_channel_info *ch;
  396. struct ieee80211_supported_band *sband;
  397. struct ieee80211_channel *channels;
  398. struct ieee80211_channel *geo_ch;
  399. struct ieee80211_rate *rates;
  400. int i = 0;
  401. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  402. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  403. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  404. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  405. return 0;
  406. }
  407. channels = kzalloc(sizeof(struct ieee80211_channel) *
  408. priv->channel_count, GFP_KERNEL);
  409. if (!channels)
  410. return -ENOMEM;
  411. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  412. GFP_KERNEL);
  413. if (!rates) {
  414. kfree(channels);
  415. return -ENOMEM;
  416. }
  417. /* 5.2GHz channels start after the 2.4GHz channels */
  418. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  419. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  420. /* just OFDM */
  421. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  422. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  423. if (priv->cfg->sku & IWL_SKU_N)
  424. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  425. IEEE80211_BAND_5GHZ);
  426. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  427. sband->channels = channels;
  428. /* OFDM & CCK */
  429. sband->bitrates = rates;
  430. sband->n_bitrates = IWL_RATE_COUNT;
  431. if (priv->cfg->sku & IWL_SKU_N)
  432. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  433. IEEE80211_BAND_2GHZ);
  434. priv->ieee_channels = channels;
  435. priv->ieee_rates = rates;
  436. for (i = 0; i < priv->channel_count; i++) {
  437. ch = &priv->channel_info[i];
  438. /* FIXME: might be removed if scan is OK */
  439. if (!is_channel_valid(ch))
  440. continue;
  441. if (is_channel_a_band(ch))
  442. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  443. else
  444. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  445. geo_ch = &sband->channels[sband->n_channels++];
  446. geo_ch->center_freq =
  447. ieee80211_channel_to_frequency(ch->channel);
  448. geo_ch->max_power = ch->max_power_avg;
  449. geo_ch->max_antenna_gain = 0xff;
  450. geo_ch->hw_value = ch->channel;
  451. if (is_channel_valid(ch)) {
  452. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  453. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  454. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  455. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  456. if (ch->flags & EEPROM_CHANNEL_RADAR)
  457. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  458. geo_ch->flags |= ch->fat_extension_channel;
  459. if (ch->max_power_avg > priv->tx_power_channel_lmt)
  460. priv->tx_power_channel_lmt = ch->max_power_avg;
  461. } else {
  462. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  463. }
  464. /* Save flags for reg domain usage */
  465. geo_ch->orig_flags = geo_ch->flags;
  466. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  467. ch->channel, geo_ch->center_freq,
  468. is_channel_a_band(ch) ? "5.2" : "2.4",
  469. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  470. "restricted" : "valid",
  471. geo_ch->flags);
  472. }
  473. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  474. priv->cfg->sku & IWL_SKU_A) {
  475. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  476. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  477. priv->pci_dev->device,
  478. priv->pci_dev->subsystem_device);
  479. priv->cfg->sku &= ~IWL_SKU_A;
  480. }
  481. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  482. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  483. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  484. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  485. return 0;
  486. }
  487. EXPORT_SYMBOL(iwlcore_init_geos);
  488. /*
  489. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  490. */
  491. void iwlcore_free_geos(struct iwl_priv *priv)
  492. {
  493. kfree(priv->ieee_channels);
  494. kfree(priv->ieee_rates);
  495. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  496. }
  497. EXPORT_SYMBOL(iwlcore_free_geos);
  498. static bool is_single_rx_stream(struct iwl_priv *priv)
  499. {
  500. return !priv->current_ht_config.is_ht ||
  501. ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
  502. (priv->current_ht_config.mcs.rx_mask[2] == 0));
  503. }
  504. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  505. enum ieee80211_band band,
  506. u16 channel, u8 extension_chan_offset)
  507. {
  508. const struct iwl_channel_info *ch_info;
  509. ch_info = iwl_get_channel_info(priv, band, channel);
  510. if (!is_channel_valid(ch_info))
  511. return 0;
  512. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  513. return !(ch_info->fat_extension_channel &
  514. IEEE80211_CHAN_NO_HT40PLUS);
  515. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  516. return !(ch_info->fat_extension_channel &
  517. IEEE80211_CHAN_NO_HT40MINUS);
  518. return 0;
  519. }
  520. u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
  521. struct ieee80211_sta_ht_cap *sta_ht_inf)
  522. {
  523. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  524. if ((!iwl_ht_conf->is_ht) ||
  525. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
  526. return 0;
  527. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  528. * the bit will not set if it is pure 40MHz case
  529. */
  530. if (sta_ht_inf) {
  531. if (!sta_ht_inf->ht_supported)
  532. return 0;
  533. }
  534. if (iwl_ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ)
  535. return 1;
  536. else
  537. return iwl_is_channel_extension(priv, priv->band,
  538. le16_to_cpu(priv->staging_rxon.channel),
  539. iwl_ht_conf->extension_chan_offset);
  540. }
  541. EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
  542. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  543. {
  544. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  545. if (hw_decrypt)
  546. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  547. else
  548. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  549. }
  550. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  551. /**
  552. * iwl_check_rxon_cmd - validate RXON structure is valid
  553. *
  554. * NOTE: This is really only useful during development and can eventually
  555. * be #ifdef'd out once the driver is stable and folks aren't actively
  556. * making changes
  557. */
  558. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  559. {
  560. int error = 0;
  561. int counter = 1;
  562. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  563. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  564. error |= le32_to_cpu(rxon->flags &
  565. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  566. RXON_FLG_RADAR_DETECT_MSK));
  567. if (error)
  568. IWL_WARN(priv, "check 24G fields %d | %d\n",
  569. counter++, error);
  570. } else {
  571. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  572. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  573. if (error)
  574. IWL_WARN(priv, "check 52 fields %d | %d\n",
  575. counter++, error);
  576. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  577. if (error)
  578. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  579. counter++, error);
  580. }
  581. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  582. if (error)
  583. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  584. /* make sure basic rates 6Mbps and 1Mbps are supported */
  585. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  586. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  587. if (error)
  588. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  589. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  590. if (error)
  591. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  592. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  593. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  594. if (error)
  595. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  596. counter++, error);
  597. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  598. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  599. if (error)
  600. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  601. counter++, error);
  602. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  603. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  604. if (error)
  605. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  606. counter++, error);
  607. if (error)
  608. IWL_WARN(priv, "Tuning to channel %d\n",
  609. le16_to_cpu(rxon->channel));
  610. if (error) {
  611. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  612. return -1;
  613. }
  614. return 0;
  615. }
  616. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  617. /**
  618. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  619. * @priv: staging_rxon is compared to active_rxon
  620. *
  621. * If the RXON structure is changing enough to require a new tune,
  622. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  623. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  624. */
  625. int iwl_full_rxon_required(struct iwl_priv *priv)
  626. {
  627. /* These items are only settable from the full RXON command */
  628. if (!(iwl_is_associated(priv)) ||
  629. compare_ether_addr(priv->staging_rxon.bssid_addr,
  630. priv->active_rxon.bssid_addr) ||
  631. compare_ether_addr(priv->staging_rxon.node_addr,
  632. priv->active_rxon.node_addr) ||
  633. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  634. priv->active_rxon.wlap_bssid_addr) ||
  635. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  636. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  637. (priv->staging_rxon.air_propagation !=
  638. priv->active_rxon.air_propagation) ||
  639. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  640. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  641. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  642. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  643. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  644. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  645. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  646. return 1;
  647. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  648. * be updated with the RXON_ASSOC command -- however only some
  649. * flag transitions are allowed using RXON_ASSOC */
  650. /* Check if we are not switching bands */
  651. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  652. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  653. return 1;
  654. /* Check if we are switching association toggle */
  655. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  656. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  657. return 1;
  658. return 0;
  659. }
  660. EXPORT_SYMBOL(iwl_full_rxon_required);
  661. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  662. {
  663. int i;
  664. int rate_mask;
  665. /* Set rate mask*/
  666. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  667. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  668. else
  669. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  670. /* Find lowest valid rate */
  671. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  672. i = iwl_rates[i].next_ieee) {
  673. if (rate_mask & (1 << i))
  674. return iwl_rates[i].plcp;
  675. }
  676. /* No valid rate was found. Assign the lowest one */
  677. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  678. return IWL_RATE_1M_PLCP;
  679. else
  680. return IWL_RATE_6M_PLCP;
  681. }
  682. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  683. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
  684. {
  685. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  686. if (!ht_info->is_ht) {
  687. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  688. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  689. RXON_FLG_FAT_PROT_MSK |
  690. RXON_FLG_HT_PROT_MSK);
  691. return;
  692. }
  693. /* FIXME: if the definition of ht_protection changed, the "translation"
  694. * will be needed for rxon->flags
  695. */
  696. rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  697. /* Set up channel bandwidth:
  698. * 20 MHz only, 20/40 mixed or pure 40 if fat ok */
  699. /* clear the HT channel mode before set the mode */
  700. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  701. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  702. if (iwl_is_fat_tx_allowed(priv, NULL)) {
  703. /* pure 40 fat */
  704. if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ)
  705. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  706. else {
  707. /* Note: control channel is opposite of extension channel */
  708. switch (ht_info->extension_chan_offset) {
  709. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  710. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  711. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  712. break;
  713. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  714. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  715. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  716. break;
  717. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  718. default:
  719. /* channel location only valid if in Mixed mode */
  720. IWL_ERR(priv, "invalid extension channel offset\n");
  721. break;
  722. }
  723. }
  724. } else {
  725. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  726. }
  727. if (priv->cfg->ops->hcmd->set_rxon_chain)
  728. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  729. IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
  730. "rxon flags 0x%X operation mode :0x%X "
  731. "extension channel offset 0x%x\n",
  732. ht_info->mcs.rx_mask[0],
  733. ht_info->mcs.rx_mask[1],
  734. ht_info->mcs.rx_mask[2],
  735. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  736. ht_info->extension_chan_offset);
  737. return;
  738. }
  739. EXPORT_SYMBOL(iwl_set_rxon_ht);
  740. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  741. #define IWL_NUM_RX_CHAINS_SINGLE 2
  742. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  743. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  744. /* Determine how many receiver/antenna chains to use.
  745. * More provides better reception via diversity. Fewer saves power.
  746. * MIMO (dual stream) requires at least 2, but works better with 3.
  747. * This does not determine *which* chains to use, just how many.
  748. */
  749. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  750. {
  751. bool is_single = is_single_rx_stream(priv);
  752. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  753. /* # of Rx chains to use when expecting MIMO. */
  754. if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
  755. WLAN_HT_CAP_SM_PS_STATIC)))
  756. return IWL_NUM_RX_CHAINS_SINGLE;
  757. else
  758. return IWL_NUM_RX_CHAINS_MULTIPLE;
  759. }
  760. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  761. {
  762. int idle_cnt;
  763. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  764. /* # Rx chains when idling and maybe trying to save power */
  765. switch (priv->current_ht_config.sm_ps) {
  766. case WLAN_HT_CAP_SM_PS_STATIC:
  767. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  768. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  769. IWL_NUM_IDLE_CHAINS_SINGLE;
  770. break;
  771. case WLAN_HT_CAP_SM_PS_DISABLED:
  772. idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
  773. break;
  774. case WLAN_HT_CAP_SM_PS_INVALID:
  775. default:
  776. IWL_ERR(priv, "invalid mimo ps mode %d\n",
  777. priv->current_ht_config.sm_ps);
  778. WARN_ON(1);
  779. idle_cnt = -1;
  780. break;
  781. }
  782. return idle_cnt;
  783. }
  784. /* up to 4 chains */
  785. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  786. {
  787. u8 res;
  788. res = (chain_bitmap & BIT(0)) >> 0;
  789. res += (chain_bitmap & BIT(1)) >> 1;
  790. res += (chain_bitmap & BIT(2)) >> 2;
  791. res += (chain_bitmap & BIT(4)) >> 4;
  792. return res;
  793. }
  794. /**
  795. * iwl_is_monitor_mode - Determine if interface in monitor mode
  796. *
  797. * priv->iw_mode is set in add_interface, but add_interface is
  798. * never called for monitor mode. The only way mac80211 informs us about
  799. * monitor mode is through configuring filters (call to configure_filter).
  800. */
  801. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  802. {
  803. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  804. }
  805. EXPORT_SYMBOL(iwl_is_monitor_mode);
  806. /**
  807. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  808. *
  809. * Selects how many and which Rx receivers/antennas/chains to use.
  810. * This should not be used for scan command ... it puts data in wrong place.
  811. */
  812. void iwl_set_rxon_chain(struct iwl_priv *priv)
  813. {
  814. bool is_single = is_single_rx_stream(priv);
  815. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  816. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  817. u32 active_chains;
  818. u16 rx_chain;
  819. /* Tell uCode which antennas are actually connected.
  820. * Before first association, we assume all antennas are connected.
  821. * Just after first association, iwl_chain_noise_calibration()
  822. * checks which antennas actually *are* connected. */
  823. if (priv->chain_noise_data.active_chains)
  824. active_chains = priv->chain_noise_data.active_chains;
  825. else
  826. active_chains = priv->hw_params.valid_rx_ant;
  827. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  828. /* How many receivers should we use? */
  829. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  830. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  831. /* correct rx chain count according hw settings
  832. * and chain noise calibration
  833. */
  834. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  835. if (valid_rx_cnt < active_rx_cnt)
  836. active_rx_cnt = valid_rx_cnt;
  837. if (valid_rx_cnt < idle_rx_cnt)
  838. idle_rx_cnt = valid_rx_cnt;
  839. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  840. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  841. /* copied from 'iwl_bg_request_scan()' */
  842. /* Force use of chains B and C (0x6) for Rx for 4965
  843. * Avoid A (0x1) because of its off-channel reception on A-band.
  844. * MIMO is not used here, but value is required */
  845. if (iwl_is_monitor_mode(priv) &&
  846. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  847. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  848. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  849. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  850. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  851. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  852. }
  853. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  854. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  855. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  856. else
  857. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  858. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  859. priv->staging_rxon.rx_chain,
  860. active_rx_cnt, idle_rx_cnt);
  861. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  862. active_rx_cnt < idle_rx_cnt);
  863. }
  864. EXPORT_SYMBOL(iwl_set_rxon_chain);
  865. /**
  866. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  867. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  868. * @channel: Any channel valid for the requested phymode
  869. * In addition to setting the staging RXON, priv->phymode is also set.
  870. *
  871. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  872. * in the staging RXON flag structure based on the phymode
  873. */
  874. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  875. {
  876. enum ieee80211_band band = ch->band;
  877. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  878. if (!iwl_get_channel_info(priv, band, channel)) {
  879. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  880. channel, band);
  881. return -EINVAL;
  882. }
  883. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  884. (priv->band == band))
  885. return 0;
  886. priv->staging_rxon.channel = cpu_to_le16(channel);
  887. if (band == IEEE80211_BAND_5GHZ)
  888. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  889. else
  890. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  891. priv->band = band;
  892. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  893. return 0;
  894. }
  895. EXPORT_SYMBOL(iwl_set_rxon_channel);
  896. void iwl_set_flags_for_band(struct iwl_priv *priv,
  897. enum ieee80211_band band)
  898. {
  899. if (band == IEEE80211_BAND_5GHZ) {
  900. priv->staging_rxon.flags &=
  901. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  902. | RXON_FLG_CCK_MSK);
  903. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  904. } else {
  905. /* Copied from iwl_post_associate() */
  906. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  907. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  908. else
  909. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  910. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  911. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  912. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  913. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  914. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  915. }
  916. }
  917. EXPORT_SYMBOL(iwl_set_flags_for_band);
  918. /*
  919. * initialize rxon structure with default values from eeprom
  920. */
  921. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  922. {
  923. const struct iwl_channel_info *ch_info;
  924. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  925. switch (mode) {
  926. case NL80211_IFTYPE_AP:
  927. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  928. break;
  929. case NL80211_IFTYPE_STATION:
  930. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  931. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  932. break;
  933. case NL80211_IFTYPE_ADHOC:
  934. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  935. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  936. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  937. RXON_FILTER_ACCEPT_GRP_MSK;
  938. break;
  939. default:
  940. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  941. break;
  942. }
  943. #if 0
  944. /* TODO: Figure out when short_preamble would be set and cache from
  945. * that */
  946. if (!hw_to_local(priv->hw)->short_preamble)
  947. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  948. else
  949. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  950. #endif
  951. ch_info = iwl_get_channel_info(priv, priv->band,
  952. le16_to_cpu(priv->active_rxon.channel));
  953. if (!ch_info)
  954. ch_info = &priv->channel_info[0];
  955. /*
  956. * in some case A channels are all non IBSS
  957. * in this case force B/G channel
  958. */
  959. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  960. !(is_channel_ibss(ch_info)))
  961. ch_info = &priv->channel_info[0];
  962. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  963. priv->band = ch_info->band;
  964. iwl_set_flags_for_band(priv, priv->band);
  965. priv->staging_rxon.ofdm_basic_rates =
  966. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  967. priv->staging_rxon.cck_basic_rates =
  968. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  969. /* clear both MIX and PURE40 mode flag */
  970. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  971. RXON_FLG_CHANNEL_MODE_PURE_40);
  972. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  973. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  974. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  975. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  976. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  977. }
  978. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  979. static void iwl_set_rate(struct iwl_priv *priv)
  980. {
  981. const struct ieee80211_supported_band *hw = NULL;
  982. struct ieee80211_rate *rate;
  983. int i;
  984. hw = iwl_get_hw_mode(priv, priv->band);
  985. if (!hw) {
  986. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  987. return;
  988. }
  989. priv->active_rate = 0;
  990. priv->active_rate_basic = 0;
  991. for (i = 0; i < hw->n_bitrates; i++) {
  992. rate = &(hw->bitrates[i]);
  993. if (rate->hw_value < IWL_RATE_COUNT)
  994. priv->active_rate |= (1 << rate->hw_value);
  995. }
  996. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  997. priv->active_rate, priv->active_rate_basic);
  998. /*
  999. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1000. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1001. * OFDM
  1002. */
  1003. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1004. priv->staging_rxon.cck_basic_rates =
  1005. ((priv->active_rate_basic &
  1006. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1007. else
  1008. priv->staging_rxon.cck_basic_rates =
  1009. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1010. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1011. priv->staging_rxon.ofdm_basic_rates =
  1012. ((priv->active_rate_basic &
  1013. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1014. IWL_FIRST_OFDM_RATE) & 0xFF;
  1015. else
  1016. priv->staging_rxon.ofdm_basic_rates =
  1017. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1018. }
  1019. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1020. {
  1021. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1022. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1023. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1024. IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
  1025. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  1026. rxon->channel = csa->channel;
  1027. priv->staging_rxon.channel = csa->channel;
  1028. }
  1029. EXPORT_SYMBOL(iwl_rx_csa);
  1030. #ifdef CONFIG_IWLWIFI_DEBUG
  1031. static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1032. {
  1033. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1034. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1035. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1036. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1037. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1038. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1039. le32_to_cpu(rxon->filter_flags));
  1040. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1041. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1042. rxon->ofdm_basic_rates);
  1043. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1044. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1045. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1046. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1047. }
  1048. #endif
  1049. /**
  1050. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1051. */
  1052. void iwl_irq_handle_error(struct iwl_priv *priv)
  1053. {
  1054. /* Set the FW error flag -- cleared on iwl_down */
  1055. set_bit(STATUS_FW_ERROR, &priv->status);
  1056. /* Cancel currently queued command. */
  1057. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1058. #ifdef CONFIG_IWLWIFI_DEBUG
  1059. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  1060. iwl_dump_nic_error_log(priv);
  1061. iwl_dump_nic_event_log(priv);
  1062. iwl_print_rx_config_cmd(priv);
  1063. }
  1064. #endif
  1065. wake_up_interruptible(&priv->wait_command_queue);
  1066. /* Keep the restart process from trying to send host
  1067. * commands by clearing the INIT status bit */
  1068. clear_bit(STATUS_READY, &priv->status);
  1069. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1070. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1071. "Restarting adapter due to uCode error.\n");
  1072. if (priv->cfg->mod_params->restart_fw)
  1073. queue_work(priv->workqueue, &priv->restart);
  1074. }
  1075. }
  1076. EXPORT_SYMBOL(iwl_irq_handle_error);
  1077. void iwl_configure_filter(struct ieee80211_hw *hw,
  1078. unsigned int changed_flags,
  1079. unsigned int *total_flags,
  1080. int mc_count, struct dev_addr_list *mc_list)
  1081. {
  1082. struct iwl_priv *priv = hw->priv;
  1083. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1084. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1085. changed_flags, *total_flags);
  1086. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1087. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1088. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1089. else
  1090. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1091. }
  1092. if (changed_flags & FIF_ALLMULTI) {
  1093. if (*total_flags & FIF_ALLMULTI)
  1094. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1095. else
  1096. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1097. }
  1098. if (changed_flags & FIF_CONTROL) {
  1099. if (*total_flags & FIF_CONTROL)
  1100. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1101. else
  1102. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1103. }
  1104. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1105. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1106. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1107. else
  1108. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1109. }
  1110. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1111. * since mac80211 will call ieee80211_hw_config immediately.
  1112. * (mc_list is not supported at this time). Otherwise, we need to
  1113. * queue a background iwl_commit_rxon work.
  1114. */
  1115. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1116. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1117. }
  1118. EXPORT_SYMBOL(iwl_configure_filter);
  1119. int iwl_setup_mac(struct iwl_priv *priv)
  1120. {
  1121. int ret;
  1122. struct ieee80211_hw *hw = priv->hw;
  1123. hw->rate_control_algorithm = "iwl-agn-rs";
  1124. /* Tell mac80211 our characteristics */
  1125. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1126. IEEE80211_HW_NOISE_DBM |
  1127. IEEE80211_HW_AMPDU_AGGREGATION |
  1128. IEEE80211_HW_SPECTRUM_MGMT;
  1129. hw->wiphy->interface_modes =
  1130. BIT(NL80211_IFTYPE_STATION) |
  1131. BIT(NL80211_IFTYPE_ADHOC);
  1132. hw->wiphy->custom_regulatory = true;
  1133. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1134. /* we create the 802.11 header and a zero-length SSID element */
  1135. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1136. /* Default value; 4 EDCA QOS priorities */
  1137. hw->queues = 4;
  1138. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1139. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1140. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1141. &priv->bands[IEEE80211_BAND_2GHZ];
  1142. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1143. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1144. &priv->bands[IEEE80211_BAND_5GHZ];
  1145. ret = ieee80211_register_hw(priv->hw);
  1146. if (ret) {
  1147. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1148. return ret;
  1149. }
  1150. priv->mac80211_registered = 1;
  1151. return 0;
  1152. }
  1153. EXPORT_SYMBOL(iwl_setup_mac);
  1154. int iwl_set_hw_params(struct iwl_priv *priv)
  1155. {
  1156. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  1157. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1158. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1159. if (priv->cfg->mod_params->amsdu_size_8K)
  1160. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1161. else
  1162. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1163. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  1164. if (priv->cfg->mod_params->disable_11n)
  1165. priv->cfg->sku &= ~IWL_SKU_N;
  1166. /* Device-specific setup */
  1167. return priv->cfg->ops->lib->set_hw_params(priv);
  1168. }
  1169. EXPORT_SYMBOL(iwl_set_hw_params);
  1170. int iwl_init_drv(struct iwl_priv *priv)
  1171. {
  1172. int ret;
  1173. priv->ibss_beacon = NULL;
  1174. spin_lock_init(&priv->lock);
  1175. spin_lock_init(&priv->sta_lock);
  1176. spin_lock_init(&priv->hcmd_lock);
  1177. INIT_LIST_HEAD(&priv->free_frames);
  1178. mutex_init(&priv->mutex);
  1179. /* Clear the driver's (not device's) station table */
  1180. iwl_clear_stations_table(priv);
  1181. priv->data_retry_limit = -1;
  1182. priv->ieee_channels = NULL;
  1183. priv->ieee_rates = NULL;
  1184. priv->band = IEEE80211_BAND_2GHZ;
  1185. priv->iw_mode = NL80211_IFTYPE_STATION;
  1186. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
  1187. /* Choose which receivers/antennas to use */
  1188. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1189. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1190. iwl_init_scan_params(priv);
  1191. iwl_reset_qos(priv);
  1192. priv->qos_data.qos_active = 0;
  1193. priv->qos_data.qos_cap.val = 0;
  1194. priv->rates_mask = IWL_RATES_MASK;
  1195. /* If power management is turned on, default to CAM mode */
  1196. priv->power_mode = IWL_POWER_MODE_CAM;
  1197. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
  1198. ret = iwl_init_channel_map(priv);
  1199. if (ret) {
  1200. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  1201. goto err;
  1202. }
  1203. ret = iwlcore_init_geos(priv);
  1204. if (ret) {
  1205. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  1206. goto err_free_channel_map;
  1207. }
  1208. iwlcore_init_hw_rates(priv, priv->ieee_rates);
  1209. return 0;
  1210. err_free_channel_map:
  1211. iwl_free_channel_map(priv);
  1212. err:
  1213. return ret;
  1214. }
  1215. EXPORT_SYMBOL(iwl_init_drv);
  1216. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1217. {
  1218. int ret = 0;
  1219. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1220. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1221. tx_power,
  1222. IWL_TX_POWER_TARGET_POWER_MIN);
  1223. return -EINVAL;
  1224. }
  1225. if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
  1226. IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
  1227. tx_power,
  1228. IWL_TX_POWER_TARGET_POWER_MAX);
  1229. return -EINVAL;
  1230. }
  1231. if (priv->tx_power_user_lmt != tx_power)
  1232. force = true;
  1233. priv->tx_power_user_lmt = tx_power;
  1234. /* if nic is not up don't send command */
  1235. if (!iwl_is_ready_rf(priv))
  1236. return ret;
  1237. if (force && priv->cfg->ops->lib->send_tx_power)
  1238. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1239. return ret;
  1240. }
  1241. EXPORT_SYMBOL(iwl_set_tx_power);
  1242. void iwl_uninit_drv(struct iwl_priv *priv)
  1243. {
  1244. iwl_calib_free_results(priv);
  1245. iwlcore_free_geos(priv);
  1246. iwl_free_channel_map(priv);
  1247. kfree(priv->scan);
  1248. }
  1249. EXPORT_SYMBOL(iwl_uninit_drv);
  1250. void iwl_disable_interrupts(struct iwl_priv *priv)
  1251. {
  1252. clear_bit(STATUS_INT_ENABLED, &priv->status);
  1253. /* disable interrupts from uCode/NIC to host */
  1254. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1255. /* acknowledge/clear/reset any interrupts still pending
  1256. * from uCode or flow handler (Rx/Tx DMA) */
  1257. iwl_write32(priv, CSR_INT, 0xffffffff);
  1258. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  1259. IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
  1260. }
  1261. EXPORT_SYMBOL(iwl_disable_interrupts);
  1262. void iwl_enable_interrupts(struct iwl_priv *priv)
  1263. {
  1264. IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
  1265. set_bit(STATUS_INT_ENABLED, &priv->status);
  1266. iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
  1267. }
  1268. EXPORT_SYMBOL(iwl_enable_interrupts);
  1269. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1270. /* Free dram table */
  1271. void iwl_free_isr_ict(struct iwl_priv *priv)
  1272. {
  1273. if (priv->ict_tbl_vir) {
  1274. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1275. PAGE_SIZE, priv->ict_tbl_vir,
  1276. priv->ict_tbl_dma);
  1277. priv->ict_tbl_vir = NULL;
  1278. }
  1279. }
  1280. EXPORT_SYMBOL(iwl_free_isr_ict);
  1281. /* allocate dram shared table it is a PAGE_SIZE aligned
  1282. * also reset all data related to ICT table interrupt.
  1283. */
  1284. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1285. {
  1286. if (priv->cfg->use_isr_legacy)
  1287. return 0;
  1288. /* allocate shrared data table */
  1289. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1290. ICT_COUNT) + PAGE_SIZE,
  1291. &priv->ict_tbl_dma);
  1292. if (!priv->ict_tbl_vir)
  1293. return -ENOMEM;
  1294. /* align table to PAGE_SIZE boundry */
  1295. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1296. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1297. (unsigned long long)priv->ict_tbl_dma,
  1298. (unsigned long long)priv->aligned_ict_tbl_dma,
  1299. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1300. priv->ict_tbl = priv->ict_tbl_vir +
  1301. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1302. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1303. priv->ict_tbl, priv->ict_tbl_vir,
  1304. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1305. /* reset table and index to all 0 */
  1306. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1307. priv->ict_index = 0;
  1308. /* add periodic RX interrupt */
  1309. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1310. return 0;
  1311. }
  1312. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1313. /* Device is going up inform it about using ICT interrupt table,
  1314. * also we need to tell the driver to start using ICT interrupt.
  1315. */
  1316. int iwl_reset_ict(struct iwl_priv *priv)
  1317. {
  1318. u32 val;
  1319. unsigned long flags;
  1320. if (!priv->ict_tbl_vir)
  1321. return 0;
  1322. spin_lock_irqsave(&priv->lock, flags);
  1323. iwl_disable_interrupts(priv);
  1324. memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
  1325. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1326. val |= CSR_DRAM_INT_TBL_ENABLE;
  1327. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1328. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1329. "aligned dma address %Lx\n",
  1330. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1331. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1332. priv->use_ict = true;
  1333. priv->ict_index = 0;
  1334. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1335. iwl_enable_interrupts(priv);
  1336. spin_unlock_irqrestore(&priv->lock, flags);
  1337. return 0;
  1338. }
  1339. EXPORT_SYMBOL(iwl_reset_ict);
  1340. /* Device is going down disable ict interrupt usage */
  1341. void iwl_disable_ict(struct iwl_priv *priv)
  1342. {
  1343. unsigned long flags;
  1344. spin_lock_irqsave(&priv->lock, flags);
  1345. priv->use_ict = false;
  1346. spin_unlock_irqrestore(&priv->lock, flags);
  1347. }
  1348. EXPORT_SYMBOL(iwl_disable_ict);
  1349. /* interrupt handler using ict table, with this interrupt driver will
  1350. * stop using INTA register to get device's interrupt, reading this register
  1351. * is expensive, device will write interrupts in ICT dram table, increment
  1352. * index then will fire interrupt to driver, driver will OR all ICT table
  1353. * entries from current index up to table entry with 0 value. the result is
  1354. * the interrupt we need to service, driver will set the entries back to 0 and
  1355. * set index.
  1356. */
  1357. irqreturn_t iwl_isr_ict(int irq, void *data)
  1358. {
  1359. struct iwl_priv *priv = data;
  1360. u32 inta, inta_mask;
  1361. u32 val = 0;
  1362. if (!priv)
  1363. return IRQ_NONE;
  1364. /* dram interrupt table not set yet,
  1365. * use legacy interrupt.
  1366. */
  1367. if (!priv->use_ict)
  1368. return iwl_isr(irq, data);
  1369. spin_lock(&priv->lock);
  1370. /* Disable (but don't clear!) interrupts here to avoid
  1371. * back-to-back ISRs and sporadic interrupts from our NIC.
  1372. * If we have something to service, the tasklet will re-enable ints.
  1373. * If we *don't* have something, we'll re-enable before leaving here.
  1374. */
  1375. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1376. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1377. /* Ignore interrupt if there's nothing in NIC to service.
  1378. * This may be due to IRQ shared with another device,
  1379. * or due to sporadic interrupts thrown from our NIC. */
  1380. if (!priv->ict_tbl[priv->ict_index]) {
  1381. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1382. goto none;
  1383. }
  1384. /* read all entries that not 0 start with ict_index */
  1385. while (priv->ict_tbl[priv->ict_index]) {
  1386. val |= priv->ict_tbl[priv->ict_index];
  1387. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1388. priv->ict_index,
  1389. priv->ict_tbl[priv->ict_index]);
  1390. priv->ict_tbl[priv->ict_index] = 0;
  1391. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1392. ICT_COUNT);
  1393. }
  1394. /* We should not get this value, just ignore it. */
  1395. if (val == 0xffffffff)
  1396. val = 0;
  1397. inta = (0xff & val) | ((0xff00 & val) << 16);
  1398. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1399. inta, inta_mask, val);
  1400. inta &= priv->inta_mask;
  1401. priv->inta |= inta;
  1402. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1403. if (likely(inta))
  1404. tasklet_schedule(&priv->irq_tasklet);
  1405. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1406. /* Allow interrupt if was disabled by this handler and
  1407. * no tasklet was schedules, We should not enable interrupt,
  1408. * tasklet will enable it.
  1409. */
  1410. iwl_enable_interrupts(priv);
  1411. }
  1412. spin_unlock(&priv->lock);
  1413. return IRQ_HANDLED;
  1414. none:
  1415. /* re-enable interrupts here since we don't have anything to service.
  1416. * only Re-enable if disabled by irq.
  1417. */
  1418. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1419. iwl_enable_interrupts(priv);
  1420. spin_unlock(&priv->lock);
  1421. return IRQ_NONE;
  1422. }
  1423. EXPORT_SYMBOL(iwl_isr_ict);
  1424. static irqreturn_t iwl_isr(int irq, void *data)
  1425. {
  1426. struct iwl_priv *priv = data;
  1427. u32 inta, inta_mask;
  1428. #ifdef CONFIG_IWLWIFI_DEBUG
  1429. u32 inta_fh;
  1430. #endif
  1431. if (!priv)
  1432. return IRQ_NONE;
  1433. spin_lock(&priv->lock);
  1434. /* Disable (but don't clear!) interrupts here to avoid
  1435. * back-to-back ISRs and sporadic interrupts from our NIC.
  1436. * If we have something to service, the tasklet will re-enable ints.
  1437. * If we *don't* have something, we'll re-enable before leaving here. */
  1438. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1439. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1440. /* Discover which interrupts are active/pending */
  1441. inta = iwl_read32(priv, CSR_INT);
  1442. /* Ignore interrupt if there's nothing in NIC to service.
  1443. * This may be due to IRQ shared with another device,
  1444. * or due to sporadic interrupts thrown from our NIC. */
  1445. if (!inta) {
  1446. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1447. goto none;
  1448. }
  1449. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1450. /* Hardware disappeared. It might have already raised
  1451. * an interrupt */
  1452. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1453. goto unplugged;
  1454. }
  1455. #ifdef CONFIG_IWLWIFI_DEBUG
  1456. if (priv->debug_level & (IWL_DL_ISR)) {
  1457. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1458. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1459. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1460. }
  1461. #endif
  1462. priv->inta |= inta;
  1463. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1464. if (likely(inta))
  1465. tasklet_schedule(&priv->irq_tasklet);
  1466. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1467. iwl_enable_interrupts(priv);
  1468. unplugged:
  1469. spin_unlock(&priv->lock);
  1470. return IRQ_HANDLED;
  1471. none:
  1472. /* re-enable interrupts here since we don't have anything to service. */
  1473. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1474. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1475. iwl_enable_interrupts(priv);
  1476. spin_unlock(&priv->lock);
  1477. return IRQ_NONE;
  1478. }
  1479. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1480. {
  1481. struct iwl_priv *priv = data;
  1482. u32 inta, inta_mask;
  1483. u32 inta_fh;
  1484. if (!priv)
  1485. return IRQ_NONE;
  1486. spin_lock(&priv->lock);
  1487. /* Disable (but don't clear!) interrupts here to avoid
  1488. * back-to-back ISRs and sporadic interrupts from our NIC.
  1489. * If we have something to service, the tasklet will re-enable ints.
  1490. * If we *don't* have something, we'll re-enable before leaving here. */
  1491. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1492. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1493. /* Discover which interrupts are active/pending */
  1494. inta = iwl_read32(priv, CSR_INT);
  1495. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1496. /* Ignore interrupt if there's nothing in NIC to service.
  1497. * This may be due to IRQ shared with another device,
  1498. * or due to sporadic interrupts thrown from our NIC. */
  1499. if (!inta && !inta_fh) {
  1500. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1501. goto none;
  1502. }
  1503. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1504. /* Hardware disappeared. It might have already raised
  1505. * an interrupt */
  1506. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1507. goto unplugged;
  1508. }
  1509. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1510. inta, inta_mask, inta_fh);
  1511. inta &= ~CSR_INT_BIT_SCD;
  1512. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1513. if (likely(inta || inta_fh))
  1514. tasklet_schedule(&priv->irq_tasklet);
  1515. unplugged:
  1516. spin_unlock(&priv->lock);
  1517. return IRQ_HANDLED;
  1518. none:
  1519. /* re-enable interrupts here since we don't have anything to service. */
  1520. /* only Re-enable if diabled by irq */
  1521. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1522. iwl_enable_interrupts(priv);
  1523. spin_unlock(&priv->lock);
  1524. return IRQ_NONE;
  1525. }
  1526. EXPORT_SYMBOL(iwl_isr_legacy);
  1527. int iwl_send_bt_config(struct iwl_priv *priv)
  1528. {
  1529. struct iwl_bt_cmd bt_cmd = {
  1530. .flags = 3,
  1531. .lead_time = 0xAA,
  1532. .max_kill = 1,
  1533. .kill_ack_mask = 0,
  1534. .kill_cts_mask = 0,
  1535. };
  1536. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1537. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1538. }
  1539. EXPORT_SYMBOL(iwl_send_bt_config);
  1540. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
  1541. {
  1542. u32 stat_flags = 0;
  1543. struct iwl_host_cmd cmd = {
  1544. .id = REPLY_STATISTICS_CMD,
  1545. .meta.flags = flags,
  1546. .len = sizeof(stat_flags),
  1547. .data = (u8 *) &stat_flags,
  1548. };
  1549. return iwl_send_cmd(priv, &cmd);
  1550. }
  1551. EXPORT_SYMBOL(iwl_send_statistics_request);
  1552. /**
  1553. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1554. * using sample data 100 bytes apart. If these sample points are good,
  1555. * it's a pretty good bet that everything between them is good, too.
  1556. */
  1557. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1558. {
  1559. u32 val;
  1560. int ret = 0;
  1561. u32 errcnt = 0;
  1562. u32 i;
  1563. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1564. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1565. /* read data comes through single port, auto-incr addr */
  1566. /* NOTE: Use the debugless read so we don't flood kernel log
  1567. * if IWL_DL_IO is set */
  1568. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1569. i + IWL49_RTC_INST_LOWER_BOUND);
  1570. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1571. if (val != le32_to_cpu(*image)) {
  1572. ret = -EIO;
  1573. errcnt++;
  1574. if (errcnt >= 3)
  1575. break;
  1576. }
  1577. }
  1578. return ret;
  1579. }
  1580. /**
  1581. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1582. * looking at all data.
  1583. */
  1584. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1585. u32 len)
  1586. {
  1587. u32 val;
  1588. u32 save_len = len;
  1589. int ret = 0;
  1590. u32 errcnt;
  1591. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1592. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1593. IWL49_RTC_INST_LOWER_BOUND);
  1594. errcnt = 0;
  1595. for (; len > 0; len -= sizeof(u32), image++) {
  1596. /* read data comes through single port, auto-incr addr */
  1597. /* NOTE: Use the debugless read so we don't flood kernel log
  1598. * if IWL_DL_IO is set */
  1599. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1600. if (val != le32_to_cpu(*image)) {
  1601. IWL_ERR(priv, "uCode INST section is invalid at "
  1602. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1603. save_len - len, val, le32_to_cpu(*image));
  1604. ret = -EIO;
  1605. errcnt++;
  1606. if (errcnt >= 20)
  1607. break;
  1608. }
  1609. }
  1610. if (!errcnt)
  1611. IWL_DEBUG_INFO(priv,
  1612. "ucode image in INSTRUCTION memory is good\n");
  1613. return ret;
  1614. }
  1615. /**
  1616. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1617. * and verify its contents
  1618. */
  1619. int iwl_verify_ucode(struct iwl_priv *priv)
  1620. {
  1621. __le32 *image;
  1622. u32 len;
  1623. int ret;
  1624. /* Try bootstrap */
  1625. image = (__le32 *)priv->ucode_boot.v_addr;
  1626. len = priv->ucode_boot.len;
  1627. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1628. if (!ret) {
  1629. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1630. return 0;
  1631. }
  1632. /* Try initialize */
  1633. image = (__le32 *)priv->ucode_init.v_addr;
  1634. len = priv->ucode_init.len;
  1635. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1636. if (!ret) {
  1637. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1638. return 0;
  1639. }
  1640. /* Try runtime/protocol */
  1641. image = (__le32 *)priv->ucode_code.v_addr;
  1642. len = priv->ucode_code.len;
  1643. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1644. if (!ret) {
  1645. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1646. return 0;
  1647. }
  1648. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1649. /* Since nothing seems to match, show first several data entries in
  1650. * instruction SRAM, so maybe visual inspection will give a clue.
  1651. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1652. image = (__le32 *)priv->ucode_boot.v_addr;
  1653. len = priv->ucode_boot.len;
  1654. ret = iwl_verify_inst_full(priv, image, len);
  1655. return ret;
  1656. }
  1657. EXPORT_SYMBOL(iwl_verify_ucode);
  1658. static const char *desc_lookup_text[] = {
  1659. "OK",
  1660. "FAIL",
  1661. "BAD_PARAM",
  1662. "BAD_CHECKSUM",
  1663. "NMI_INTERRUPT_WDG",
  1664. "SYSASSERT",
  1665. "FATAL_ERROR",
  1666. "BAD_COMMAND",
  1667. "HW_ERROR_TUNE_LOCK",
  1668. "HW_ERROR_TEMPERATURE",
  1669. "ILLEGAL_CHAN_FREQ",
  1670. "VCC_NOT_STABLE",
  1671. "FH_ERROR",
  1672. "NMI_INTERRUPT_HOST",
  1673. "NMI_INTERRUPT_ACTION_PT",
  1674. "NMI_INTERRUPT_UNKNOWN",
  1675. "UCODE_VERSION_MISMATCH",
  1676. "HW_ERROR_ABS_LOCK",
  1677. "HW_ERROR_CAL_LOCK_FAIL",
  1678. "NMI_INTERRUPT_INST_ACTION_PT",
  1679. "NMI_INTERRUPT_DATA_ACTION_PT",
  1680. "NMI_TRM_HW_ER",
  1681. "NMI_INTERRUPT_TRM",
  1682. "NMI_INTERRUPT_BREAK_POINT"
  1683. "DEBUG_0",
  1684. "DEBUG_1",
  1685. "DEBUG_2",
  1686. "DEBUG_3",
  1687. "UNKNOWN"
  1688. };
  1689. static const char *desc_lookup(int i)
  1690. {
  1691. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1692. if (i < 0 || i > max)
  1693. i = max;
  1694. return desc_lookup_text[i];
  1695. }
  1696. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1697. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1698. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1699. {
  1700. u32 data2, line;
  1701. u32 desc, time, count, base, data1;
  1702. u32 blink1, blink2, ilink1, ilink2;
  1703. if (priv->ucode_type == UCODE_INIT)
  1704. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1705. else
  1706. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1707. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1708. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1709. return;
  1710. }
  1711. count = iwl_read_targ_mem(priv, base);
  1712. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1713. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1714. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1715. priv->status, count);
  1716. }
  1717. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1718. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1719. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1720. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1721. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1722. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1723. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1724. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1725. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1726. IWL_ERR(priv, "Desc Time "
  1727. "data1 data2 line\n");
  1728. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1729. desc_lookup(desc), desc, time, data1, data2, line);
  1730. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1731. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1732. ilink1, ilink2);
  1733. }
  1734. EXPORT_SYMBOL(iwl_dump_nic_error_log);
  1735. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1736. /**
  1737. * iwl_print_event_log - Dump error event log to syslog
  1738. *
  1739. */
  1740. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1741. u32 num_events, u32 mode)
  1742. {
  1743. u32 i;
  1744. u32 base; /* SRAM byte address of event log header */
  1745. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1746. u32 ptr; /* SRAM byte address of log data */
  1747. u32 ev, time, data; /* event log data */
  1748. if (num_events == 0)
  1749. return;
  1750. if (priv->ucode_type == UCODE_INIT)
  1751. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1752. else
  1753. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1754. if (mode == 0)
  1755. event_size = 2 * sizeof(u32);
  1756. else
  1757. event_size = 3 * sizeof(u32);
  1758. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1759. /* "time" is actually "data" for mode 0 (no timestamp).
  1760. * place event id # at far right for easier visual parsing. */
  1761. for (i = 0; i < num_events; i++) {
  1762. ev = iwl_read_targ_mem(priv, ptr);
  1763. ptr += sizeof(u32);
  1764. time = iwl_read_targ_mem(priv, ptr);
  1765. ptr += sizeof(u32);
  1766. if (mode == 0) {
  1767. /* data, ev */
  1768. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1769. } else {
  1770. data = iwl_read_targ_mem(priv, ptr);
  1771. ptr += sizeof(u32);
  1772. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1773. time, data, ev);
  1774. }
  1775. }
  1776. }
  1777. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1778. {
  1779. u32 base; /* SRAM byte address of event log header */
  1780. u32 capacity; /* event log capacity in # entries */
  1781. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1782. u32 num_wraps; /* # times uCode wrapped to top of log */
  1783. u32 next_entry; /* index of next entry to be written by uCode */
  1784. u32 size; /* # entries that we'll print */
  1785. if (priv->ucode_type == UCODE_INIT)
  1786. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1787. else
  1788. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1789. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1790. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1791. return;
  1792. }
  1793. /* event log header */
  1794. capacity = iwl_read_targ_mem(priv, base);
  1795. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1796. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1797. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1798. size = num_wraps ? capacity : next_entry;
  1799. /* bail out if nothing in log */
  1800. if (size == 0) {
  1801. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1802. return;
  1803. }
  1804. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1805. size, num_wraps);
  1806. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1807. * i.e the next one that uCode would fill. */
  1808. if (num_wraps)
  1809. iwl_print_event_log(priv, next_entry,
  1810. capacity - next_entry, mode);
  1811. /* (then/else) start at top of log */
  1812. iwl_print_event_log(priv, 0, next_entry, mode);
  1813. }
  1814. EXPORT_SYMBOL(iwl_dump_nic_event_log);
  1815. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1816. {
  1817. struct iwl_ct_kill_config cmd;
  1818. unsigned long flags;
  1819. int ret = 0;
  1820. spin_lock_irqsave(&priv->lock, flags);
  1821. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1822. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1823. spin_unlock_irqrestore(&priv->lock, flags);
  1824. cmd.critical_temperature_R =
  1825. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1826. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1827. sizeof(cmd), &cmd);
  1828. if (ret)
  1829. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1830. else
  1831. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
  1832. "critical temperature is %d\n",
  1833. cmd.critical_temperature_R);
  1834. }
  1835. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1836. /*
  1837. * CARD_STATE_CMD
  1838. *
  1839. * Use: Sets the device's internal card state to enable, disable, or halt
  1840. *
  1841. * When in the 'enable' state the card operates as normal.
  1842. * When in the 'disable' state, the card enters into a low power mode.
  1843. * When in the 'halt' state, the card is shut down and must be fully
  1844. * restarted to come back on.
  1845. */
  1846. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1847. {
  1848. struct iwl_host_cmd cmd = {
  1849. .id = REPLY_CARD_STATE_CMD,
  1850. .len = sizeof(u32),
  1851. .data = &flags,
  1852. .meta.flags = meta_flag,
  1853. };
  1854. return iwl_send_cmd(priv, &cmd);
  1855. }
  1856. EXPORT_SYMBOL(iwl_send_card_state);
  1857. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1858. struct iwl_rx_mem_buffer *rxb)
  1859. {
  1860. #ifdef CONFIG_IWLWIFI_DEBUG
  1861. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1862. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1863. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1864. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1865. #endif
  1866. }
  1867. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1868. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1869. struct iwl_rx_mem_buffer *rxb)
  1870. {
  1871. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1872. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1873. "notification for %s:\n",
  1874. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  1875. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  1876. }
  1877. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1878. void iwl_rx_reply_error(struct iwl_priv *priv,
  1879. struct iwl_rx_mem_buffer *rxb)
  1880. {
  1881. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1882. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1883. "seq 0x%04X ser 0x%08X\n",
  1884. le32_to_cpu(pkt->u.err_resp.error_type),
  1885. get_cmd_string(pkt->u.err_resp.cmd_id),
  1886. pkt->u.err_resp.cmd_id,
  1887. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1888. le32_to_cpu(pkt->u.err_resp.error_info));
  1889. }
  1890. EXPORT_SYMBOL(iwl_rx_reply_error);
  1891. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1892. {
  1893. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1894. }
  1895. EXPORT_SYMBOL(iwl_clear_isr_stats);
  1896. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1897. const struct ieee80211_tx_queue_params *params)
  1898. {
  1899. struct iwl_priv *priv = hw->priv;
  1900. unsigned long flags;
  1901. int q;
  1902. IWL_DEBUG_MAC80211(priv, "enter\n");
  1903. if (!iwl_is_ready_rf(priv)) {
  1904. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1905. return -EIO;
  1906. }
  1907. if (queue >= AC_NUM) {
  1908. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1909. return 0;
  1910. }
  1911. q = AC_NUM - 1 - queue;
  1912. spin_lock_irqsave(&priv->lock, flags);
  1913. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1914. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1915. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1916. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1917. cpu_to_le16((params->txop * 32));
  1918. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1919. priv->qos_data.qos_active = 1;
  1920. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1921. iwl_activate_qos(priv, 1);
  1922. else if (priv->assoc_id && iwl_is_associated(priv))
  1923. iwl_activate_qos(priv, 0);
  1924. spin_unlock_irqrestore(&priv->lock, flags);
  1925. IWL_DEBUG_MAC80211(priv, "leave\n");
  1926. return 0;
  1927. }
  1928. EXPORT_SYMBOL(iwl_mac_conf_tx);
  1929. static void iwl_ht_conf(struct iwl_priv *priv,
  1930. struct ieee80211_bss_conf *bss_conf)
  1931. {
  1932. struct ieee80211_sta_ht_cap *ht_conf;
  1933. struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
  1934. struct ieee80211_sta *sta;
  1935. IWL_DEBUG_MAC80211(priv, "enter: \n");
  1936. if (!iwl_conf->is_ht)
  1937. return;
  1938. /*
  1939. * It is totally wrong to base global information on something
  1940. * that is valid only when associated, alas, this driver works
  1941. * that way and I don't know how to fix it.
  1942. */
  1943. rcu_read_lock();
  1944. sta = ieee80211_find_sta(priv->hw, priv->bssid);
  1945. if (!sta) {
  1946. rcu_read_unlock();
  1947. return;
  1948. }
  1949. ht_conf = &sta->ht_cap;
  1950. if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
  1951. iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
  1952. if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
  1953. iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
  1954. iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
  1955. iwl_conf->max_amsdu_size =
  1956. !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
  1957. iwl_conf->supported_chan_width =
  1958. !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
  1959. /*
  1960. * XXX: The HT configuration needs to be moved into iwl_mac_config()
  1961. * to be done there correctly.
  1962. */
  1963. iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
  1964. if (conf_is_ht40_minus(&priv->hw->conf))
  1965. iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  1966. else if (conf_is_ht40_plus(&priv->hw->conf))
  1967. iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  1968. /* If no above or below channel supplied disable FAT channel */
  1969. if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE &&
  1970. iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  1971. iwl_conf->supported_chan_width = 0;
  1972. iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
  1973. memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
  1974. iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0;
  1975. iwl_conf->ht_protection =
  1976. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  1977. iwl_conf->non_GF_STA_present =
  1978. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1979. rcu_read_unlock();
  1980. IWL_DEBUG_MAC80211(priv, "leave\n");
  1981. }
  1982. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  1983. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  1984. struct ieee80211_vif *vif,
  1985. struct ieee80211_bss_conf *bss_conf,
  1986. u32 changes)
  1987. {
  1988. struct iwl_priv *priv = hw->priv;
  1989. int ret;
  1990. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  1991. if (!iwl_is_alive(priv))
  1992. return;
  1993. mutex_lock(&priv->mutex);
  1994. if (changes & BSS_CHANGED_BEACON &&
  1995. priv->iw_mode == NL80211_IFTYPE_AP) {
  1996. dev_kfree_skb(priv->ibss_beacon);
  1997. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  1998. }
  1999. if (changes & BSS_CHANGED_BEACON_INT) {
  2000. priv->beacon_int = bss_conf->beacon_int;
  2001. /* TODO: in AP mode, do something to make this take effect */
  2002. }
  2003. if (changes & BSS_CHANGED_BSSID) {
  2004. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  2005. /*
  2006. * If there is currently a HW scan going on in the
  2007. * background then we need to cancel it else the RXON
  2008. * below/in post_associate will fail.
  2009. */
  2010. if (iwl_scan_cancel_timeout(priv, 100)) {
  2011. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  2012. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  2013. mutex_unlock(&priv->mutex);
  2014. return;
  2015. }
  2016. /* mac80211 only sets assoc when in STATION mode */
  2017. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  2018. bss_conf->assoc) {
  2019. memcpy(priv->staging_rxon.bssid_addr,
  2020. bss_conf->bssid, ETH_ALEN);
  2021. /* currently needed in a few places */
  2022. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2023. } else {
  2024. priv->staging_rxon.filter_flags &=
  2025. ~RXON_FILTER_ASSOC_MSK;
  2026. }
  2027. }
  2028. /*
  2029. * This needs to be after setting the BSSID in case
  2030. * mac80211 decides to do both changes at once because
  2031. * it will invoke post_associate.
  2032. */
  2033. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2034. changes & BSS_CHANGED_BEACON) {
  2035. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2036. if (beacon)
  2037. iwl_mac_beacon_update(hw, beacon);
  2038. }
  2039. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2040. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2041. bss_conf->use_short_preamble);
  2042. if (bss_conf->use_short_preamble)
  2043. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2044. else
  2045. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2046. }
  2047. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2048. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2049. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2050. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2051. else
  2052. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2053. }
  2054. if (changes & BSS_CHANGED_BASIC_RATES) {
  2055. /* XXX use this information
  2056. *
  2057. * To do that, remove code from iwl_set_rate() and put something
  2058. * like this here:
  2059. *
  2060. if (A-band)
  2061. priv->staging_rxon.ofdm_basic_rates =
  2062. bss_conf->basic_rates;
  2063. else
  2064. priv->staging_rxon.ofdm_basic_rates =
  2065. bss_conf->basic_rates >> 4;
  2066. priv->staging_rxon.cck_basic_rates =
  2067. bss_conf->basic_rates & 0xF;
  2068. */
  2069. }
  2070. if (changes & BSS_CHANGED_HT) {
  2071. iwl_ht_conf(priv, bss_conf);
  2072. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2073. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2074. }
  2075. if (changes & BSS_CHANGED_ASSOC) {
  2076. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2077. if (bss_conf->assoc) {
  2078. priv->assoc_id = bss_conf->aid;
  2079. priv->beacon_int = bss_conf->beacon_int;
  2080. priv->power_data.dtim_period = bss_conf->dtim_period;
  2081. priv->timestamp = bss_conf->timestamp;
  2082. priv->assoc_capability = bss_conf->assoc_capability;
  2083. /*
  2084. * We have just associated, don't start scan too early
  2085. * leave time for EAPOL exchange to complete.
  2086. *
  2087. * XXX: do this in mac80211
  2088. */
  2089. priv->next_scan_jiffies = jiffies +
  2090. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2091. if (!iwl_is_rfkill(priv))
  2092. priv->cfg->ops->lib->post_associate(priv);
  2093. } else
  2094. priv->assoc_id = 0;
  2095. }
  2096. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2097. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2098. changes);
  2099. ret = iwl_send_rxon_assoc(priv);
  2100. if (!ret) {
  2101. /* Sync active_rxon with latest change. */
  2102. memcpy((void *)&priv->active_rxon,
  2103. &priv->staging_rxon,
  2104. sizeof(struct iwl_rxon_cmd));
  2105. }
  2106. }
  2107. mutex_unlock(&priv->mutex);
  2108. IWL_DEBUG_MAC80211(priv, "leave\n");
  2109. }
  2110. EXPORT_SYMBOL(iwl_bss_info_changed);
  2111. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2112. {
  2113. struct iwl_priv *priv = hw->priv;
  2114. unsigned long flags;
  2115. __le64 timestamp;
  2116. IWL_DEBUG_MAC80211(priv, "enter\n");
  2117. if (!iwl_is_ready_rf(priv)) {
  2118. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2119. return -EIO;
  2120. }
  2121. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2122. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2123. return -EIO;
  2124. }
  2125. spin_lock_irqsave(&priv->lock, flags);
  2126. if (priv->ibss_beacon)
  2127. dev_kfree_skb(priv->ibss_beacon);
  2128. priv->ibss_beacon = skb;
  2129. priv->assoc_id = 0;
  2130. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2131. priv->timestamp = le64_to_cpu(timestamp);
  2132. IWL_DEBUG_MAC80211(priv, "leave\n");
  2133. spin_unlock_irqrestore(&priv->lock, flags);
  2134. iwl_reset_qos(priv);
  2135. priv->cfg->ops->lib->post_associate(priv);
  2136. return 0;
  2137. }
  2138. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2139. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2140. {
  2141. if (mode == NL80211_IFTYPE_ADHOC) {
  2142. const struct iwl_channel_info *ch_info;
  2143. ch_info = iwl_get_channel_info(priv,
  2144. priv->band,
  2145. le16_to_cpu(priv->staging_rxon.channel));
  2146. if (!ch_info || !is_channel_ibss(ch_info)) {
  2147. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2148. le16_to_cpu(priv->staging_rxon.channel));
  2149. return -EINVAL;
  2150. }
  2151. }
  2152. iwl_connection_init_rx_config(priv, mode);
  2153. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2154. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2155. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2156. iwl_clear_stations_table(priv);
  2157. /* dont commit rxon if rf-kill is on*/
  2158. if (!iwl_is_ready_rf(priv))
  2159. return -EAGAIN;
  2160. iwlcore_commit_rxon(priv);
  2161. return 0;
  2162. }
  2163. EXPORT_SYMBOL(iwl_set_mode);
  2164. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2165. struct ieee80211_if_init_conf *conf)
  2166. {
  2167. struct iwl_priv *priv = hw->priv;
  2168. unsigned long flags;
  2169. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2170. if (priv->vif) {
  2171. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2172. return -EOPNOTSUPP;
  2173. }
  2174. spin_lock_irqsave(&priv->lock, flags);
  2175. priv->vif = conf->vif;
  2176. priv->iw_mode = conf->type;
  2177. spin_unlock_irqrestore(&priv->lock, flags);
  2178. mutex_lock(&priv->mutex);
  2179. if (conf->mac_addr) {
  2180. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2181. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2182. }
  2183. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2184. /* we are not ready, will run again when ready */
  2185. set_bit(STATUS_MODE_PENDING, &priv->status);
  2186. mutex_unlock(&priv->mutex);
  2187. IWL_DEBUG_MAC80211(priv, "leave\n");
  2188. return 0;
  2189. }
  2190. EXPORT_SYMBOL(iwl_mac_add_interface);
  2191. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2192. struct ieee80211_if_init_conf *conf)
  2193. {
  2194. struct iwl_priv *priv = hw->priv;
  2195. IWL_DEBUG_MAC80211(priv, "enter\n");
  2196. mutex_lock(&priv->mutex);
  2197. if (iwl_is_ready_rf(priv)) {
  2198. iwl_scan_cancel_timeout(priv, 100);
  2199. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2200. iwlcore_commit_rxon(priv);
  2201. }
  2202. if (priv->vif == conf->vif) {
  2203. priv->vif = NULL;
  2204. memset(priv->bssid, 0, ETH_ALEN);
  2205. }
  2206. mutex_unlock(&priv->mutex);
  2207. IWL_DEBUG_MAC80211(priv, "leave\n");
  2208. }
  2209. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2210. /**
  2211. * iwl_mac_config - mac80211 config callback
  2212. *
  2213. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2214. * be set inappropriately and the driver currently sets the hardware up to
  2215. * use it whenever needed.
  2216. */
  2217. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2218. {
  2219. struct iwl_priv *priv = hw->priv;
  2220. const struct iwl_channel_info *ch_info;
  2221. struct ieee80211_conf *conf = &hw->conf;
  2222. unsigned long flags = 0;
  2223. int ret = 0;
  2224. u16 ch;
  2225. int scan_active = 0;
  2226. mutex_lock(&priv->mutex);
  2227. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2228. conf->channel->hw_value, changed);
  2229. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2230. test_bit(STATUS_SCANNING, &priv->status))) {
  2231. scan_active = 1;
  2232. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2233. }
  2234. /* during scanning mac80211 will delay channel setting until
  2235. * scan finish with changed = 0
  2236. */
  2237. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2238. if (scan_active)
  2239. goto set_ch_out;
  2240. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2241. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2242. if (!is_channel_valid(ch_info)) {
  2243. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2244. ret = -EINVAL;
  2245. goto set_ch_out;
  2246. }
  2247. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2248. !is_channel_ibss(ch_info)) {
  2249. IWL_ERR(priv, "channel %d in band %d not "
  2250. "IBSS channel\n",
  2251. conf->channel->hw_value, conf->channel->band);
  2252. ret = -EINVAL;
  2253. goto set_ch_out;
  2254. }
  2255. priv->current_ht_config.is_ht = conf_is_ht(conf);
  2256. spin_lock_irqsave(&priv->lock, flags);
  2257. /* if we are switching from ht to 2.4 clear flags
  2258. * from any ht related info since 2.4 does not
  2259. * support ht */
  2260. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2261. priv->staging_rxon.flags = 0;
  2262. iwl_set_rxon_channel(priv, conf->channel);
  2263. iwl_set_flags_for_band(priv, conf->channel->band);
  2264. spin_unlock_irqrestore(&priv->lock, flags);
  2265. set_ch_out:
  2266. /* The list of supported rates and rate mask can be different
  2267. * for each band; since the band may have changed, reset
  2268. * the rate mask to what mac80211 lists */
  2269. iwl_set_rate(priv);
  2270. }
  2271. if (changed & IEEE80211_CONF_CHANGE_PS &&
  2272. priv->iw_mode == NL80211_IFTYPE_STATION) {
  2273. priv->power_data.power_disabled =
  2274. !(conf->flags & IEEE80211_CONF_PS);
  2275. ret = iwl_power_update_mode(priv, 0);
  2276. if (ret)
  2277. IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
  2278. }
  2279. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2280. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2281. priv->tx_power_user_lmt, conf->power_level);
  2282. iwl_set_tx_power(priv, conf->power_level, false);
  2283. }
  2284. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2285. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2286. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2287. if (!iwl_is_ready(priv)) {
  2288. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2289. goto out;
  2290. }
  2291. if (scan_active)
  2292. goto out;
  2293. if (memcmp(&priv->active_rxon,
  2294. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2295. iwlcore_commit_rxon(priv);
  2296. else
  2297. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2298. out:
  2299. IWL_DEBUG_MAC80211(priv, "leave\n");
  2300. mutex_unlock(&priv->mutex);
  2301. return ret;
  2302. }
  2303. EXPORT_SYMBOL(iwl_mac_config);
  2304. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2305. struct ieee80211_tx_queue_stats *stats)
  2306. {
  2307. struct iwl_priv *priv = hw->priv;
  2308. int i, avail;
  2309. struct iwl_tx_queue *txq;
  2310. struct iwl_queue *q;
  2311. unsigned long flags;
  2312. IWL_DEBUG_MAC80211(priv, "enter\n");
  2313. if (!iwl_is_ready_rf(priv)) {
  2314. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2315. return -EIO;
  2316. }
  2317. spin_lock_irqsave(&priv->lock, flags);
  2318. for (i = 0; i < AC_NUM; i++) {
  2319. txq = &priv->txq[i];
  2320. q = &txq->q;
  2321. avail = iwl_queue_space(q);
  2322. stats[i].len = q->n_window - avail;
  2323. stats[i].limit = q->n_window - q->high_mark;
  2324. stats[i].count = q->n_window;
  2325. }
  2326. spin_unlock_irqrestore(&priv->lock, flags);
  2327. IWL_DEBUG_MAC80211(priv, "leave\n");
  2328. return 0;
  2329. }
  2330. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2331. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2332. {
  2333. struct iwl_priv *priv = hw->priv;
  2334. unsigned long flags;
  2335. mutex_lock(&priv->mutex);
  2336. IWL_DEBUG_MAC80211(priv, "enter\n");
  2337. spin_lock_irqsave(&priv->lock, flags);
  2338. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
  2339. spin_unlock_irqrestore(&priv->lock, flags);
  2340. iwl_reset_qos(priv);
  2341. spin_lock_irqsave(&priv->lock, flags);
  2342. priv->assoc_id = 0;
  2343. priv->assoc_capability = 0;
  2344. priv->assoc_station_added = 0;
  2345. /* new association get rid of ibss beacon skb */
  2346. if (priv->ibss_beacon)
  2347. dev_kfree_skb(priv->ibss_beacon);
  2348. priv->ibss_beacon = NULL;
  2349. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2350. priv->timestamp = 0;
  2351. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2352. priv->beacon_int = 0;
  2353. spin_unlock_irqrestore(&priv->lock, flags);
  2354. if (!iwl_is_ready_rf(priv)) {
  2355. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2356. mutex_unlock(&priv->mutex);
  2357. return;
  2358. }
  2359. /* we are restarting association process
  2360. * clear RXON_FILTER_ASSOC_MSK bit
  2361. */
  2362. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2363. iwl_scan_cancel_timeout(priv, 100);
  2364. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2365. iwlcore_commit_rxon(priv);
  2366. }
  2367. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2368. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2369. mutex_unlock(&priv->mutex);
  2370. return;
  2371. }
  2372. iwl_set_rate(priv);
  2373. mutex_unlock(&priv->mutex);
  2374. IWL_DEBUG_MAC80211(priv, "leave\n");
  2375. }
  2376. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2377. #ifdef CONFIG_PM
  2378. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2379. {
  2380. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2381. /*
  2382. * This function is called when system goes into suspend state
  2383. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2384. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2385. * it will not call apm_ops.stop() to stop the DMA operation.
  2386. * Calling apm_ops.stop here to make sure we stop the DMA.
  2387. */
  2388. priv->cfg->ops->lib->apm_ops.stop(priv);
  2389. pci_save_state(pdev);
  2390. pci_disable_device(pdev);
  2391. pci_set_power_state(pdev, PCI_D3hot);
  2392. return 0;
  2393. }
  2394. EXPORT_SYMBOL(iwl_pci_suspend);
  2395. int iwl_pci_resume(struct pci_dev *pdev)
  2396. {
  2397. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2398. int ret;
  2399. pci_set_power_state(pdev, PCI_D0);
  2400. ret = pci_enable_device(pdev);
  2401. if (ret)
  2402. return ret;
  2403. pci_restore_state(pdev);
  2404. iwl_enable_interrupts(priv);
  2405. return 0;
  2406. }
  2407. EXPORT_SYMBOL(iwl_pci_resume);
  2408. #endif /* CONFIG_PM */