platsmp.c 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109
  1. /*
  2. * Symmetric Multi Processing (SMP) support for Armada XP
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Yehuda Yitschak <yehuday@marvell.com>
  8. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
  16. * This file implements the routines for preparing the SMP infrastructure
  17. * and waking up the secondary CPUs
  18. */
  19. #include <linux/init.h>
  20. #include <linux/smp.h>
  21. #include <linux/clk.h>
  22. #include <linux/of.h>
  23. #include <linux/mbus.h>
  24. #include <asm/cacheflush.h>
  25. #include <asm/smp_plat.h>
  26. #include "common.h"
  27. #include "armada-370-xp.h"
  28. #include "pmsu.h"
  29. #include "coherency.h"
  30. static struct clk *__init get_cpu_clk(int cpu)
  31. {
  32. struct clk *cpu_clk;
  33. struct device_node *np = of_get_cpu_node(cpu, NULL);
  34. if (WARN(!np, "missing cpu node\n"))
  35. return NULL;
  36. cpu_clk = of_clk_get(np, 0);
  37. if (WARN_ON(IS_ERR(cpu_clk)))
  38. return NULL;
  39. return cpu_clk;
  40. }
  41. void __init set_secondary_cpus_clock(void)
  42. {
  43. int thiscpu, cpu;
  44. unsigned long rate;
  45. struct clk *cpu_clk;
  46. thiscpu = smp_processor_id();
  47. cpu_clk = get_cpu_clk(thiscpu);
  48. if (!cpu_clk)
  49. return;
  50. clk_prepare_enable(cpu_clk);
  51. rate = clk_get_rate(cpu_clk);
  52. /* set all the other CPU clk to the same rate than the boot CPU */
  53. for_each_possible_cpu(cpu) {
  54. if (cpu == thiscpu)
  55. continue;
  56. cpu_clk = get_cpu_clk(cpu);
  57. if (!cpu_clk)
  58. return;
  59. clk_set_rate(cpu_clk, rate);
  60. }
  61. }
  62. static void armada_xp_secondary_init(unsigned int cpu)
  63. {
  64. armada_xp_mpic_smp_cpu_init();
  65. }
  66. static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
  67. {
  68. pr_info("Booting CPU %d\n", cpu);
  69. armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
  70. return 0;
  71. }
  72. static void __init armada_xp_smp_init_cpus(void)
  73. {
  74. unsigned int ncores = num_possible_cpus();
  75. if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
  76. panic("Invalid number of CPUs in DT\n");
  77. set_smp_cross_call(armada_mpic_send_doorbell);
  78. }
  79. void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
  80. {
  81. set_secondary_cpus_clock();
  82. flush_cache_all();
  83. set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
  84. mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
  85. }
  86. struct smp_operations armada_xp_smp_ops __initdata = {
  87. .smp_init_cpus = armada_xp_smp_init_cpus,
  88. .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
  89. .smp_secondary_init = armada_xp_secondary_init,
  90. .smp_boot_secondary = armada_xp_boot_secondary,
  91. #ifdef CONFIG_HOTPLUG_CPU
  92. .cpu_die = armada_xp_cpu_die,
  93. #endif
  94. };