gpmc.c 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448
  1. /*
  2. * GPMC support functions
  3. *
  4. * Copyright (C) 2005-2006 Nokia Corporation
  5. *
  6. * Author: Juha Yrjola
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #undef DEBUG
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/ioport.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/module.h>
  20. #include <asm/io.h>
  21. #include <asm/mach-types.h>
  22. #include <mach/gpmc.h>
  23. #include <mach/sdrc.h>
  24. /* GPMC register offsets */
  25. #define GPMC_REVISION 0x00
  26. #define GPMC_SYSCONFIG 0x10
  27. #define GPMC_SYSSTATUS 0x14
  28. #define GPMC_IRQSTATUS 0x18
  29. #define GPMC_IRQENABLE 0x1c
  30. #define GPMC_TIMEOUT_CONTROL 0x40
  31. #define GPMC_ERR_ADDRESS 0x44
  32. #define GPMC_ERR_TYPE 0x48
  33. #define GPMC_CONFIG 0x50
  34. #define GPMC_STATUS 0x54
  35. #define GPMC_PREFETCH_CONFIG1 0x1e0
  36. #define GPMC_PREFETCH_CONFIG2 0x1e4
  37. #define GPMC_PREFETCH_CONTROL 0x1ec
  38. #define GPMC_PREFETCH_STATUS 0x1f0
  39. #define GPMC_ECC_CONFIG 0x1f4
  40. #define GPMC_ECC_CONTROL 0x1f8
  41. #define GPMC_ECC_SIZE_CONFIG 0x1fc
  42. #define GPMC_CS0 0x60
  43. #define GPMC_CS_SIZE 0x30
  44. #define GPMC_MEM_START 0x00000000
  45. #define GPMC_MEM_END 0x3FFFFFFF
  46. #define BOOT_ROM_SPACE 0x100000 /* 1MB */
  47. #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
  48. #define GPMC_SECTION_SHIFT 28 /* 128 MB */
  49. static struct resource gpmc_mem_root;
  50. static struct resource gpmc_cs_mem[GPMC_CS_NUM];
  51. static DEFINE_SPINLOCK(gpmc_mem_lock);
  52. static unsigned gpmc_cs_map;
  53. static void __iomem *gpmc_base;
  54. static struct clk *gpmc_l3_clk;
  55. static void gpmc_write_reg(int idx, u32 val)
  56. {
  57. __raw_writel(val, gpmc_base + idx);
  58. }
  59. static u32 gpmc_read_reg(int idx)
  60. {
  61. return __raw_readl(gpmc_base + idx);
  62. }
  63. void gpmc_cs_write_reg(int cs, int idx, u32 val)
  64. {
  65. void __iomem *reg_addr;
  66. reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
  67. __raw_writel(val, reg_addr);
  68. }
  69. u32 gpmc_cs_read_reg(int cs, int idx)
  70. {
  71. void __iomem *reg_addr;
  72. reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
  73. return __raw_readl(reg_addr);
  74. }
  75. /* TODO: Add support for gpmc_fck to clock framework and use it */
  76. unsigned long gpmc_get_fclk_period(void)
  77. {
  78. unsigned long rate = clk_get_rate(gpmc_l3_clk);
  79. if (rate == 0) {
  80. printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
  81. return 0;
  82. }
  83. rate /= 1000;
  84. rate = 1000000000 / rate; /* In picoseconds */
  85. return rate;
  86. }
  87. unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
  88. {
  89. unsigned long tick_ps;
  90. /* Calculate in picosecs to yield more exact results */
  91. tick_ps = gpmc_get_fclk_period();
  92. return (time_ns * 1000 + tick_ps - 1) / tick_ps;
  93. }
  94. unsigned int gpmc_ticks_to_ns(unsigned int ticks)
  95. {
  96. return ticks * gpmc_get_fclk_period() / 1000;
  97. }
  98. unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
  99. {
  100. unsigned long ticks = gpmc_ns_to_ticks(time_ns);
  101. return ticks * gpmc_get_fclk_period() / 1000;
  102. }
  103. #ifdef DEBUG
  104. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
  105. int time, const char *name)
  106. #else
  107. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
  108. int time)
  109. #endif
  110. {
  111. u32 l;
  112. int ticks, mask, nr_bits;
  113. if (time == 0)
  114. ticks = 0;
  115. else
  116. ticks = gpmc_ns_to_ticks(time);
  117. nr_bits = end_bit - st_bit + 1;
  118. if (ticks >= 1 << nr_bits) {
  119. #ifdef DEBUG
  120. printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
  121. cs, name, time, ticks, 1 << nr_bits);
  122. #endif
  123. return -1;
  124. }
  125. mask = (1 << nr_bits) - 1;
  126. l = gpmc_cs_read_reg(cs, reg);
  127. #ifdef DEBUG
  128. printk(KERN_INFO
  129. "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
  130. cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
  131. (l >> st_bit) & mask, time);
  132. #endif
  133. l &= ~(mask << st_bit);
  134. l |= ticks << st_bit;
  135. gpmc_cs_write_reg(cs, reg, l);
  136. return 0;
  137. }
  138. #ifdef DEBUG
  139. #define GPMC_SET_ONE(reg, st, end, field) \
  140. if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
  141. t->field, #field) < 0) \
  142. return -1
  143. #else
  144. #define GPMC_SET_ONE(reg, st, end, field) \
  145. if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
  146. return -1
  147. #endif
  148. int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
  149. {
  150. int div;
  151. u32 l;
  152. l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
  153. div = l / gpmc_get_fclk_period();
  154. if (div > 4)
  155. return -1;
  156. if (div <= 0)
  157. div = 1;
  158. return div;
  159. }
  160. int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
  161. {
  162. int div;
  163. u32 l;
  164. div = gpmc_cs_calc_divider(cs, t->sync_clk);
  165. if (div < 0)
  166. return -1;
  167. GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
  168. GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
  169. GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
  170. GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
  171. GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
  172. GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
  173. GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
  174. GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
  175. GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
  176. GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
  177. GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
  178. GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
  179. GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
  180. GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
  181. /* caller is expected to have initialized CONFIG1 to cover
  182. * at least sync vs async
  183. */
  184. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  185. if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
  186. #ifdef DEBUG
  187. printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
  188. cs, (div * gpmc_get_fclk_period()) / 1000, div);
  189. #endif
  190. l &= ~0x03;
  191. l |= (div - 1);
  192. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
  193. }
  194. return 0;
  195. }
  196. static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
  197. {
  198. u32 l;
  199. u32 mask;
  200. mask = (1 << GPMC_SECTION_SHIFT) - size;
  201. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  202. l &= ~0x3f;
  203. l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
  204. l &= ~(0x0f << 8);
  205. l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
  206. l |= 1 << 6; /* CSVALID */
  207. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  208. }
  209. static void gpmc_cs_disable_mem(int cs)
  210. {
  211. u32 l;
  212. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  213. l &= ~(1 << 6); /* CSVALID */
  214. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  215. }
  216. static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
  217. {
  218. u32 l;
  219. u32 mask;
  220. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  221. *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
  222. mask = (l >> 8) & 0x0f;
  223. *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
  224. }
  225. static int gpmc_cs_mem_enabled(int cs)
  226. {
  227. u32 l;
  228. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  229. return l & (1 << 6);
  230. }
  231. int gpmc_cs_set_reserved(int cs, int reserved)
  232. {
  233. if (cs > GPMC_CS_NUM)
  234. return -ENODEV;
  235. gpmc_cs_map &= ~(1 << cs);
  236. gpmc_cs_map |= (reserved ? 1 : 0) << cs;
  237. return 0;
  238. }
  239. int gpmc_cs_reserved(int cs)
  240. {
  241. if (cs > GPMC_CS_NUM)
  242. return -ENODEV;
  243. return gpmc_cs_map & (1 << cs);
  244. }
  245. static unsigned long gpmc_mem_align(unsigned long size)
  246. {
  247. int order;
  248. size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
  249. order = GPMC_CHUNK_SHIFT - 1;
  250. do {
  251. size >>= 1;
  252. order++;
  253. } while (size);
  254. size = 1 << order;
  255. return size;
  256. }
  257. static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
  258. {
  259. struct resource *res = &gpmc_cs_mem[cs];
  260. int r;
  261. size = gpmc_mem_align(size);
  262. spin_lock(&gpmc_mem_lock);
  263. res->start = base;
  264. res->end = base + size - 1;
  265. r = request_resource(&gpmc_mem_root, res);
  266. spin_unlock(&gpmc_mem_lock);
  267. return r;
  268. }
  269. int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
  270. {
  271. struct resource *res = &gpmc_cs_mem[cs];
  272. int r = -1;
  273. if (cs > GPMC_CS_NUM)
  274. return -ENODEV;
  275. size = gpmc_mem_align(size);
  276. if (size > (1 << GPMC_SECTION_SHIFT))
  277. return -ENOMEM;
  278. spin_lock(&gpmc_mem_lock);
  279. if (gpmc_cs_reserved(cs)) {
  280. r = -EBUSY;
  281. goto out;
  282. }
  283. if (gpmc_cs_mem_enabled(cs))
  284. r = adjust_resource(res, res->start & ~(size - 1), size);
  285. if (r < 0)
  286. r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
  287. size, NULL, NULL);
  288. if (r < 0)
  289. goto out;
  290. gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
  291. *base = res->start;
  292. gpmc_cs_set_reserved(cs, 1);
  293. out:
  294. spin_unlock(&gpmc_mem_lock);
  295. return r;
  296. }
  297. EXPORT_SYMBOL(gpmc_cs_request);
  298. void gpmc_cs_free(int cs)
  299. {
  300. spin_lock(&gpmc_mem_lock);
  301. if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
  302. printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
  303. BUG();
  304. spin_unlock(&gpmc_mem_lock);
  305. return;
  306. }
  307. gpmc_cs_disable_mem(cs);
  308. release_resource(&gpmc_cs_mem[cs]);
  309. gpmc_cs_set_reserved(cs, 0);
  310. spin_unlock(&gpmc_mem_lock);
  311. }
  312. EXPORT_SYMBOL(gpmc_cs_free);
  313. static void __init gpmc_mem_init(void)
  314. {
  315. int cs;
  316. unsigned long boot_rom_space = 0;
  317. /* never allocate the first page, to facilitate bug detection;
  318. * even if we didn't boot from ROM.
  319. */
  320. boot_rom_space = BOOT_ROM_SPACE;
  321. /* In apollon the CS0 is mapped as 0x0000 0000 */
  322. if (machine_is_omap_apollon())
  323. boot_rom_space = 0;
  324. gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
  325. gpmc_mem_root.end = GPMC_MEM_END;
  326. /* Reserve all regions that has been set up by bootloader */
  327. for (cs = 0; cs < GPMC_CS_NUM; cs++) {
  328. u32 base, size;
  329. if (!gpmc_cs_mem_enabled(cs))
  330. continue;
  331. gpmc_cs_get_memconf(cs, &base, &size);
  332. if (gpmc_cs_insert_mem(cs, base, size) < 0)
  333. BUG();
  334. }
  335. }
  336. void __init gpmc_init(void)
  337. {
  338. u32 l;
  339. char *ck;
  340. if (cpu_is_omap24xx()) {
  341. ck = "core_l3_ck";
  342. if (cpu_is_omap2420())
  343. l = OMAP2420_GPMC_BASE;
  344. else
  345. l = OMAP34XX_GPMC_BASE;
  346. } else if (cpu_is_omap34xx()) {
  347. ck = "gpmc_fck";
  348. l = OMAP34XX_GPMC_BASE;
  349. }
  350. gpmc_l3_clk = clk_get(NULL, ck);
  351. if (IS_ERR(gpmc_l3_clk)) {
  352. printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
  353. return -ENODEV;
  354. }
  355. gpmc_base = ioremap(l, SZ_4K);
  356. if (!gpmc_base) {
  357. clk_put(gpmc_l3_clk);
  358. printk(KERN_ERR "Could not get GPMC register memory\n");
  359. return -ENOMEM;
  360. }
  361. BUG_ON(IS_ERR(gpmc_l3_clk));
  362. l = gpmc_read_reg(GPMC_REVISION);
  363. printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
  364. /* Set smart idle mode and automatic L3 clock gating */
  365. l = gpmc_read_reg(GPMC_SYSCONFIG);
  366. l &= 0x03 << 3;
  367. l |= (0x02 << 3) | (1 << 0);
  368. gpmc_write_reg(GPMC_SYSCONFIG, l);
  369. gpmc_mem_init();
  370. }