tegra-cpufreq.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * Author:
  5. * Colin Cross <ccross@google.com>
  6. * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/types.h>
  21. #include <linux/sched.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <linux/suspend.h>
  29. static struct cpufreq_frequency_table freq_table[] = {
  30. { .frequency = 216000 },
  31. { .frequency = 312000 },
  32. { .frequency = 456000 },
  33. { .frequency = 608000 },
  34. { .frequency = 760000 },
  35. { .frequency = 816000 },
  36. { .frequency = 912000 },
  37. { .frequency = 1000000 },
  38. { .frequency = CPUFREQ_TABLE_END },
  39. };
  40. #define NUM_CPUS 2
  41. static struct clk *cpu_clk;
  42. static struct clk *pll_x_clk;
  43. static struct clk *pll_p_clk;
  44. static struct clk *emc_clk;
  45. static unsigned long target_cpu_speed[NUM_CPUS];
  46. static DEFINE_MUTEX(tegra_cpu_lock);
  47. static bool is_suspended;
  48. static unsigned int tegra_getspeed(unsigned int cpu)
  49. {
  50. unsigned long rate;
  51. if (cpu >= NUM_CPUS)
  52. return 0;
  53. rate = clk_get_rate(cpu_clk) / 1000;
  54. return rate;
  55. }
  56. static int tegra_cpu_clk_set_rate(unsigned long rate)
  57. {
  58. int ret;
  59. /*
  60. * Take an extra reference to the main pll so it doesn't turn
  61. * off when we move the cpu off of it
  62. */
  63. clk_prepare_enable(pll_x_clk);
  64. ret = clk_set_parent(cpu_clk, pll_p_clk);
  65. if (ret) {
  66. pr_err("Failed to switch cpu to clock pll_p\n");
  67. goto out;
  68. }
  69. if (rate == clk_get_rate(pll_p_clk))
  70. goto out;
  71. ret = clk_set_rate(pll_x_clk, rate);
  72. if (ret) {
  73. pr_err("Failed to change pll_x to %lu\n", rate);
  74. goto out;
  75. }
  76. ret = clk_set_parent(cpu_clk, pll_x_clk);
  77. if (ret) {
  78. pr_err("Failed to switch cpu to clock pll_x\n");
  79. goto out;
  80. }
  81. out:
  82. clk_disable_unprepare(pll_x_clk);
  83. return ret;
  84. }
  85. static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
  86. unsigned long rate)
  87. {
  88. int ret = 0;
  89. struct cpufreq_freqs freqs;
  90. freqs.old = tegra_getspeed(0);
  91. freqs.new = rate;
  92. if (freqs.old == freqs.new)
  93. return ret;
  94. /*
  95. * Vote on memory bus frequency based on cpu frequency
  96. * This sets the minimum frequency, display or avp may request higher
  97. */
  98. if (rate >= 816000)
  99. clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
  100. else if (rate >= 456000)
  101. clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
  102. else
  103. clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
  104. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  105. #ifdef CONFIG_CPU_FREQ_DEBUG
  106. printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
  107. freqs.old, freqs.new);
  108. #endif
  109. ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
  110. if (ret) {
  111. pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
  112. freqs.new);
  113. freqs.new = freqs.old;
  114. }
  115. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  116. return ret;
  117. }
  118. static unsigned long tegra_cpu_highest_speed(void)
  119. {
  120. unsigned long rate = 0;
  121. int i;
  122. for_each_online_cpu(i)
  123. rate = max(rate, target_cpu_speed[i]);
  124. return rate;
  125. }
  126. static int tegra_target(struct cpufreq_policy *policy,
  127. unsigned int target_freq,
  128. unsigned int relation)
  129. {
  130. unsigned int idx;
  131. unsigned int freq;
  132. int ret = 0;
  133. mutex_lock(&tegra_cpu_lock);
  134. if (is_suspended) {
  135. ret = -EBUSY;
  136. goto out;
  137. }
  138. cpufreq_frequency_table_target(policy, freq_table, target_freq,
  139. relation, &idx);
  140. freq = freq_table[idx].frequency;
  141. target_cpu_speed[policy->cpu] = freq;
  142. ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
  143. out:
  144. mutex_unlock(&tegra_cpu_lock);
  145. return ret;
  146. }
  147. static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
  148. void *dummy)
  149. {
  150. mutex_lock(&tegra_cpu_lock);
  151. if (event == PM_SUSPEND_PREPARE) {
  152. struct cpufreq_policy *policy = cpufreq_cpu_get(0);
  153. is_suspended = true;
  154. pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
  155. freq_table[0].frequency);
  156. tegra_update_cpu_speed(policy, freq_table[0].frequency);
  157. cpufreq_cpu_put(policy);
  158. } else if (event == PM_POST_SUSPEND) {
  159. is_suspended = false;
  160. }
  161. mutex_unlock(&tegra_cpu_lock);
  162. return NOTIFY_OK;
  163. }
  164. static struct notifier_block tegra_cpu_pm_notifier = {
  165. .notifier_call = tegra_pm_notify,
  166. };
  167. static int tegra_cpu_init(struct cpufreq_policy *policy)
  168. {
  169. if (policy->cpu >= NUM_CPUS)
  170. return -EINVAL;
  171. clk_prepare_enable(emc_clk);
  172. clk_prepare_enable(cpu_clk);
  173. cpufreq_table_validate_and_show(policy, freq_table);
  174. policy->cur = tegra_getspeed(policy->cpu);
  175. target_cpu_speed[policy->cpu] = policy->cur;
  176. /* FIXME: what's the actual transition time? */
  177. policy->cpuinfo.transition_latency = 300 * 1000;
  178. cpumask_copy(policy->cpus, cpu_possible_mask);
  179. if (policy->cpu == 0)
  180. register_pm_notifier(&tegra_cpu_pm_notifier);
  181. return 0;
  182. }
  183. static int tegra_cpu_exit(struct cpufreq_policy *policy)
  184. {
  185. cpufreq_frequency_table_put_attr(policy->cpu);
  186. clk_disable_unprepare(emc_clk);
  187. return 0;
  188. }
  189. static struct cpufreq_driver tegra_cpufreq_driver = {
  190. .verify = cpufreq_generic_frequency_table_verify,
  191. .target = tegra_target,
  192. .get = tegra_getspeed,
  193. .init = tegra_cpu_init,
  194. .exit = tegra_cpu_exit,
  195. .name = "tegra",
  196. .attr = cpufreq_generic_attr,
  197. };
  198. static int __init tegra_cpufreq_init(void)
  199. {
  200. cpu_clk = clk_get_sys(NULL, "cclk");
  201. if (IS_ERR(cpu_clk))
  202. return PTR_ERR(cpu_clk);
  203. pll_x_clk = clk_get_sys(NULL, "pll_x");
  204. if (IS_ERR(pll_x_clk))
  205. return PTR_ERR(pll_x_clk);
  206. pll_p_clk = clk_get_sys(NULL, "pll_p");
  207. if (IS_ERR(pll_p_clk))
  208. return PTR_ERR(pll_p_clk);
  209. emc_clk = clk_get_sys("cpu", "emc");
  210. if (IS_ERR(emc_clk)) {
  211. clk_put(cpu_clk);
  212. return PTR_ERR(emc_clk);
  213. }
  214. return cpufreq_register_driver(&tegra_cpufreq_driver);
  215. }
  216. static void __exit tegra_cpufreq_exit(void)
  217. {
  218. cpufreq_unregister_driver(&tegra_cpufreq_driver);
  219. clk_put(emc_clk);
  220. clk_put(cpu_clk);
  221. }
  222. MODULE_AUTHOR("Colin Cross <ccross@android.com>");
  223. MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
  224. MODULE_LICENSE("GPL");
  225. module_init(tegra_cpufreq_init);
  226. module_exit(tegra_cpufreq_exit);