ac97c.c 31 KB

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  1. /*
  2. * Driver for Atmel AC97C
  3. *
  4. * Copyright (C) 2005-2009 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/bitmap.h>
  13. #include <linux/device.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/atmel_pdc.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/mutex.h>
  22. #include <linux/gpio.h>
  23. #include <linux/types.h>
  24. #include <linux/io.h>
  25. #include <sound/core.h>
  26. #include <sound/initval.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/ac97_codec.h>
  30. #include <sound/atmel-ac97c.h>
  31. #include <sound/memalloc.h>
  32. #include <linux/dw_dmac.h>
  33. #include <mach/cpu.h>
  34. #include <mach/gpio.h>
  35. #ifdef CONFIG_ARCH_AT91
  36. #include <mach/hardware.h>
  37. #endif
  38. #include "ac97c.h"
  39. enum {
  40. DMA_TX_READY = 0,
  41. DMA_RX_READY,
  42. DMA_TX_CHAN_PRESENT,
  43. DMA_RX_CHAN_PRESENT,
  44. };
  45. /* Serialize access to opened variable */
  46. static DEFINE_MUTEX(opened_mutex);
  47. struct atmel_ac97c_dma {
  48. struct dma_chan *rx_chan;
  49. struct dma_chan *tx_chan;
  50. };
  51. struct atmel_ac97c {
  52. struct clk *pclk;
  53. struct platform_device *pdev;
  54. struct atmel_ac97c_dma dma;
  55. struct snd_pcm_substream *playback_substream;
  56. struct snd_pcm_substream *capture_substream;
  57. struct snd_card *card;
  58. struct snd_pcm *pcm;
  59. struct snd_ac97 *ac97;
  60. struct snd_ac97_bus *ac97_bus;
  61. u64 cur_format;
  62. unsigned int cur_rate;
  63. unsigned long flags;
  64. int playback_period, capture_period;
  65. /* Serialize access to opened variable */
  66. spinlock_t lock;
  67. void __iomem *regs;
  68. int irq;
  69. int opened;
  70. int reset_pin;
  71. };
  72. #define get_chip(card) ((struct atmel_ac97c *)(card)->private_data)
  73. #define ac97c_writel(chip, reg, val) \
  74. __raw_writel((val), (chip)->regs + AC97C_##reg)
  75. #define ac97c_readl(chip, reg) \
  76. __raw_readl((chip)->regs + AC97C_##reg)
  77. /* This function is called by the DMA driver. */
  78. static void atmel_ac97c_dma_playback_period_done(void *arg)
  79. {
  80. struct atmel_ac97c *chip = arg;
  81. snd_pcm_period_elapsed(chip->playback_substream);
  82. }
  83. static void atmel_ac97c_dma_capture_period_done(void *arg)
  84. {
  85. struct atmel_ac97c *chip = arg;
  86. snd_pcm_period_elapsed(chip->capture_substream);
  87. }
  88. static int atmel_ac97c_prepare_dma(struct atmel_ac97c *chip,
  89. struct snd_pcm_substream *substream,
  90. enum dma_transfer_direction direction)
  91. {
  92. struct dma_chan *chan;
  93. struct dw_cyclic_desc *cdesc;
  94. struct snd_pcm_runtime *runtime = substream->runtime;
  95. unsigned long buffer_len, period_len;
  96. /*
  97. * We don't do DMA on "complex" transfers, i.e. with
  98. * non-halfword-aligned buffers or lengths.
  99. */
  100. if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
  101. dev_dbg(&chip->pdev->dev, "too complex transfer\n");
  102. return -EINVAL;
  103. }
  104. if (direction == DMA_MEM_TO_DEV)
  105. chan = chip->dma.tx_chan;
  106. else
  107. chan = chip->dma.rx_chan;
  108. buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
  109. period_len = frames_to_bytes(runtime, runtime->period_size);
  110. cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
  111. period_len, direction);
  112. if (IS_ERR(cdesc)) {
  113. dev_dbg(&chip->pdev->dev, "could not prepare cyclic DMA\n");
  114. return PTR_ERR(cdesc);
  115. }
  116. if (direction == DMA_MEM_TO_DEV) {
  117. cdesc->period_callback = atmel_ac97c_dma_playback_period_done;
  118. set_bit(DMA_TX_READY, &chip->flags);
  119. } else {
  120. cdesc->period_callback = atmel_ac97c_dma_capture_period_done;
  121. set_bit(DMA_RX_READY, &chip->flags);
  122. }
  123. cdesc->period_callback_param = chip;
  124. return 0;
  125. }
  126. static struct snd_pcm_hardware atmel_ac97c_hw = {
  127. .info = (SNDRV_PCM_INFO_MMAP
  128. | SNDRV_PCM_INFO_MMAP_VALID
  129. | SNDRV_PCM_INFO_INTERLEAVED
  130. | SNDRV_PCM_INFO_BLOCK_TRANSFER
  131. | SNDRV_PCM_INFO_JOINT_DUPLEX
  132. | SNDRV_PCM_INFO_RESUME
  133. | SNDRV_PCM_INFO_PAUSE),
  134. .formats = (SNDRV_PCM_FMTBIT_S16_BE
  135. | SNDRV_PCM_FMTBIT_S16_LE),
  136. .rates = (SNDRV_PCM_RATE_CONTINUOUS),
  137. .rate_min = 4000,
  138. .rate_max = 48000,
  139. .channels_min = 1,
  140. .channels_max = 2,
  141. .buffer_bytes_max = 2 * 2 * 64 * 2048,
  142. .period_bytes_min = 4096,
  143. .period_bytes_max = 4096,
  144. .periods_min = 6,
  145. .periods_max = 64,
  146. };
  147. static int atmel_ac97c_playback_open(struct snd_pcm_substream *substream)
  148. {
  149. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  150. struct snd_pcm_runtime *runtime = substream->runtime;
  151. mutex_lock(&opened_mutex);
  152. chip->opened++;
  153. runtime->hw = atmel_ac97c_hw;
  154. if (chip->cur_rate) {
  155. runtime->hw.rate_min = chip->cur_rate;
  156. runtime->hw.rate_max = chip->cur_rate;
  157. }
  158. if (chip->cur_format)
  159. runtime->hw.formats = (1ULL << chip->cur_format);
  160. mutex_unlock(&opened_mutex);
  161. chip->playback_substream = substream;
  162. return 0;
  163. }
  164. static int atmel_ac97c_capture_open(struct snd_pcm_substream *substream)
  165. {
  166. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  167. struct snd_pcm_runtime *runtime = substream->runtime;
  168. mutex_lock(&opened_mutex);
  169. chip->opened++;
  170. runtime->hw = atmel_ac97c_hw;
  171. if (chip->cur_rate) {
  172. runtime->hw.rate_min = chip->cur_rate;
  173. runtime->hw.rate_max = chip->cur_rate;
  174. }
  175. if (chip->cur_format)
  176. runtime->hw.formats = (1ULL << chip->cur_format);
  177. mutex_unlock(&opened_mutex);
  178. chip->capture_substream = substream;
  179. return 0;
  180. }
  181. static int atmel_ac97c_playback_close(struct snd_pcm_substream *substream)
  182. {
  183. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  184. mutex_lock(&opened_mutex);
  185. chip->opened--;
  186. if (!chip->opened) {
  187. chip->cur_rate = 0;
  188. chip->cur_format = 0;
  189. }
  190. mutex_unlock(&opened_mutex);
  191. chip->playback_substream = NULL;
  192. return 0;
  193. }
  194. static int atmel_ac97c_capture_close(struct snd_pcm_substream *substream)
  195. {
  196. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  197. mutex_lock(&opened_mutex);
  198. chip->opened--;
  199. if (!chip->opened) {
  200. chip->cur_rate = 0;
  201. chip->cur_format = 0;
  202. }
  203. mutex_unlock(&opened_mutex);
  204. chip->capture_substream = NULL;
  205. return 0;
  206. }
  207. static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream,
  208. struct snd_pcm_hw_params *hw_params)
  209. {
  210. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  211. int retval;
  212. retval = snd_pcm_lib_malloc_pages(substream,
  213. params_buffer_bytes(hw_params));
  214. if (retval < 0)
  215. return retval;
  216. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  217. if (cpu_is_at32ap7000()) {
  218. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  219. if (retval == 1)
  220. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  221. dw_dma_cyclic_free(chip->dma.tx_chan);
  222. }
  223. /* Set restrictions to params. */
  224. mutex_lock(&opened_mutex);
  225. chip->cur_rate = params_rate(hw_params);
  226. chip->cur_format = params_format(hw_params);
  227. mutex_unlock(&opened_mutex);
  228. return retval;
  229. }
  230. static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *hw_params)
  232. {
  233. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  234. int retval;
  235. retval = snd_pcm_lib_malloc_pages(substream,
  236. params_buffer_bytes(hw_params));
  237. if (retval < 0)
  238. return retval;
  239. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  240. if (cpu_is_at32ap7000() && retval == 1)
  241. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  242. dw_dma_cyclic_free(chip->dma.rx_chan);
  243. /* Set restrictions to params. */
  244. mutex_lock(&opened_mutex);
  245. chip->cur_rate = params_rate(hw_params);
  246. chip->cur_format = params_format(hw_params);
  247. mutex_unlock(&opened_mutex);
  248. return retval;
  249. }
  250. static int atmel_ac97c_playback_hw_free(struct snd_pcm_substream *substream)
  251. {
  252. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  253. if (cpu_is_at32ap7000()) {
  254. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  255. dw_dma_cyclic_free(chip->dma.tx_chan);
  256. }
  257. return snd_pcm_lib_free_pages(substream);
  258. }
  259. static int atmel_ac97c_capture_hw_free(struct snd_pcm_substream *substream)
  260. {
  261. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  262. if (cpu_is_at32ap7000()) {
  263. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  264. dw_dma_cyclic_free(chip->dma.rx_chan);
  265. }
  266. return snd_pcm_lib_free_pages(substream);
  267. }
  268. static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
  269. {
  270. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  271. struct snd_pcm_runtime *runtime = substream->runtime;
  272. int block_size = frames_to_bytes(runtime, runtime->period_size);
  273. unsigned long word = ac97c_readl(chip, OCA);
  274. int retval;
  275. chip->playback_period = 0;
  276. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  277. /* assign channels to AC97C channel A */
  278. switch (runtime->channels) {
  279. case 1:
  280. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  281. break;
  282. case 2:
  283. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  284. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  285. break;
  286. default:
  287. /* TODO: support more than two channels */
  288. return -EINVAL;
  289. }
  290. ac97c_writel(chip, OCA, word);
  291. /* configure sample format and size */
  292. word = ac97c_readl(chip, CAMR);
  293. if (chip->opened <= 1)
  294. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  295. else
  296. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  297. switch (runtime->format) {
  298. case SNDRV_PCM_FORMAT_S16_LE:
  299. if (cpu_is_at32ap7000())
  300. word |= AC97C_CMR_CEM_LITTLE;
  301. break;
  302. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  303. word &= ~(AC97C_CMR_CEM_LITTLE);
  304. break;
  305. default:
  306. word = ac97c_readl(chip, OCA);
  307. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  308. ac97c_writel(chip, OCA, word);
  309. return -EINVAL;
  310. }
  311. /* Enable underrun interrupt on channel A */
  312. word |= AC97C_CSR_UNRUN;
  313. ac97c_writel(chip, CAMR, word);
  314. /* Enable channel A event interrupt */
  315. word = ac97c_readl(chip, IMR);
  316. word |= AC97C_SR_CAEVT;
  317. ac97c_writel(chip, IER, word);
  318. /* set variable rate if needed */
  319. if (runtime->rate != 48000) {
  320. word = ac97c_readl(chip, MR);
  321. word |= AC97C_MR_VRA;
  322. ac97c_writel(chip, MR, word);
  323. } else {
  324. word = ac97c_readl(chip, MR);
  325. word &= ~(AC97C_MR_VRA);
  326. ac97c_writel(chip, MR, word);
  327. }
  328. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
  329. runtime->rate);
  330. if (retval)
  331. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  332. runtime->rate);
  333. if (cpu_is_at32ap7000()) {
  334. if (!test_bit(DMA_TX_READY, &chip->flags))
  335. retval = atmel_ac97c_prepare_dma(chip, substream,
  336. DMA_MEM_TO_DEV);
  337. } else {
  338. /* Initialize and start the PDC */
  339. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
  340. writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
  341. writel(runtime->dma_addr + block_size,
  342. chip->regs + ATMEL_PDC_TNPR);
  343. writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
  344. }
  345. return retval;
  346. }
  347. static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
  348. {
  349. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  350. struct snd_pcm_runtime *runtime = substream->runtime;
  351. int block_size = frames_to_bytes(runtime, runtime->period_size);
  352. unsigned long word = ac97c_readl(chip, ICA);
  353. int retval;
  354. chip->capture_period = 0;
  355. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  356. /* assign channels to AC97C channel A */
  357. switch (runtime->channels) {
  358. case 1:
  359. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  360. break;
  361. case 2:
  362. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  363. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  364. break;
  365. default:
  366. /* TODO: support more than two channels */
  367. return -EINVAL;
  368. }
  369. ac97c_writel(chip, ICA, word);
  370. /* configure sample format and size */
  371. word = ac97c_readl(chip, CAMR);
  372. if (chip->opened <= 1)
  373. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  374. else
  375. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  376. switch (runtime->format) {
  377. case SNDRV_PCM_FORMAT_S16_LE:
  378. if (cpu_is_at32ap7000())
  379. word |= AC97C_CMR_CEM_LITTLE;
  380. break;
  381. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  382. word &= ~(AC97C_CMR_CEM_LITTLE);
  383. break;
  384. default:
  385. word = ac97c_readl(chip, ICA);
  386. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  387. ac97c_writel(chip, ICA, word);
  388. return -EINVAL;
  389. }
  390. /* Enable overrun interrupt on channel A */
  391. word |= AC97C_CSR_OVRUN;
  392. ac97c_writel(chip, CAMR, word);
  393. /* Enable channel A event interrupt */
  394. word = ac97c_readl(chip, IMR);
  395. word |= AC97C_SR_CAEVT;
  396. ac97c_writel(chip, IER, word);
  397. /* set variable rate if needed */
  398. if (runtime->rate != 48000) {
  399. word = ac97c_readl(chip, MR);
  400. word |= AC97C_MR_VRA;
  401. ac97c_writel(chip, MR, word);
  402. } else {
  403. word = ac97c_readl(chip, MR);
  404. word &= ~(AC97C_MR_VRA);
  405. ac97c_writel(chip, MR, word);
  406. }
  407. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE,
  408. runtime->rate);
  409. if (retval)
  410. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  411. runtime->rate);
  412. if (cpu_is_at32ap7000()) {
  413. if (!test_bit(DMA_RX_READY, &chip->flags))
  414. retval = atmel_ac97c_prepare_dma(chip, substream,
  415. DMA_DEV_TO_MEM);
  416. } else {
  417. /* Initialize and start the PDC */
  418. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
  419. writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
  420. writel(runtime->dma_addr + block_size,
  421. chip->regs + ATMEL_PDC_RNPR);
  422. writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
  423. }
  424. return retval;
  425. }
  426. static int
  427. atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  428. {
  429. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  430. unsigned long camr, ptcr = 0;
  431. int retval = 0;
  432. camr = ac97c_readl(chip, CAMR);
  433. switch (cmd) {
  434. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  435. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  436. case SNDRV_PCM_TRIGGER_START:
  437. if (cpu_is_at32ap7000()) {
  438. retval = dw_dma_cyclic_start(chip->dma.tx_chan);
  439. if (retval)
  440. goto out;
  441. } else {
  442. ptcr = ATMEL_PDC_TXTEN;
  443. }
  444. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX;
  445. break;
  446. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  447. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  448. case SNDRV_PCM_TRIGGER_STOP:
  449. if (cpu_is_at32ap7000())
  450. dw_dma_cyclic_stop(chip->dma.tx_chan);
  451. else
  452. ptcr |= ATMEL_PDC_TXTDIS;
  453. if (chip->opened <= 1)
  454. camr &= ~AC97C_CMR_CENA;
  455. break;
  456. default:
  457. retval = -EINVAL;
  458. goto out;
  459. }
  460. ac97c_writel(chip, CAMR, camr);
  461. if (!cpu_is_at32ap7000())
  462. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  463. out:
  464. return retval;
  465. }
  466. static int
  467. atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  468. {
  469. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  470. unsigned long camr, ptcr = 0;
  471. int retval = 0;
  472. camr = ac97c_readl(chip, CAMR);
  473. ptcr = readl(chip->regs + ATMEL_PDC_PTSR);
  474. switch (cmd) {
  475. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  476. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  477. case SNDRV_PCM_TRIGGER_START:
  478. if (cpu_is_at32ap7000()) {
  479. retval = dw_dma_cyclic_start(chip->dma.rx_chan);
  480. if (retval)
  481. goto out;
  482. } else {
  483. ptcr = ATMEL_PDC_RXTEN;
  484. }
  485. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX;
  486. break;
  487. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  488. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  489. case SNDRV_PCM_TRIGGER_STOP:
  490. if (cpu_is_at32ap7000())
  491. dw_dma_cyclic_stop(chip->dma.rx_chan);
  492. else
  493. ptcr |= (ATMEL_PDC_RXTDIS);
  494. if (chip->opened <= 1)
  495. camr &= ~AC97C_CMR_CENA;
  496. break;
  497. default:
  498. retval = -EINVAL;
  499. break;
  500. }
  501. ac97c_writel(chip, CAMR, camr);
  502. if (!cpu_is_at32ap7000())
  503. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  504. out:
  505. return retval;
  506. }
  507. static snd_pcm_uframes_t
  508. atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream)
  509. {
  510. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  511. struct snd_pcm_runtime *runtime = substream->runtime;
  512. snd_pcm_uframes_t frames;
  513. unsigned long bytes;
  514. if (cpu_is_at32ap7000())
  515. bytes = dw_dma_get_src_addr(chip->dma.tx_chan);
  516. else
  517. bytes = readl(chip->regs + ATMEL_PDC_TPR);
  518. bytes -= runtime->dma_addr;
  519. frames = bytes_to_frames(runtime, bytes);
  520. if (frames >= runtime->buffer_size)
  521. frames -= runtime->buffer_size;
  522. return frames;
  523. }
  524. static snd_pcm_uframes_t
  525. atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream)
  526. {
  527. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  528. struct snd_pcm_runtime *runtime = substream->runtime;
  529. snd_pcm_uframes_t frames;
  530. unsigned long bytes;
  531. if (cpu_is_at32ap7000())
  532. bytes = dw_dma_get_dst_addr(chip->dma.rx_chan);
  533. else
  534. bytes = readl(chip->regs + ATMEL_PDC_RPR);
  535. bytes -= runtime->dma_addr;
  536. frames = bytes_to_frames(runtime, bytes);
  537. if (frames >= runtime->buffer_size)
  538. frames -= runtime->buffer_size;
  539. return frames;
  540. }
  541. static struct snd_pcm_ops atmel_ac97_playback_ops = {
  542. .open = atmel_ac97c_playback_open,
  543. .close = atmel_ac97c_playback_close,
  544. .ioctl = snd_pcm_lib_ioctl,
  545. .hw_params = atmel_ac97c_playback_hw_params,
  546. .hw_free = atmel_ac97c_playback_hw_free,
  547. .prepare = atmel_ac97c_playback_prepare,
  548. .trigger = atmel_ac97c_playback_trigger,
  549. .pointer = atmel_ac97c_playback_pointer,
  550. };
  551. static struct snd_pcm_ops atmel_ac97_capture_ops = {
  552. .open = atmel_ac97c_capture_open,
  553. .close = atmel_ac97c_capture_close,
  554. .ioctl = snd_pcm_lib_ioctl,
  555. .hw_params = atmel_ac97c_capture_hw_params,
  556. .hw_free = atmel_ac97c_capture_hw_free,
  557. .prepare = atmel_ac97c_capture_prepare,
  558. .trigger = atmel_ac97c_capture_trigger,
  559. .pointer = atmel_ac97c_capture_pointer,
  560. };
  561. static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev)
  562. {
  563. struct atmel_ac97c *chip = (struct atmel_ac97c *)dev;
  564. irqreturn_t retval = IRQ_NONE;
  565. u32 sr = ac97c_readl(chip, SR);
  566. u32 casr = ac97c_readl(chip, CASR);
  567. u32 cosr = ac97c_readl(chip, COSR);
  568. u32 camr = ac97c_readl(chip, CAMR);
  569. if (sr & AC97C_SR_CAEVT) {
  570. struct snd_pcm_runtime *runtime;
  571. int offset, next_period, block_size;
  572. dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
  573. casr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  574. casr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  575. casr & AC97C_CSR_UNRUN ? " UNRUN" : "",
  576. casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  577. casr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  578. !casr ? " NONE" : "");
  579. if (!cpu_is_at32ap7000()) {
  580. if ((casr & camr) & AC97C_CSR_ENDTX) {
  581. runtime = chip->playback_substream->runtime;
  582. block_size = frames_to_bytes(runtime,
  583. runtime->period_size);
  584. chip->playback_period++;
  585. if (chip->playback_period == runtime->periods)
  586. chip->playback_period = 0;
  587. next_period = chip->playback_period + 1;
  588. if (next_period == runtime->periods)
  589. next_period = 0;
  590. offset = block_size * next_period;
  591. writel(runtime->dma_addr + offset,
  592. chip->regs + ATMEL_PDC_TNPR);
  593. writel(block_size / 2,
  594. chip->regs + ATMEL_PDC_TNCR);
  595. snd_pcm_period_elapsed(
  596. chip->playback_substream);
  597. }
  598. if ((casr & camr) & AC97C_CSR_ENDRX) {
  599. runtime = chip->capture_substream->runtime;
  600. block_size = frames_to_bytes(runtime,
  601. runtime->period_size);
  602. chip->capture_period++;
  603. if (chip->capture_period == runtime->periods)
  604. chip->capture_period = 0;
  605. next_period = chip->capture_period + 1;
  606. if (next_period == runtime->periods)
  607. next_period = 0;
  608. offset = block_size * next_period;
  609. writel(runtime->dma_addr + offset,
  610. chip->regs + ATMEL_PDC_RNPR);
  611. writel(block_size / 2,
  612. chip->regs + ATMEL_PDC_RNCR);
  613. snd_pcm_period_elapsed(chip->capture_substream);
  614. }
  615. }
  616. retval = IRQ_HANDLED;
  617. }
  618. if (sr & AC97C_SR_COEVT) {
  619. dev_info(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n",
  620. cosr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  621. cosr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  622. cosr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  623. cosr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  624. !cosr ? " NONE" : "");
  625. retval = IRQ_HANDLED;
  626. }
  627. if (retval == IRQ_NONE) {
  628. dev_err(&chip->pdev->dev, "spurious interrupt sr 0x%08x "
  629. "casr 0x%08x cosr 0x%08x\n", sr, casr, cosr);
  630. }
  631. return retval;
  632. }
  633. static struct ac97_pcm at91_ac97_pcm_defs[] = {
  634. /* Playback */
  635. {
  636. .exclusive = 1,
  637. .r = { {
  638. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  639. | (1 << AC97_SLOT_PCM_RIGHT)),
  640. } },
  641. },
  642. /* PCM in */
  643. {
  644. .stream = 1,
  645. .exclusive = 1,
  646. .r = { {
  647. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  648. | (1 << AC97_SLOT_PCM_RIGHT)),
  649. } }
  650. },
  651. /* Mic in */
  652. {
  653. .stream = 1,
  654. .exclusive = 1,
  655. .r = { {
  656. .slots = (1<<AC97_SLOT_MIC),
  657. } }
  658. },
  659. };
  660. static int atmel_ac97c_pcm_new(struct atmel_ac97c *chip)
  661. {
  662. struct snd_pcm *pcm;
  663. struct snd_pcm_hardware hw = atmel_ac97c_hw;
  664. int capture, playback, retval, err;
  665. capture = test_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  666. playback = test_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  667. if (!cpu_is_at32ap7000()) {
  668. err = snd_ac97_pcm_assign(chip->ac97_bus,
  669. ARRAY_SIZE(at91_ac97_pcm_defs),
  670. at91_ac97_pcm_defs);
  671. if (err)
  672. return err;
  673. }
  674. retval = snd_pcm_new(chip->card, chip->card->shortname,
  675. chip->pdev->id, playback, capture, &pcm);
  676. if (retval)
  677. return retval;
  678. if (capture)
  679. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  680. &atmel_ac97_capture_ops);
  681. if (playback)
  682. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  683. &atmel_ac97_playback_ops);
  684. retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  685. &chip->pdev->dev, hw.periods_min * hw.period_bytes_min,
  686. hw.buffer_bytes_max);
  687. if (retval)
  688. return retval;
  689. pcm->private_data = chip;
  690. pcm->info_flags = 0;
  691. strcpy(pcm->name, chip->card->shortname);
  692. chip->pcm = pcm;
  693. return 0;
  694. }
  695. static int atmel_ac97c_mixer_new(struct atmel_ac97c *chip)
  696. {
  697. struct snd_ac97_template template;
  698. memset(&template, 0, sizeof(template));
  699. template.private_data = chip;
  700. return snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
  701. }
  702. static void atmel_ac97c_write(struct snd_ac97 *ac97, unsigned short reg,
  703. unsigned short val)
  704. {
  705. struct atmel_ac97c *chip = get_chip(ac97);
  706. unsigned long word;
  707. int timeout = 40;
  708. word = (reg & 0x7f) << 16 | val;
  709. do {
  710. if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
  711. ac97c_writel(chip, COTHR, word);
  712. return;
  713. }
  714. udelay(1);
  715. } while (--timeout);
  716. dev_dbg(&chip->pdev->dev, "codec write timeout\n");
  717. }
  718. static unsigned short atmel_ac97c_read(struct snd_ac97 *ac97,
  719. unsigned short reg)
  720. {
  721. struct atmel_ac97c *chip = get_chip(ac97);
  722. unsigned long word;
  723. int timeout = 40;
  724. int write = 10;
  725. word = (0x80 | (reg & 0x7f)) << 16;
  726. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
  727. ac97c_readl(chip, CORHR);
  728. retry_write:
  729. timeout = 40;
  730. do {
  731. if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
  732. ac97c_writel(chip, COTHR, word);
  733. goto read_reg;
  734. }
  735. udelay(10);
  736. } while (--timeout);
  737. if (!--write)
  738. goto timed_out;
  739. goto retry_write;
  740. read_reg:
  741. do {
  742. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
  743. unsigned short val = ac97c_readl(chip, CORHR);
  744. return val;
  745. }
  746. udelay(10);
  747. } while (--timeout);
  748. if (!--write)
  749. goto timed_out;
  750. goto retry_write;
  751. timed_out:
  752. dev_dbg(&chip->pdev->dev, "codec read timeout\n");
  753. return 0xffff;
  754. }
  755. static bool filter(struct dma_chan *chan, void *slave)
  756. {
  757. struct dw_dma_slave *dws = slave;
  758. if (dws->dma_dev == chan->device->dev) {
  759. chan->private = dws;
  760. return true;
  761. } else
  762. return false;
  763. }
  764. static void atmel_ac97c_reset(struct atmel_ac97c *chip)
  765. {
  766. ac97c_writel(chip, MR, 0);
  767. ac97c_writel(chip, MR, AC97C_MR_ENA);
  768. ac97c_writel(chip, CAMR, 0);
  769. ac97c_writel(chip, COMR, 0);
  770. if (gpio_is_valid(chip->reset_pin)) {
  771. gpio_set_value(chip->reset_pin, 0);
  772. /* AC97 v2.2 specifications says minimum 1 us. */
  773. udelay(2);
  774. gpio_set_value(chip->reset_pin, 1);
  775. } else {
  776. ac97c_writel(chip, MR, AC97C_MR_WRST | AC97C_MR_ENA);
  777. udelay(2);
  778. ac97c_writel(chip, MR, AC97C_MR_ENA);
  779. }
  780. }
  781. static int atmel_ac97c_probe(struct platform_device *pdev)
  782. {
  783. struct snd_card *card;
  784. struct atmel_ac97c *chip;
  785. struct resource *regs;
  786. struct ac97c_platform_data *pdata;
  787. struct clk *pclk;
  788. static struct snd_ac97_bus_ops ops = {
  789. .write = atmel_ac97c_write,
  790. .read = atmel_ac97c_read,
  791. };
  792. int retval;
  793. int irq;
  794. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  795. if (!regs) {
  796. dev_dbg(&pdev->dev, "no memory resource\n");
  797. return -ENXIO;
  798. }
  799. pdata = pdev->dev.platform_data;
  800. if (!pdata) {
  801. dev_dbg(&pdev->dev, "no platform data\n");
  802. return -ENXIO;
  803. }
  804. irq = platform_get_irq(pdev, 0);
  805. if (irq < 0) {
  806. dev_dbg(&pdev->dev, "could not get irq\n");
  807. return -ENXIO;
  808. }
  809. if (cpu_is_at32ap7000()) {
  810. pclk = clk_get(&pdev->dev, "pclk");
  811. } else {
  812. pclk = clk_get(&pdev->dev, "ac97_clk");
  813. }
  814. if (IS_ERR(pclk)) {
  815. dev_dbg(&pdev->dev, "no peripheral clock\n");
  816. return PTR_ERR(pclk);
  817. }
  818. clk_enable(pclk);
  819. retval = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  820. THIS_MODULE, sizeof(struct atmel_ac97c), &card);
  821. if (retval) {
  822. dev_dbg(&pdev->dev, "could not create sound card device\n");
  823. goto err_snd_card_new;
  824. }
  825. chip = get_chip(card);
  826. retval = request_irq(irq, atmel_ac97c_interrupt, 0, "AC97C", chip);
  827. if (retval) {
  828. dev_dbg(&pdev->dev, "unable to request irq %d\n", irq);
  829. goto err_request_irq;
  830. }
  831. chip->irq = irq;
  832. spin_lock_init(&chip->lock);
  833. strcpy(card->driver, "Atmel AC97C");
  834. strcpy(card->shortname, "Atmel AC97C");
  835. sprintf(card->longname, "Atmel AC97 controller");
  836. chip->card = card;
  837. chip->pclk = pclk;
  838. chip->pdev = pdev;
  839. chip->regs = ioremap(regs->start, resource_size(regs));
  840. if (!chip->regs) {
  841. dev_dbg(&pdev->dev, "could not remap register memory\n");
  842. retval = -ENOMEM;
  843. goto err_ioremap;
  844. }
  845. if (gpio_is_valid(pdata->reset_pin)) {
  846. if (gpio_request(pdata->reset_pin, "reset_pin")) {
  847. dev_dbg(&pdev->dev, "reset pin not available\n");
  848. chip->reset_pin = -ENODEV;
  849. } else {
  850. gpio_direction_output(pdata->reset_pin, 1);
  851. chip->reset_pin = pdata->reset_pin;
  852. }
  853. } else {
  854. chip->reset_pin = -EINVAL;
  855. }
  856. snd_card_set_dev(card, &pdev->dev);
  857. atmel_ac97c_reset(chip);
  858. /* Enable overrun interrupt from codec channel */
  859. ac97c_writel(chip, COMR, AC97C_CSR_OVRUN);
  860. ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
  861. retval = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
  862. if (retval) {
  863. dev_dbg(&pdev->dev, "could not register on ac97 bus\n");
  864. goto err_ac97_bus;
  865. }
  866. retval = atmel_ac97c_mixer_new(chip);
  867. if (retval) {
  868. dev_dbg(&pdev->dev, "could not register ac97 mixer\n");
  869. goto err_ac97_bus;
  870. }
  871. if (cpu_is_at32ap7000()) {
  872. if (pdata->rx_dws.dma_dev) {
  873. dma_cap_mask_t mask;
  874. dma_cap_zero(mask);
  875. dma_cap_set(DMA_SLAVE, mask);
  876. chip->dma.rx_chan = dma_request_channel(mask, filter,
  877. &pdata->rx_dws);
  878. if (chip->dma.rx_chan) {
  879. struct dma_slave_config dma_conf = {
  880. .src_addr = regs->start + AC97C_CARHR +
  881. 2,
  882. .src_addr_width =
  883. DMA_SLAVE_BUSWIDTH_2_BYTES,
  884. .src_maxburst = 1,
  885. .dst_maxburst = 1,
  886. .direction = DMA_DEV_TO_MEM,
  887. .device_fc = false,
  888. };
  889. dmaengine_slave_config(chip->dma.rx_chan,
  890. &dma_conf);
  891. }
  892. dev_info(&chip->pdev->dev, "using %s for DMA RX\n",
  893. dev_name(&chip->dma.rx_chan->dev->device));
  894. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  895. }
  896. if (pdata->tx_dws.dma_dev) {
  897. dma_cap_mask_t mask;
  898. dma_cap_zero(mask);
  899. dma_cap_set(DMA_SLAVE, mask);
  900. chip->dma.tx_chan = dma_request_channel(mask, filter,
  901. &pdata->tx_dws);
  902. if (chip->dma.tx_chan) {
  903. struct dma_slave_config dma_conf = {
  904. .dst_addr = regs->start + AC97C_CATHR +
  905. 2,
  906. .dst_addr_width =
  907. DMA_SLAVE_BUSWIDTH_2_BYTES,
  908. .src_maxburst = 1,
  909. .dst_maxburst = 1,
  910. .direction = DMA_MEM_TO_DEV,
  911. .device_fc = false,
  912. };
  913. dmaengine_slave_config(chip->dma.tx_chan,
  914. &dma_conf);
  915. }
  916. dev_info(&chip->pdev->dev, "using %s for DMA TX\n",
  917. dev_name(&chip->dma.tx_chan->dev->device));
  918. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  919. }
  920. if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) &&
  921. !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) {
  922. dev_dbg(&pdev->dev, "DMA not available\n");
  923. retval = -ENODEV;
  924. goto err_dma;
  925. }
  926. } else {
  927. /* Just pretend that we have DMA channel(for at91 i is actually
  928. * the PDC) */
  929. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  930. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  931. }
  932. retval = atmel_ac97c_pcm_new(chip);
  933. if (retval) {
  934. dev_dbg(&pdev->dev, "could not register ac97 pcm device\n");
  935. goto err_dma;
  936. }
  937. retval = snd_card_register(card);
  938. if (retval) {
  939. dev_dbg(&pdev->dev, "could not register sound card\n");
  940. goto err_dma;
  941. }
  942. platform_set_drvdata(pdev, card);
  943. dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p, irq = %d\n",
  944. chip->regs, irq);
  945. return 0;
  946. err_dma:
  947. if (cpu_is_at32ap7000()) {
  948. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  949. dma_release_channel(chip->dma.rx_chan);
  950. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  951. dma_release_channel(chip->dma.tx_chan);
  952. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  953. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  954. chip->dma.rx_chan = NULL;
  955. chip->dma.tx_chan = NULL;
  956. }
  957. err_ac97_bus:
  958. snd_card_set_dev(card, NULL);
  959. if (gpio_is_valid(chip->reset_pin))
  960. gpio_free(chip->reset_pin);
  961. iounmap(chip->regs);
  962. err_ioremap:
  963. free_irq(irq, chip);
  964. err_request_irq:
  965. snd_card_free(card);
  966. err_snd_card_new:
  967. clk_disable(pclk);
  968. clk_put(pclk);
  969. return retval;
  970. }
  971. #ifdef CONFIG_PM_SLEEP
  972. static int atmel_ac97c_suspend(struct device *pdev)
  973. {
  974. struct snd_card *card = dev_get_drvdata(pdev);
  975. struct atmel_ac97c *chip = card->private_data;
  976. if (cpu_is_at32ap7000()) {
  977. if (test_bit(DMA_RX_READY, &chip->flags))
  978. dw_dma_cyclic_stop(chip->dma.rx_chan);
  979. if (test_bit(DMA_TX_READY, &chip->flags))
  980. dw_dma_cyclic_stop(chip->dma.tx_chan);
  981. }
  982. clk_disable(chip->pclk);
  983. return 0;
  984. }
  985. static int atmel_ac97c_resume(struct device *pdev)
  986. {
  987. struct snd_card *card = dev_get_drvdata(pdev);
  988. struct atmel_ac97c *chip = card->private_data;
  989. clk_enable(chip->pclk);
  990. if (cpu_is_at32ap7000()) {
  991. if (test_bit(DMA_RX_READY, &chip->flags))
  992. dw_dma_cyclic_start(chip->dma.rx_chan);
  993. if (test_bit(DMA_TX_READY, &chip->flags))
  994. dw_dma_cyclic_start(chip->dma.tx_chan);
  995. }
  996. return 0;
  997. }
  998. static SIMPLE_DEV_PM_OPS(atmel_ac97c_pm, atmel_ac97c_suspend, atmel_ac97c_resume);
  999. #define ATMEL_AC97C_PM_OPS &atmel_ac97c_pm
  1000. #else
  1001. #define ATMEL_AC97C_PM_OPS NULL
  1002. #endif
  1003. static int atmel_ac97c_remove(struct platform_device *pdev)
  1004. {
  1005. struct snd_card *card = platform_get_drvdata(pdev);
  1006. struct atmel_ac97c *chip = get_chip(card);
  1007. if (gpio_is_valid(chip->reset_pin))
  1008. gpio_free(chip->reset_pin);
  1009. ac97c_writel(chip, CAMR, 0);
  1010. ac97c_writel(chip, COMR, 0);
  1011. ac97c_writel(chip, MR, 0);
  1012. clk_disable(chip->pclk);
  1013. clk_put(chip->pclk);
  1014. iounmap(chip->regs);
  1015. free_irq(chip->irq, chip);
  1016. if (cpu_is_at32ap7000()) {
  1017. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  1018. dma_release_channel(chip->dma.rx_chan);
  1019. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  1020. dma_release_channel(chip->dma.tx_chan);
  1021. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  1022. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  1023. chip->dma.rx_chan = NULL;
  1024. chip->dma.tx_chan = NULL;
  1025. }
  1026. snd_card_set_dev(card, NULL);
  1027. snd_card_free(card);
  1028. platform_set_drvdata(pdev, NULL);
  1029. return 0;
  1030. }
  1031. static struct platform_driver atmel_ac97c_driver = {
  1032. .remove = atmel_ac97c_remove,
  1033. .driver = {
  1034. .name = "atmel_ac97c",
  1035. .owner = THIS_MODULE,
  1036. .pm = ATMEL_AC97C_PM_OPS,
  1037. },
  1038. };
  1039. static int __init atmel_ac97c_init(void)
  1040. {
  1041. return platform_driver_probe(&atmel_ac97c_driver,
  1042. atmel_ac97c_probe);
  1043. }
  1044. module_init(atmel_ac97c_init);
  1045. static void __exit atmel_ac97c_exit(void)
  1046. {
  1047. platform_driver_unregister(&atmel_ac97c_driver);
  1048. }
  1049. module_exit(atmel_ac97c_exit);
  1050. MODULE_LICENSE("GPL");
  1051. MODULE_DESCRIPTION("Driver for Atmel AC97 controller");
  1052. MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");