max310x.c 36 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264
  1. /*
  2. * Maxim (Dallas) MAX3107/8 serial driver
  3. *
  4. * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
  5. *
  6. * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
  7. * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
  8. * Based on max3107.c, by Aavamobile
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. /* TODO: MAX3109 support (Dual) */
  16. /* TODO: MAX14830 support (Quad) */
  17. #include <linux/module.h>
  18. #include <linux/device.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/serial.h>
  21. #include <linux/tty.h>
  22. #include <linux/tty_flip.h>
  23. #include <linux/regmap.h>
  24. #include <linux/gpio.h>
  25. #include <linux/spi/spi.h>
  26. #include <linux/platform_data/max310x.h>
  27. #define MAX310X_MAJOR 204
  28. #define MAX310X_MINOR 209
  29. /* MAX310X register definitions */
  30. #define MAX310X_RHR_REG (0x00) /* RX FIFO */
  31. #define MAX310X_THR_REG (0x00) /* TX FIFO */
  32. #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
  33. #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
  34. #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
  35. #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
  36. #define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */
  37. #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
  38. #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
  39. #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
  40. #define MAX310X_MODE1_REG (0x09) /* MODE1 */
  41. #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
  42. #define MAX310X_LCR_REG (0x0b) /* LCR */
  43. #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
  44. #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
  45. #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
  46. #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
  47. #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
  48. #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
  49. #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
  50. #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
  51. #define MAX310X_XON1_REG (0x14) /* XON1 character */
  52. #define MAX310X_XON2_REG (0x15) /* XON2 character */
  53. #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
  54. #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
  55. #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
  56. #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
  57. #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
  58. #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
  59. #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
  60. #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
  61. #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
  62. /* Only present in MAX3107 */
  63. #define MAX3107_REVID_REG (0x1f) /* Revision identification */
  64. /* IRQ register bits */
  65. #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
  66. #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
  67. #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
  68. #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
  69. #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
  70. #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
  71. #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
  72. #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
  73. /* LSR register bits */
  74. #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
  75. #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
  76. #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
  77. #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
  78. #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
  79. #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
  80. #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
  81. /* Special character register bits */
  82. #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
  83. #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
  84. #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
  85. #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
  86. #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
  87. #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
  88. /* Status register bits */
  89. #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
  90. #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
  91. #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
  92. #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
  93. #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
  94. #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
  95. /* MODE1 register bits */
  96. #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
  97. #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
  98. #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
  99. #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
  100. #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
  101. #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
  102. #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
  103. #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
  104. /* MODE2 register bits */
  105. #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
  106. #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
  107. #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
  108. #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
  109. #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
  110. #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
  111. #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
  112. #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
  113. /* LCR register bits */
  114. #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
  115. #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
  116. *
  117. * Word length bits table:
  118. * 00 -> 5 bit words
  119. * 01 -> 6 bit words
  120. * 10 -> 7 bit words
  121. * 11 -> 8 bit words
  122. */
  123. #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
  124. *
  125. * STOP length bit table:
  126. * 0 -> 1 stop bit
  127. * 1 -> 1-1.5 stop bits if
  128. * word length is 5,
  129. * 2 stop bits otherwise
  130. */
  131. #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
  132. #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
  133. #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
  134. #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
  135. #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
  136. #define MAX310X_LCR_WORD_LEN_5 (0x00)
  137. #define MAX310X_LCR_WORD_LEN_6 (0x01)
  138. #define MAX310X_LCR_WORD_LEN_7 (0x02)
  139. #define MAX310X_LCR_WORD_LEN_8 (0x03)
  140. /* IRDA register bits */
  141. #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
  142. #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
  143. #define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
  144. #define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
  145. #define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
  146. #define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
  147. /* Flow control trigger level register masks */
  148. #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
  149. #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
  150. #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
  151. #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
  152. /* FIFO interrupt trigger level register masks */
  153. #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
  154. #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
  155. #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
  156. #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
  157. /* Flow control register bits */
  158. #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
  159. #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
  160. #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
  161. * are used in conjunction with
  162. * XOFF2 for definition of
  163. * special character */
  164. #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
  165. #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
  166. #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
  167. *
  168. * SWFLOW bits 1 & 0 table:
  169. * 00 -> no transmitter flow
  170. * control
  171. * 01 -> receiver compares
  172. * XON2 and XOFF2
  173. * and controls
  174. * transmitter
  175. * 10 -> receiver compares
  176. * XON1 and XOFF1
  177. * and controls
  178. * transmitter
  179. * 11 -> receiver compares
  180. * XON1, XON2, XOFF1 and
  181. * XOFF2 and controls
  182. * transmitter
  183. */
  184. #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
  185. #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
  186. *
  187. * SWFLOW bits 3 & 2 table:
  188. * 00 -> no received flow
  189. * control
  190. * 01 -> transmitter generates
  191. * XON2 and XOFF2
  192. * 10 -> transmitter generates
  193. * XON1 and XOFF1
  194. * 11 -> transmitter generates
  195. * XON1, XON2, XOFF1 and
  196. * XOFF2
  197. */
  198. /* GPIO configuration register bits */
  199. #define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
  200. #define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
  201. #define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
  202. #define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
  203. #define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
  204. #define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
  205. #define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
  206. #define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
  207. /* GPIO DATA register bits */
  208. #define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
  209. #define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
  210. #define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
  211. #define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
  212. #define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
  213. #define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
  214. #define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
  215. #define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
  216. /* PLL configuration register masks */
  217. #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
  218. #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
  219. /* Baud rate generator configuration register bits */
  220. #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
  221. #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
  222. /* Clock source register bits */
  223. #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
  224. #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
  225. #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
  226. #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
  227. #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
  228. /* Misc definitions */
  229. #define MAX310X_FIFO_SIZE (128)
  230. /* MAX3107 specific */
  231. #define MAX3107_REV_ID (0xa0)
  232. #define MAX3107_REV_MASK (0xfe)
  233. /* IRQ status bits definitions */
  234. #define MAX310X_IRQ_TX (MAX310X_IRQ_TXFIFO_BIT | \
  235. MAX310X_IRQ_TXEMPTY_BIT)
  236. #define MAX310X_IRQ_RX (MAX310X_IRQ_RXFIFO_BIT | \
  237. MAX310X_IRQ_RXEMPTY_BIT)
  238. /* Supported chip types */
  239. enum {
  240. MAX310X_TYPE_MAX3107 = 3107,
  241. MAX310X_TYPE_MAX3108 = 3108,
  242. };
  243. struct max310x_port {
  244. struct uart_driver uart;
  245. struct uart_port port;
  246. const char *name;
  247. int uartclk;
  248. unsigned int nr_gpio;
  249. #ifdef CONFIG_GPIOLIB
  250. struct gpio_chip gpio;
  251. #endif
  252. struct regmap *regmap;
  253. struct regmap_config regcfg;
  254. struct workqueue_struct *wq;
  255. struct work_struct tx_work;
  256. struct mutex max310x_mutex;
  257. struct max310x_pdata *pdata;
  258. };
  259. static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg)
  260. {
  261. switch (reg) {
  262. case MAX310X_IRQSTS_REG:
  263. case MAX310X_LSR_IRQSTS_REG:
  264. case MAX310X_SPCHR_IRQSTS_REG:
  265. case MAX310X_STS_IRQSTS_REG:
  266. case MAX310X_TXFIFOLVL_REG:
  267. case MAX310X_RXFIFOLVL_REG:
  268. case MAX3107_REVID_REG: /* Only available on MAX3107 */
  269. return false;
  270. default:
  271. break;
  272. }
  273. return true;
  274. }
  275. static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
  276. {
  277. switch (reg) {
  278. case MAX310X_RHR_REG:
  279. case MAX310X_IRQSTS_REG:
  280. case MAX310X_LSR_IRQSTS_REG:
  281. case MAX310X_SPCHR_IRQSTS_REG:
  282. case MAX310X_STS_IRQSTS_REG:
  283. case MAX310X_TXFIFOLVL_REG:
  284. case MAX310X_RXFIFOLVL_REG:
  285. case MAX310X_GPIODATA_REG:
  286. return true;
  287. default:
  288. break;
  289. }
  290. return false;
  291. }
  292. static bool max310x_reg_precious(struct device *dev, unsigned int reg)
  293. {
  294. switch (reg) {
  295. case MAX310X_RHR_REG:
  296. case MAX310X_IRQSTS_REG:
  297. case MAX310X_SPCHR_IRQSTS_REG:
  298. case MAX310X_STS_IRQSTS_REG:
  299. return true;
  300. default:
  301. break;
  302. }
  303. return false;
  304. }
  305. static void max310x_set_baud(struct max310x_port *s, int baud)
  306. {
  307. unsigned int mode = 0, div = s->uartclk / baud;
  308. if (!(div / 16)) {
  309. /* Mode x2 */
  310. mode = MAX310X_BRGCFG_2XMODE_BIT;
  311. div = (s->uartclk * 2) / baud;
  312. }
  313. if (!(div / 16)) {
  314. /* Mode x4 */
  315. mode = MAX310X_BRGCFG_4XMODE_BIT;
  316. div = (s->uartclk * 4) / baud;
  317. }
  318. regmap_write(s->regmap, MAX310X_BRGDIVMSB_REG,
  319. ((div / 16) >> 8) & 0xff);
  320. regmap_write(s->regmap, MAX310X_BRGDIVLSB_REG, (div / 16) & 0xff);
  321. regmap_write(s->regmap, MAX310X_BRGCFG_REG, (div % 16) | mode);
  322. }
  323. static void max310x_wait_pll(struct max310x_port *s)
  324. {
  325. int tryes = 1000;
  326. /* Wait for PLL only if crystal is used */
  327. if (!(s->pdata->driver_flags & MAX310X_EXT_CLK)) {
  328. unsigned int sts = 0;
  329. while (tryes--) {
  330. regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &sts);
  331. if (sts & MAX310X_STS_CLKREADY_BIT)
  332. break;
  333. }
  334. }
  335. }
  336. static int max310x_update_best_err(unsigned long f, long *besterr)
  337. {
  338. /* Use baudrate 115200 for calculate error */
  339. long err = f % (115200 * 16);
  340. if ((*besterr < 0) || (*besterr > err)) {
  341. *besterr = err;
  342. return 0;
  343. }
  344. return 1;
  345. }
  346. static int max310x_set_ref_clk(struct max310x_port *s)
  347. {
  348. unsigned int div, clksrc, pllcfg = 0;
  349. long besterr = -1;
  350. unsigned long fdiv, fmul, bestfreq = s->pdata->frequency;
  351. /* First, update error without PLL */
  352. max310x_update_best_err(s->pdata->frequency, &besterr);
  353. /* Try all possible PLL dividers */
  354. for (div = 1; (div <= 63) && besterr; div++) {
  355. fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div);
  356. /* Try multiplier 6 */
  357. fmul = fdiv * 6;
  358. if ((fdiv >= 500000) && (fdiv <= 800000))
  359. if (!max310x_update_best_err(fmul, &besterr)) {
  360. pllcfg = (0 << 6) | div;
  361. bestfreq = fmul;
  362. }
  363. /* Try multiplier 48 */
  364. fmul = fdiv * 48;
  365. if ((fdiv >= 850000) && (fdiv <= 1200000))
  366. if (!max310x_update_best_err(fmul, &besterr)) {
  367. pllcfg = (1 << 6) | div;
  368. bestfreq = fmul;
  369. }
  370. /* Try multiplier 96 */
  371. fmul = fdiv * 96;
  372. if ((fdiv >= 425000) && (fdiv <= 1000000))
  373. if (!max310x_update_best_err(fmul, &besterr)) {
  374. pllcfg = (2 << 6) | div;
  375. bestfreq = fmul;
  376. }
  377. /* Try multiplier 144 */
  378. fmul = fdiv * 144;
  379. if ((fdiv >= 390000) && (fdiv <= 667000))
  380. if (!max310x_update_best_err(fmul, &besterr)) {
  381. pllcfg = (3 << 6) | div;
  382. bestfreq = fmul;
  383. }
  384. }
  385. /* Configure clock source */
  386. if (s->pdata->driver_flags & MAX310X_EXT_CLK)
  387. clksrc = MAX310X_CLKSRC_EXTCLK_BIT;
  388. else
  389. clksrc = MAX310X_CLKSRC_CRYST_BIT;
  390. /* Configure PLL */
  391. if (pllcfg) {
  392. clksrc |= MAX310X_CLKSRC_PLL_BIT;
  393. regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
  394. } else
  395. clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
  396. regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
  397. if (pllcfg)
  398. max310x_wait_pll(s);
  399. dev_dbg(s->port.dev, "Reference clock set to %lu Hz\n", bestfreq);
  400. return (int)bestfreq;
  401. }
  402. static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen)
  403. {
  404. unsigned int sts = 0, ch = 0, flag;
  405. if (unlikely(rxlen >= MAX310X_FIFO_SIZE)) {
  406. dev_warn(s->port.dev, "Possible RX FIFO overrun %d\n", rxlen);
  407. /* Ensure sanity of RX level */
  408. rxlen = MAX310X_FIFO_SIZE;
  409. }
  410. dev_dbg(s->port.dev, "RX Len = %u\n", rxlen);
  411. while (rxlen--) {
  412. regmap_read(s->regmap, MAX310X_RHR_REG, &ch);
  413. regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &sts);
  414. sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
  415. MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
  416. s->port.icount.rx++;
  417. flag = TTY_NORMAL;
  418. if (unlikely(sts)) {
  419. if (sts & MAX310X_LSR_RXBRK_BIT) {
  420. s->port.icount.brk++;
  421. if (uart_handle_break(&s->port))
  422. continue;
  423. } else if (sts & MAX310X_LSR_RXPAR_BIT)
  424. s->port.icount.parity++;
  425. else if (sts & MAX310X_LSR_FRERR_BIT)
  426. s->port.icount.frame++;
  427. else if (sts & MAX310X_LSR_RXOVR_BIT)
  428. s->port.icount.overrun++;
  429. sts &= s->port.read_status_mask;
  430. if (sts & MAX310X_LSR_RXBRK_BIT)
  431. flag = TTY_BREAK;
  432. else if (sts & MAX310X_LSR_RXPAR_BIT)
  433. flag = TTY_PARITY;
  434. else if (sts & MAX310X_LSR_FRERR_BIT)
  435. flag = TTY_FRAME;
  436. else if (sts & MAX310X_LSR_RXOVR_BIT)
  437. flag = TTY_OVERRUN;
  438. }
  439. if (uart_handle_sysrq_char(s->port, ch))
  440. continue;
  441. if (sts & s->port.ignore_status_mask)
  442. continue;
  443. uart_insert_char(&s->port, sts, MAX310X_LSR_RXOVR_BIT,
  444. ch, flag);
  445. }
  446. tty_flip_buffer_push(&s->port.state->port);
  447. }
  448. static void max310x_handle_tx(struct max310x_port *s)
  449. {
  450. struct circ_buf *xmit = &s->port.state->xmit;
  451. unsigned int txlen = 0, to_send;
  452. if (unlikely(s->port.x_char)) {
  453. regmap_write(s->regmap, MAX310X_THR_REG, s->port.x_char);
  454. s->port.icount.tx++;
  455. s->port.x_char = 0;
  456. return;
  457. }
  458. if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
  459. return;
  460. /* Get length of data pending in circular buffer */
  461. to_send = uart_circ_chars_pending(xmit);
  462. if (likely(to_send)) {
  463. /* Limit to size of TX FIFO */
  464. regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &txlen);
  465. txlen = MAX310X_FIFO_SIZE - txlen;
  466. to_send = (to_send > txlen) ? txlen : to_send;
  467. dev_dbg(s->port.dev, "TX Len = %u\n", to_send);
  468. /* Add data to send */
  469. s->port.icount.tx += to_send;
  470. while (to_send--) {
  471. regmap_write(s->regmap, MAX310X_THR_REG,
  472. xmit->buf[xmit->tail]);
  473. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  474. };
  475. }
  476. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  477. uart_write_wakeup(&s->port);
  478. }
  479. static irqreturn_t max310x_ist(int irq, void *dev_id)
  480. {
  481. struct max310x_port *s = (struct max310x_port *)dev_id;
  482. unsigned int ists = 0, lsr = 0, rxlen = 0;
  483. mutex_lock(&s->max310x_mutex);
  484. for (;;) {
  485. /* Read IRQ status & RX FIFO level */
  486. regmap_read(s->regmap, MAX310X_IRQSTS_REG, &ists);
  487. regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &lsr);
  488. regmap_read(s->regmap, MAX310X_RXFIFOLVL_REG, &rxlen);
  489. if (!ists && !(lsr & MAX310X_LSR_RXTO_BIT) && !rxlen)
  490. break;
  491. dev_dbg(s->port.dev, "IRQ status: 0x%02x\n", ists);
  492. if (rxlen)
  493. max310x_handle_rx(s, rxlen);
  494. if (ists & MAX310X_IRQ_TX)
  495. max310x_handle_tx(s);
  496. if (ists & MAX310X_IRQ_CTS_BIT)
  497. uart_handle_cts_change(&s->port,
  498. !!(lsr & MAX310X_LSR_CTS_BIT));
  499. }
  500. mutex_unlock(&s->max310x_mutex);
  501. return IRQ_HANDLED;
  502. }
  503. static void max310x_wq_proc(struct work_struct *ws)
  504. {
  505. struct max310x_port *s = container_of(ws, struct max310x_port, tx_work);
  506. mutex_lock(&s->max310x_mutex);
  507. max310x_handle_tx(s);
  508. mutex_unlock(&s->max310x_mutex);
  509. }
  510. static void max310x_start_tx(struct uart_port *port)
  511. {
  512. struct max310x_port *s = container_of(port, struct max310x_port, port);
  513. queue_work(s->wq, &s->tx_work);
  514. }
  515. static void max310x_stop_tx(struct uart_port *port)
  516. {
  517. /* Do nothing */
  518. }
  519. static void max310x_stop_rx(struct uart_port *port)
  520. {
  521. /* Do nothing */
  522. }
  523. static unsigned int max310x_tx_empty(struct uart_port *port)
  524. {
  525. unsigned int val = 0;
  526. struct max310x_port *s = container_of(port, struct max310x_port, port);
  527. mutex_lock(&s->max310x_mutex);
  528. regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &val);
  529. mutex_unlock(&s->max310x_mutex);
  530. return val ? 0 : TIOCSER_TEMT;
  531. }
  532. static void max310x_enable_ms(struct uart_port *port)
  533. {
  534. /* Modem status not supported */
  535. }
  536. static unsigned int max310x_get_mctrl(struct uart_port *port)
  537. {
  538. /* DCD and DSR are not wired and CTS/RTS is handled automatically
  539. * so just indicate DSR and CAR asserted
  540. */
  541. return TIOCM_DSR | TIOCM_CAR;
  542. }
  543. static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
  544. {
  545. /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
  546. * so do nothing
  547. */
  548. }
  549. static void max310x_break_ctl(struct uart_port *port, int break_state)
  550. {
  551. struct max310x_port *s = container_of(port, struct max310x_port, port);
  552. mutex_lock(&s->max310x_mutex);
  553. regmap_update_bits(s->regmap, MAX310X_LCR_REG,
  554. MAX310X_LCR_TXBREAK_BIT,
  555. break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
  556. mutex_unlock(&s->max310x_mutex);
  557. }
  558. static void max310x_set_termios(struct uart_port *port,
  559. struct ktermios *termios,
  560. struct ktermios *old)
  561. {
  562. struct max310x_port *s = container_of(port, struct max310x_port, port);
  563. unsigned int lcr, flow = 0;
  564. int baud;
  565. mutex_lock(&s->max310x_mutex);
  566. /* Mask termios capabilities we don't support */
  567. termios->c_cflag &= ~CMSPAR;
  568. termios->c_iflag &= ~IXANY;
  569. /* Word size */
  570. switch (termios->c_cflag & CSIZE) {
  571. case CS5:
  572. lcr = MAX310X_LCR_WORD_LEN_5;
  573. break;
  574. case CS6:
  575. lcr = MAX310X_LCR_WORD_LEN_6;
  576. break;
  577. case CS7:
  578. lcr = MAX310X_LCR_WORD_LEN_7;
  579. break;
  580. case CS8:
  581. default:
  582. lcr = MAX310X_LCR_WORD_LEN_8;
  583. break;
  584. }
  585. /* Parity */
  586. if (termios->c_cflag & PARENB) {
  587. lcr |= MAX310X_LCR_PARITY_BIT;
  588. if (!(termios->c_cflag & PARODD))
  589. lcr |= MAX310X_LCR_EVENPARITY_BIT;
  590. }
  591. /* Stop bits */
  592. if (termios->c_cflag & CSTOPB)
  593. lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
  594. /* Update LCR register */
  595. regmap_write(s->regmap, MAX310X_LCR_REG, lcr);
  596. /* Set read status mask */
  597. port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
  598. if (termios->c_iflag & INPCK)
  599. port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
  600. MAX310X_LSR_FRERR_BIT;
  601. if (termios->c_iflag & (BRKINT | PARMRK))
  602. port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
  603. /* Set status ignore mask */
  604. port->ignore_status_mask = 0;
  605. if (termios->c_iflag & IGNBRK)
  606. port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
  607. if (!(termios->c_cflag & CREAD))
  608. port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
  609. MAX310X_LSR_RXOVR_BIT |
  610. MAX310X_LSR_FRERR_BIT |
  611. MAX310X_LSR_RXBRK_BIT;
  612. /* Configure flow control */
  613. regmap_write(s->regmap, MAX310X_XON1_REG, termios->c_cc[VSTART]);
  614. regmap_write(s->regmap, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
  615. if (termios->c_cflag & CRTSCTS)
  616. flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
  617. MAX310X_FLOWCTRL_AUTORTS_BIT;
  618. if (termios->c_iflag & IXON)
  619. flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
  620. MAX310X_FLOWCTRL_SWFLOWEN_BIT;
  621. if (termios->c_iflag & IXOFF)
  622. flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
  623. MAX310X_FLOWCTRL_SWFLOWEN_BIT;
  624. regmap_write(s->regmap, MAX310X_FLOWCTRL_REG, flow);
  625. /* Get baud rate generator configuration */
  626. baud = uart_get_baud_rate(port, termios, old,
  627. port->uartclk / 16 / 0xffff,
  628. port->uartclk / 4);
  629. /* Setup baudrate generator */
  630. max310x_set_baud(s, baud);
  631. /* Update timeout according to new baud rate */
  632. uart_update_timeout(port, termios->c_cflag, baud);
  633. mutex_unlock(&s->max310x_mutex);
  634. }
  635. static int max310x_startup(struct uart_port *port)
  636. {
  637. unsigned int val, line = port->line;
  638. struct max310x_port *s = container_of(port, struct max310x_port, port);
  639. if (s->pdata->suspend)
  640. s->pdata->suspend(0);
  641. mutex_lock(&s->max310x_mutex);
  642. /* Configure baud rate, 9600 as default */
  643. max310x_set_baud(s, 9600);
  644. /* Configure LCR register, 8N1 mode by default */
  645. val = MAX310X_LCR_WORD_LEN_8;
  646. regmap_write(s->regmap, MAX310X_LCR_REG, val);
  647. /* Configure MODE1 register */
  648. regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
  649. MAX310X_MODE1_TRNSCVCTRL_BIT,
  650. (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL)
  651. ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0);
  652. /* Configure MODE2 register */
  653. val = MAX310X_MODE2_RXEMPTINV_BIT;
  654. if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK)
  655. val |= MAX310X_MODE2_LOOPBACK_BIT;
  656. if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS)
  657. val |= MAX310X_MODE2_ECHOSUPR_BIT;
  658. /* Reset FIFOs */
  659. val |= MAX310X_MODE2_FIFORST_BIT;
  660. regmap_write(s->regmap, MAX310X_MODE2_REG, val);
  661. /* Configure FIFO trigger level register */
  662. /* RX FIFO trigger for 16 words, TX FIFO trigger for 64 words */
  663. val = MAX310X_FIFOTRIGLVL_RX(16) | MAX310X_FIFOTRIGLVL_TX(64);
  664. regmap_write(s->regmap, MAX310X_FIFOTRIGLVL_REG, val);
  665. /* Configure flow control levels */
  666. /* Flow control halt level 96, resume level 48 */
  667. val = MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96);
  668. regmap_write(s->regmap, MAX310X_FLOWLVL_REG, val);
  669. /* Clear timeout register */
  670. regmap_write(s->regmap, MAX310X_RXTO_REG, 0);
  671. /* Configure LSR interrupt enable register */
  672. /* Enable RX timeout interrupt */
  673. val = MAX310X_LSR_RXTO_BIT;
  674. regmap_write(s->regmap, MAX310X_LSR_IRQEN_REG, val);
  675. /* Clear FIFO reset */
  676. regmap_update_bits(s->regmap, MAX310X_MODE2_REG,
  677. MAX310X_MODE2_FIFORST_BIT, 0);
  678. /* Clear IRQ status register by reading it */
  679. regmap_read(s->regmap, MAX310X_IRQSTS_REG, &val);
  680. /* Configure interrupt enable register */
  681. /* Enable CTS change interrupt */
  682. val = MAX310X_IRQ_CTS_BIT;
  683. /* Enable RX, TX interrupts */
  684. val |= MAX310X_IRQ_RX | MAX310X_IRQ_TX;
  685. regmap_write(s->regmap, MAX310X_IRQEN_REG, val);
  686. mutex_unlock(&s->max310x_mutex);
  687. return 0;
  688. }
  689. static void max310x_shutdown(struct uart_port *port)
  690. {
  691. struct max310x_port *s = container_of(port, struct max310x_port, port);
  692. /* Disable all interrupts */
  693. mutex_lock(&s->max310x_mutex);
  694. regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
  695. mutex_unlock(&s->max310x_mutex);
  696. if (s->pdata->suspend)
  697. s->pdata->suspend(1);
  698. }
  699. static const char *max310x_type(struct uart_port *port)
  700. {
  701. struct max310x_port *s = container_of(port, struct max310x_port, port);
  702. return (port->type == PORT_MAX310X) ? s->name : NULL;
  703. }
  704. static int max310x_request_port(struct uart_port *port)
  705. {
  706. /* Do nothing */
  707. return 0;
  708. }
  709. static void max310x_release_port(struct uart_port *port)
  710. {
  711. /* Do nothing */
  712. }
  713. static void max310x_config_port(struct uart_port *port, int flags)
  714. {
  715. if (flags & UART_CONFIG_TYPE)
  716. port->type = PORT_MAX310X;
  717. }
  718. static int max310x_verify_port(struct uart_port *port, struct serial_struct *ser)
  719. {
  720. if ((ser->type == PORT_UNKNOWN) || (ser->type == PORT_MAX310X))
  721. return 0;
  722. if (ser->irq == port->irq)
  723. return 0;
  724. return -EINVAL;
  725. }
  726. static struct uart_ops max310x_ops = {
  727. .tx_empty = max310x_tx_empty,
  728. .set_mctrl = max310x_set_mctrl,
  729. .get_mctrl = max310x_get_mctrl,
  730. .stop_tx = max310x_stop_tx,
  731. .start_tx = max310x_start_tx,
  732. .stop_rx = max310x_stop_rx,
  733. .enable_ms = max310x_enable_ms,
  734. .break_ctl = max310x_break_ctl,
  735. .startup = max310x_startup,
  736. .shutdown = max310x_shutdown,
  737. .set_termios = max310x_set_termios,
  738. .type = max310x_type,
  739. .request_port = max310x_request_port,
  740. .release_port = max310x_release_port,
  741. .config_port = max310x_config_port,
  742. .verify_port = max310x_verify_port,
  743. };
  744. #ifdef CONFIG_PM_SLEEP
  745. static int max310x_suspend(struct device *dev)
  746. {
  747. int ret;
  748. struct max310x_port *s = dev_get_drvdata(dev);
  749. dev_dbg(dev, "Suspend\n");
  750. ret = uart_suspend_port(&s->uart, &s->port);
  751. mutex_lock(&s->max310x_mutex);
  752. /* Enable sleep mode */
  753. regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
  754. MAX310X_MODE1_FORCESLEEP_BIT,
  755. MAX310X_MODE1_FORCESLEEP_BIT);
  756. mutex_unlock(&s->max310x_mutex);
  757. if (s->pdata->suspend)
  758. s->pdata->suspend(1);
  759. return ret;
  760. }
  761. static int max310x_resume(struct device *dev)
  762. {
  763. struct max310x_port *s = dev_get_drvdata(dev);
  764. dev_dbg(dev, "Resume\n");
  765. if (s->pdata->suspend)
  766. s->pdata->suspend(0);
  767. mutex_lock(&s->max310x_mutex);
  768. /* Disable sleep mode */
  769. regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
  770. MAX310X_MODE1_FORCESLEEP_BIT,
  771. 0);
  772. max310x_wait_pll(s);
  773. mutex_unlock(&s->max310x_mutex);
  774. return uart_resume_port(&s->uart, &s->port);
  775. }
  776. static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
  777. #define MAX310X_PM_OPS (&max310x_pm_ops)
  778. #else
  779. #define MAX310X_PM_OPS NULL
  780. #endif
  781. #ifdef CONFIG_GPIOLIB
  782. static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
  783. {
  784. unsigned int val = 0;
  785. struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
  786. mutex_lock(&s->max310x_mutex);
  787. regmap_read(s->regmap, MAX310X_GPIODATA_REG, &val);
  788. mutex_unlock(&s->max310x_mutex);
  789. return !!((val >> 4) & (1 << offset));
  790. }
  791. static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  792. {
  793. struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
  794. mutex_lock(&s->max310x_mutex);
  795. regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
  796. 1 << offset : 0);
  797. mutex_unlock(&s->max310x_mutex);
  798. }
  799. static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  800. {
  801. struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
  802. mutex_lock(&s->max310x_mutex);
  803. regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, 0);
  804. mutex_unlock(&s->max310x_mutex);
  805. return 0;
  806. }
  807. static int max310x_gpio_direction_output(struct gpio_chip *chip,
  808. unsigned offset, int value)
  809. {
  810. struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
  811. mutex_lock(&s->max310x_mutex);
  812. regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset,
  813. 1 << offset);
  814. regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
  815. 1 << offset : 0);
  816. mutex_unlock(&s->max310x_mutex);
  817. return 0;
  818. }
  819. #endif
  820. /* Generic platform data */
  821. static struct max310x_pdata generic_plat_data = {
  822. .driver_flags = MAX310X_EXT_CLK,
  823. .uart_flags[0] = MAX310X_ECHO_SUPRESS,
  824. .frequency = 26000000,
  825. };
  826. static int max310x_probe(struct spi_device *spi)
  827. {
  828. struct max310x_port *s;
  829. struct device *dev = &spi->dev;
  830. int chiptype = spi_get_device_id(spi)->driver_data;
  831. struct max310x_pdata *pdata = dev->platform_data;
  832. unsigned int val = 0;
  833. int ret;
  834. /* Check for IRQ */
  835. if (spi->irq <= 0) {
  836. dev_err(dev, "No IRQ specified\n");
  837. return -ENOTSUPP;
  838. }
  839. /* Alloc port structure */
  840. s = devm_kzalloc(dev, sizeof(struct max310x_port), GFP_KERNEL);
  841. if (!s) {
  842. dev_err(dev, "Error allocating port structure\n");
  843. return -ENOMEM;
  844. }
  845. dev_set_drvdata(dev, s);
  846. if (!pdata) {
  847. dev_warn(dev, "No platform data supplied, using defaults\n");
  848. pdata = &generic_plat_data;
  849. }
  850. s->pdata = pdata;
  851. /* Individual chip settings */
  852. switch (chiptype) {
  853. case MAX310X_TYPE_MAX3107:
  854. s->name = "MAX3107";
  855. s->nr_gpio = 4;
  856. s->uart.nr = 1;
  857. s->regcfg.max_register = 0x1f;
  858. break;
  859. case MAX310X_TYPE_MAX3108:
  860. s->name = "MAX3108";
  861. s->nr_gpio = 4;
  862. s->uart.nr = 1;
  863. s->regcfg.max_register = 0x1e;
  864. break;
  865. default:
  866. dev_err(dev, "Unsupported chip type %i\n", chiptype);
  867. return -ENOTSUPP;
  868. }
  869. /* Check input frequency */
  870. if ((pdata->driver_flags & MAX310X_EXT_CLK) &&
  871. ((pdata->frequency < 500000) || (pdata->frequency > 35000000)))
  872. goto err_freq;
  873. /* Check frequency for quartz */
  874. if (!(pdata->driver_flags & MAX310X_EXT_CLK) &&
  875. ((pdata->frequency < 1000000) || (pdata->frequency > 4000000)))
  876. goto err_freq;
  877. mutex_init(&s->max310x_mutex);
  878. /* Setup SPI bus */
  879. spi->mode = SPI_MODE_0;
  880. spi->bits_per_word = 8;
  881. spi->max_speed_hz = 26000000;
  882. spi_setup(spi);
  883. /* Setup regmap */
  884. s->regcfg.reg_bits = 8;
  885. s->regcfg.val_bits = 8;
  886. s->regcfg.read_flag_mask = 0x00;
  887. s->regcfg.write_flag_mask = 0x80;
  888. s->regcfg.cache_type = REGCACHE_RBTREE;
  889. s->regcfg.writeable_reg = max3107_8_reg_writeable;
  890. s->regcfg.volatile_reg = max310x_reg_volatile;
  891. s->regcfg.precious_reg = max310x_reg_precious;
  892. s->regmap = devm_regmap_init_spi(spi, &s->regcfg);
  893. if (IS_ERR(s->regmap)) {
  894. ret = PTR_ERR(s->regmap);
  895. dev_err(dev, "Failed to initialize register map\n");
  896. goto err_out;
  897. }
  898. /* Reset chip & check SPI function */
  899. ret = regmap_write(s->regmap, MAX310X_MODE2_REG, MAX310X_MODE2_RST_BIT);
  900. if (ret) {
  901. dev_err(dev, "SPI transfer failed\n");
  902. goto err_out;
  903. }
  904. /* Clear chip reset */
  905. regmap_write(s->regmap, MAX310X_MODE2_REG, 0);
  906. switch (chiptype) {
  907. case MAX310X_TYPE_MAX3107:
  908. /* Check REV ID to ensure we are talking to what we expect */
  909. regmap_read(s->regmap, MAX3107_REVID_REG, &val);
  910. if (((val & MAX3107_REV_MASK) != MAX3107_REV_ID)) {
  911. dev_err(dev, "%s ID 0x%02x does not match\n",
  912. s->name, val);
  913. ret = -ENODEV;
  914. goto err_out;
  915. }
  916. break;
  917. case MAX310X_TYPE_MAX3108:
  918. /* MAX3108 have not REV ID register, we just check default value
  919. * from clocksource register to make sure everything works.
  920. */
  921. regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
  922. if (val != (MAX310X_CLKSRC_EXTCLK_BIT |
  923. MAX310X_CLKSRC_PLLBYP_BIT)) {
  924. dev_err(dev, "%s not present\n", s->name);
  925. ret = -ENODEV;
  926. goto err_out;
  927. }
  928. break;
  929. }
  930. /* Board specific configure */
  931. if (pdata->init)
  932. pdata->init();
  933. if (pdata->suspend)
  934. pdata->suspend(0);
  935. /* Calculate referecne clock */
  936. s->uartclk = max310x_set_ref_clk(s);
  937. /* Disable all interrupts */
  938. regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
  939. /* Setup MODE1 register */
  940. val = MAX310X_MODE1_IRQSEL_BIT; /* Enable IRQ pin */
  941. if (pdata->driver_flags & MAX310X_AUTOSLEEP)
  942. val = MAX310X_MODE1_AUTOSLEEP_BIT;
  943. regmap_write(s->regmap, MAX310X_MODE1_REG, val);
  944. /* Setup interrupt */
  945. ret = devm_request_threaded_irq(dev, spi->irq, NULL, max310x_ist,
  946. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  947. dev_name(dev), s);
  948. if (ret) {
  949. dev_err(dev, "Unable to reguest IRQ %i\n", spi->irq);
  950. goto err_out;
  951. }
  952. /* Register UART driver */
  953. s->uart.owner = THIS_MODULE;
  954. s->uart.driver_name = dev_name(dev);
  955. s->uart.dev_name = "ttyMAX";
  956. s->uart.major = MAX310X_MAJOR;
  957. s->uart.minor = MAX310X_MINOR;
  958. ret = uart_register_driver(&s->uart);
  959. if (ret) {
  960. dev_err(dev, "Registering UART driver failed\n");
  961. goto err_out;
  962. }
  963. /* Initialize workqueue for start TX */
  964. s->wq = create_freezable_workqueue(dev_name(dev));
  965. INIT_WORK(&s->tx_work, max310x_wq_proc);
  966. /* Initialize UART port data */
  967. s->port.line = 0;
  968. s->port.dev = dev;
  969. s->port.irq = spi->irq;
  970. s->port.type = PORT_MAX310X;
  971. s->port.fifosize = MAX310X_FIFO_SIZE;
  972. s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
  973. s->port.iotype = UPIO_PORT;
  974. s->port.membase = (void __iomem *)0xffffffff; /* Bogus value */
  975. s->port.uartclk = s->uartclk;
  976. s->port.ops = &max310x_ops;
  977. uart_add_one_port(&s->uart, &s->port);
  978. #ifdef CONFIG_GPIOLIB
  979. /* Setup GPIO cotroller */
  980. if (pdata->gpio_base) {
  981. s->gpio.owner = THIS_MODULE;
  982. s->gpio.dev = dev;
  983. s->gpio.label = dev_name(dev);
  984. s->gpio.direction_input = max310x_gpio_direction_input;
  985. s->gpio.get = max310x_gpio_get;
  986. s->gpio.direction_output= max310x_gpio_direction_output;
  987. s->gpio.set = max310x_gpio_set;
  988. s->gpio.base = pdata->gpio_base;
  989. s->gpio.ngpio = s->nr_gpio;
  990. s->gpio.can_sleep = 1;
  991. if (gpiochip_add(&s->gpio)) {
  992. /* Indicate that we should not call gpiochip_remove */
  993. s->gpio.base = 0;
  994. }
  995. } else
  996. dev_info(dev, "GPIO support not enabled\n");
  997. #endif
  998. /* Go to suspend mode */
  999. if (pdata->suspend)
  1000. pdata->suspend(1);
  1001. return 0;
  1002. err_freq:
  1003. dev_err(dev, "Frequency parameter incorrect\n");
  1004. ret = -EINVAL;
  1005. err_out:
  1006. dev_set_drvdata(dev, NULL);
  1007. return ret;
  1008. }
  1009. static int max310x_remove(struct spi_device *spi)
  1010. {
  1011. struct device *dev = &spi->dev;
  1012. struct max310x_port *s = dev_get_drvdata(dev);
  1013. int ret = 0;
  1014. dev_dbg(dev, "Removing port\n");
  1015. devm_free_irq(dev, s->port.irq, s);
  1016. destroy_workqueue(s->wq);
  1017. uart_remove_one_port(&s->uart, &s->port);
  1018. uart_unregister_driver(&s->uart);
  1019. #ifdef CONFIG_GPIOLIB
  1020. if (s->pdata->gpio_base) {
  1021. ret = gpiochip_remove(&s->gpio);
  1022. if (ret)
  1023. dev_err(dev, "Failed to remove gpio chip: %d\n", ret);
  1024. }
  1025. #endif
  1026. dev_set_drvdata(dev, NULL);
  1027. if (s->pdata->suspend)
  1028. s->pdata->suspend(1);
  1029. if (s->pdata->exit)
  1030. s->pdata->exit();
  1031. return ret;
  1032. }
  1033. static const struct spi_device_id max310x_id_table[] = {
  1034. { "max3107", MAX310X_TYPE_MAX3107 },
  1035. { "max3108", MAX310X_TYPE_MAX3108 },
  1036. { }
  1037. };
  1038. MODULE_DEVICE_TABLE(spi, max310x_id_table);
  1039. static struct spi_driver max310x_driver = {
  1040. .driver = {
  1041. .name = "max310x",
  1042. .owner = THIS_MODULE,
  1043. .pm = MAX310X_PM_OPS,
  1044. },
  1045. .probe = max310x_probe,
  1046. .remove = max310x_remove,
  1047. .id_table = max310x_id_table,
  1048. };
  1049. module_spi_driver(max310x_driver);
  1050. MODULE_LICENSE("GPL v2");
  1051. MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
  1052. MODULE_DESCRIPTION("MAX310X serial driver");