atmel-isi.c 27 KB

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  1. /*
  2. * Copyright (c) 2011 Atmel Corporation
  3. * Josh Wu, <josh.wu@atmel.com>
  4. *
  5. * Based on previous work by Lars Haring, <lars.haring@atmel.com>
  6. * and Sedji Gaouaou
  7. * Based on the bttv driver for Bt848 with respective copyright holders
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/completion.h>
  15. #include <linux/delay.h>
  16. #include <linux/fs.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <media/atmel-isi.h>
  24. #include <media/soc_camera.h>
  25. #include <media/soc_mediabus.h>
  26. #include <media/videobuf2-dma-contig.h>
  27. #define MAX_BUFFER_NUM 32
  28. #define MAX_SUPPORT_WIDTH 2048
  29. #define MAX_SUPPORT_HEIGHT 2048
  30. #define VID_LIMIT_BYTES (16 * 1024 * 1024)
  31. #define MIN_FRAME_RATE 15
  32. #define FRAME_INTERVAL_MILLI_SEC (1000 / MIN_FRAME_RATE)
  33. /* ISI states */
  34. enum {
  35. ISI_STATE_IDLE = 0,
  36. ISI_STATE_READY,
  37. ISI_STATE_WAIT_SOF,
  38. };
  39. /* Frame buffer descriptor */
  40. struct fbd {
  41. /* Physical address of the frame buffer */
  42. u32 fb_address;
  43. /* DMA Control Register(only in HISI2) */
  44. u32 dma_ctrl;
  45. /* Physical address of the next fbd */
  46. u32 next_fbd_address;
  47. };
  48. static void set_dma_ctrl(struct fbd *fb_desc, u32 ctrl)
  49. {
  50. fb_desc->dma_ctrl = ctrl;
  51. }
  52. struct isi_dma_desc {
  53. struct list_head list;
  54. struct fbd *p_fbd;
  55. u32 fbd_phys;
  56. };
  57. /* Frame buffer data */
  58. struct frame_buffer {
  59. struct vb2_buffer vb;
  60. struct isi_dma_desc *p_dma_desc;
  61. struct list_head list;
  62. };
  63. struct atmel_isi {
  64. /* Protects the access of variables shared with the ISR */
  65. spinlock_t lock;
  66. void __iomem *regs;
  67. int sequence;
  68. /* State of the ISI module in capturing mode */
  69. int state;
  70. /* Wait queue for waiting for SOF */
  71. wait_queue_head_t vsync_wq;
  72. struct vb2_alloc_ctx *alloc_ctx;
  73. /* Allocate descriptors for dma buffer use */
  74. struct fbd *p_fb_descriptors;
  75. u32 fb_descriptors_phys;
  76. struct list_head dma_desc_head;
  77. struct isi_dma_desc dma_desc[MAX_BUFFER_NUM];
  78. struct completion complete;
  79. /* ISI peripherial clock */
  80. struct clk *pclk;
  81. /* ISI_MCK, feed to camera sensor to generate pixel clock */
  82. struct clk *mck;
  83. unsigned int irq;
  84. struct isi_platform_data *pdata;
  85. u16 width_flags; /* max 12 bits */
  86. struct list_head video_buffer_list;
  87. struct frame_buffer *active;
  88. struct soc_camera_device *icd;
  89. struct soc_camera_host soc_host;
  90. };
  91. static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val)
  92. {
  93. writel(val, isi->regs + reg);
  94. }
  95. static u32 isi_readl(struct atmel_isi *isi, u32 reg)
  96. {
  97. return readl(isi->regs + reg);
  98. }
  99. static int configure_geometry(struct atmel_isi *isi, u32 width,
  100. u32 height, enum v4l2_mbus_pixelcode code)
  101. {
  102. u32 cfg2, cr;
  103. switch (code) {
  104. /* YUV, including grey */
  105. case V4L2_MBUS_FMT_Y8_1X8:
  106. cr = ISI_CFG2_GRAYSCALE;
  107. break;
  108. case V4L2_MBUS_FMT_UYVY8_2X8:
  109. cr = ISI_CFG2_YCC_SWAP_MODE_3;
  110. break;
  111. case V4L2_MBUS_FMT_VYUY8_2X8:
  112. cr = ISI_CFG2_YCC_SWAP_MODE_2;
  113. break;
  114. case V4L2_MBUS_FMT_YUYV8_2X8:
  115. cr = ISI_CFG2_YCC_SWAP_MODE_1;
  116. break;
  117. case V4L2_MBUS_FMT_YVYU8_2X8:
  118. cr = ISI_CFG2_YCC_SWAP_DEFAULT;
  119. break;
  120. /* RGB, TODO */
  121. default:
  122. return -EINVAL;
  123. }
  124. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  125. cfg2 = isi_readl(isi, ISI_CFG2);
  126. cfg2 |= cr;
  127. /* Set width */
  128. cfg2 &= ~(ISI_CFG2_IM_HSIZE_MASK);
  129. cfg2 |= ((width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
  130. ISI_CFG2_IM_HSIZE_MASK;
  131. /* Set height */
  132. cfg2 &= ~(ISI_CFG2_IM_VSIZE_MASK);
  133. cfg2 |= ((height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
  134. & ISI_CFG2_IM_VSIZE_MASK;
  135. isi_writel(isi, ISI_CFG2, cfg2);
  136. return 0;
  137. }
  138. static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
  139. {
  140. if (isi->active) {
  141. struct vb2_buffer *vb = &isi->active->vb;
  142. struct frame_buffer *buf = isi->active;
  143. list_del_init(&buf->list);
  144. v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
  145. vb->v4l2_buf.sequence = isi->sequence++;
  146. vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
  147. }
  148. if (list_empty(&isi->video_buffer_list)) {
  149. isi->active = NULL;
  150. } else {
  151. /* start next dma frame. */
  152. isi->active = list_entry(isi->video_buffer_list.next,
  153. struct frame_buffer, list);
  154. isi_writel(isi, ISI_DMA_C_DSCR,
  155. isi->active->p_dma_desc->fbd_phys);
  156. isi_writel(isi, ISI_DMA_C_CTRL,
  157. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  158. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  159. }
  160. return IRQ_HANDLED;
  161. }
  162. /* ISI interrupt service routine */
  163. static irqreturn_t isi_interrupt(int irq, void *dev_id)
  164. {
  165. struct atmel_isi *isi = dev_id;
  166. u32 status, mask, pending;
  167. irqreturn_t ret = IRQ_NONE;
  168. spin_lock(&isi->lock);
  169. status = isi_readl(isi, ISI_STATUS);
  170. mask = isi_readl(isi, ISI_INTMASK);
  171. pending = status & mask;
  172. if (pending & ISI_CTRL_SRST) {
  173. complete(&isi->complete);
  174. isi_writel(isi, ISI_INTDIS, ISI_CTRL_SRST);
  175. ret = IRQ_HANDLED;
  176. } else if (pending & ISI_CTRL_DIS) {
  177. complete(&isi->complete);
  178. isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
  179. ret = IRQ_HANDLED;
  180. } else {
  181. if ((pending & ISI_SR_VSYNC) &&
  182. (isi->state == ISI_STATE_IDLE)) {
  183. isi->state = ISI_STATE_READY;
  184. wake_up_interruptible(&isi->vsync_wq);
  185. ret = IRQ_HANDLED;
  186. }
  187. if (likely(pending & ISI_SR_CXFR_DONE))
  188. ret = atmel_isi_handle_streaming(isi);
  189. }
  190. spin_unlock(&isi->lock);
  191. return ret;
  192. }
  193. #define WAIT_ISI_RESET 1
  194. #define WAIT_ISI_DISABLE 0
  195. static int atmel_isi_wait_status(struct atmel_isi *isi, int wait_reset)
  196. {
  197. unsigned long timeout;
  198. /*
  199. * The reset or disable will only succeed if we have a
  200. * pixel clock from the camera.
  201. */
  202. init_completion(&isi->complete);
  203. if (wait_reset) {
  204. isi_writel(isi, ISI_INTEN, ISI_CTRL_SRST);
  205. isi_writel(isi, ISI_CTRL, ISI_CTRL_SRST);
  206. } else {
  207. isi_writel(isi, ISI_INTEN, ISI_CTRL_DIS);
  208. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  209. }
  210. timeout = wait_for_completion_timeout(&isi->complete,
  211. msecs_to_jiffies(100));
  212. if (timeout == 0)
  213. return -ETIMEDOUT;
  214. return 0;
  215. }
  216. /* ------------------------------------------------------------------
  217. Videobuf operations
  218. ------------------------------------------------------------------*/
  219. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
  220. unsigned int *nbuffers, unsigned int *nplanes,
  221. unsigned int sizes[], void *alloc_ctxs[])
  222. {
  223. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  224. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  225. struct atmel_isi *isi = ici->priv;
  226. unsigned long size;
  227. int ret;
  228. /* Reset ISI */
  229. ret = atmel_isi_wait_status(isi, WAIT_ISI_RESET);
  230. if (ret < 0) {
  231. dev_err(icd->parent, "Reset ISI timed out\n");
  232. return ret;
  233. }
  234. /* Disable all interrupts */
  235. isi_writel(isi, ISI_INTDIS, ~0UL);
  236. size = icd->sizeimage;
  237. if (!*nbuffers || *nbuffers > MAX_BUFFER_NUM)
  238. *nbuffers = MAX_BUFFER_NUM;
  239. if (size * *nbuffers > VID_LIMIT_BYTES)
  240. *nbuffers = VID_LIMIT_BYTES / size;
  241. *nplanes = 1;
  242. sizes[0] = size;
  243. alloc_ctxs[0] = isi->alloc_ctx;
  244. isi->sequence = 0;
  245. isi->active = NULL;
  246. dev_dbg(icd->parent, "%s, count=%d, size=%ld\n", __func__,
  247. *nbuffers, size);
  248. return 0;
  249. }
  250. static int buffer_init(struct vb2_buffer *vb)
  251. {
  252. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  253. buf->p_dma_desc = NULL;
  254. INIT_LIST_HEAD(&buf->list);
  255. return 0;
  256. }
  257. static int buffer_prepare(struct vb2_buffer *vb)
  258. {
  259. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  260. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  261. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  262. struct atmel_isi *isi = ici->priv;
  263. unsigned long size;
  264. struct isi_dma_desc *desc;
  265. size = icd->sizeimage;
  266. if (vb2_plane_size(vb, 0) < size) {
  267. dev_err(icd->parent, "%s data will not fit into plane (%lu < %lu)\n",
  268. __func__, vb2_plane_size(vb, 0), size);
  269. return -EINVAL;
  270. }
  271. vb2_set_plane_payload(&buf->vb, 0, size);
  272. if (!buf->p_dma_desc) {
  273. if (list_empty(&isi->dma_desc_head)) {
  274. dev_err(icd->parent, "Not enough dma descriptors.\n");
  275. return -EINVAL;
  276. } else {
  277. /* Get an available descriptor */
  278. desc = list_entry(isi->dma_desc_head.next,
  279. struct isi_dma_desc, list);
  280. /* Delete the descriptor since now it is used */
  281. list_del_init(&desc->list);
  282. /* Initialize the dma descriptor */
  283. desc->p_fbd->fb_address =
  284. vb2_dma_contig_plane_dma_addr(vb, 0);
  285. desc->p_fbd->next_fbd_address = 0;
  286. set_dma_ctrl(desc->p_fbd, ISI_DMA_CTRL_WB);
  287. buf->p_dma_desc = desc;
  288. }
  289. }
  290. return 0;
  291. }
  292. static void buffer_cleanup(struct vb2_buffer *vb)
  293. {
  294. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  295. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  296. struct atmel_isi *isi = ici->priv;
  297. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  298. /* This descriptor is available now and we add to head list */
  299. if (buf->p_dma_desc)
  300. list_add(&buf->p_dma_desc->list, &isi->dma_desc_head);
  301. }
  302. static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
  303. {
  304. u32 ctrl, cfg1;
  305. cfg1 = isi_readl(isi, ISI_CFG1);
  306. /* Enable irq: cxfr for the codec path, pxfr for the preview path */
  307. isi_writel(isi, ISI_INTEN,
  308. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  309. /* Check if already in a frame */
  310. if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
  311. dev_err(isi->icd->parent, "Already in frame handling.\n");
  312. return;
  313. }
  314. isi_writel(isi, ISI_DMA_C_DSCR, buffer->p_dma_desc->fbd_phys);
  315. isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  316. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  317. /* Enable linked list */
  318. cfg1 |= isi->pdata->frate | ISI_CFG1_DISCR;
  319. /* Enable codec path and ISI */
  320. ctrl = ISI_CTRL_CDC | ISI_CTRL_EN;
  321. isi_writel(isi, ISI_CTRL, ctrl);
  322. isi_writel(isi, ISI_CFG1, cfg1);
  323. }
  324. static void buffer_queue(struct vb2_buffer *vb)
  325. {
  326. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  327. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  328. struct atmel_isi *isi = ici->priv;
  329. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  330. unsigned long flags = 0;
  331. spin_lock_irqsave(&isi->lock, flags);
  332. list_add_tail(&buf->list, &isi->video_buffer_list);
  333. if (isi->active == NULL) {
  334. isi->active = buf;
  335. if (vb2_is_streaming(vb->vb2_queue))
  336. start_dma(isi, buf);
  337. }
  338. spin_unlock_irqrestore(&isi->lock, flags);
  339. }
  340. static int start_streaming(struct vb2_queue *vq, unsigned int count)
  341. {
  342. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  343. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  344. struct atmel_isi *isi = ici->priv;
  345. u32 sr = 0;
  346. int ret;
  347. spin_lock_irq(&isi->lock);
  348. isi->state = ISI_STATE_IDLE;
  349. /* Clear any pending SOF interrupt */
  350. sr = isi_readl(isi, ISI_STATUS);
  351. /* Enable VSYNC interrupt for SOF */
  352. isi_writel(isi, ISI_INTEN, ISI_SR_VSYNC);
  353. isi_writel(isi, ISI_CTRL, ISI_CTRL_EN);
  354. spin_unlock_irq(&isi->lock);
  355. dev_dbg(icd->parent, "Waiting for SOF\n");
  356. ret = wait_event_interruptible(isi->vsync_wq,
  357. isi->state != ISI_STATE_IDLE);
  358. if (ret)
  359. goto err;
  360. if (isi->state != ISI_STATE_READY) {
  361. ret = -EIO;
  362. goto err;
  363. }
  364. spin_lock_irq(&isi->lock);
  365. isi->state = ISI_STATE_WAIT_SOF;
  366. isi_writel(isi, ISI_INTDIS, ISI_SR_VSYNC);
  367. if (count)
  368. start_dma(isi, isi->active);
  369. spin_unlock_irq(&isi->lock);
  370. return 0;
  371. err:
  372. isi->active = NULL;
  373. isi->sequence = 0;
  374. INIT_LIST_HEAD(&isi->video_buffer_list);
  375. return ret;
  376. }
  377. /* abort streaming and wait for last buffer */
  378. static int stop_streaming(struct vb2_queue *vq)
  379. {
  380. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  381. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  382. struct atmel_isi *isi = ici->priv;
  383. struct frame_buffer *buf, *node;
  384. int ret = 0;
  385. unsigned long timeout;
  386. spin_lock_irq(&isi->lock);
  387. isi->active = NULL;
  388. /* Release all active buffers */
  389. list_for_each_entry_safe(buf, node, &isi->video_buffer_list, list) {
  390. list_del_init(&buf->list);
  391. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  392. }
  393. spin_unlock_irq(&isi->lock);
  394. timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
  395. /* Wait until the end of the current frame. */
  396. while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
  397. time_before(jiffies, timeout))
  398. msleep(1);
  399. if (time_after(jiffies, timeout)) {
  400. dev_err(icd->parent,
  401. "Timeout waiting for finishing codec request\n");
  402. return -ETIMEDOUT;
  403. }
  404. /* Disable interrupts */
  405. isi_writel(isi, ISI_INTDIS,
  406. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  407. /* Disable ISI and wait for it is done */
  408. ret = atmel_isi_wait_status(isi, WAIT_ISI_DISABLE);
  409. if (ret < 0)
  410. dev_err(icd->parent, "Disable ISI timed out\n");
  411. return ret;
  412. }
  413. static struct vb2_ops isi_video_qops = {
  414. .queue_setup = queue_setup,
  415. .buf_init = buffer_init,
  416. .buf_prepare = buffer_prepare,
  417. .buf_cleanup = buffer_cleanup,
  418. .buf_queue = buffer_queue,
  419. .start_streaming = start_streaming,
  420. .stop_streaming = stop_streaming,
  421. .wait_prepare = soc_camera_unlock,
  422. .wait_finish = soc_camera_lock,
  423. };
  424. /* ------------------------------------------------------------------
  425. SOC camera operations for the device
  426. ------------------------------------------------------------------*/
  427. static int isi_camera_init_videobuf(struct vb2_queue *q,
  428. struct soc_camera_device *icd)
  429. {
  430. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  431. q->io_modes = VB2_MMAP;
  432. q->drv_priv = icd;
  433. q->buf_struct_size = sizeof(struct frame_buffer);
  434. q->ops = &isi_video_qops;
  435. q->mem_ops = &vb2_dma_contig_memops;
  436. q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  437. return vb2_queue_init(q);
  438. }
  439. static int isi_camera_set_fmt(struct soc_camera_device *icd,
  440. struct v4l2_format *f)
  441. {
  442. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  443. struct atmel_isi *isi = ici->priv;
  444. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  445. const struct soc_camera_format_xlate *xlate;
  446. struct v4l2_pix_format *pix = &f->fmt.pix;
  447. struct v4l2_mbus_framefmt mf;
  448. int ret;
  449. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  450. if (!xlate) {
  451. dev_warn(icd->parent, "Format %x not found\n",
  452. pix->pixelformat);
  453. return -EINVAL;
  454. }
  455. dev_dbg(icd->parent, "Plan to set format %dx%d\n",
  456. pix->width, pix->height);
  457. mf.width = pix->width;
  458. mf.height = pix->height;
  459. mf.field = pix->field;
  460. mf.colorspace = pix->colorspace;
  461. mf.code = xlate->code;
  462. ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
  463. if (ret < 0)
  464. return ret;
  465. if (mf.code != xlate->code)
  466. return -EINVAL;
  467. ret = configure_geometry(isi, pix->width, pix->height, xlate->code);
  468. if (ret < 0)
  469. return ret;
  470. pix->width = mf.width;
  471. pix->height = mf.height;
  472. pix->field = mf.field;
  473. pix->colorspace = mf.colorspace;
  474. icd->current_fmt = xlate;
  475. dev_dbg(icd->parent, "Finally set format %dx%d\n",
  476. pix->width, pix->height);
  477. return ret;
  478. }
  479. static int isi_camera_try_fmt(struct soc_camera_device *icd,
  480. struct v4l2_format *f)
  481. {
  482. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  483. const struct soc_camera_format_xlate *xlate;
  484. struct v4l2_pix_format *pix = &f->fmt.pix;
  485. struct v4l2_mbus_framefmt mf;
  486. u32 pixfmt = pix->pixelformat;
  487. int ret;
  488. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  489. if (pixfmt && !xlate) {
  490. dev_warn(icd->parent, "Format %x not found\n", pixfmt);
  491. return -EINVAL;
  492. }
  493. /* limit to Atmel ISI hardware capabilities */
  494. if (pix->height > MAX_SUPPORT_HEIGHT)
  495. pix->height = MAX_SUPPORT_HEIGHT;
  496. if (pix->width > MAX_SUPPORT_WIDTH)
  497. pix->width = MAX_SUPPORT_WIDTH;
  498. /* limit to sensor capabilities */
  499. mf.width = pix->width;
  500. mf.height = pix->height;
  501. mf.field = pix->field;
  502. mf.colorspace = pix->colorspace;
  503. mf.code = xlate->code;
  504. ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
  505. if (ret < 0)
  506. return ret;
  507. pix->width = mf.width;
  508. pix->height = mf.height;
  509. pix->colorspace = mf.colorspace;
  510. switch (mf.field) {
  511. case V4L2_FIELD_ANY:
  512. pix->field = V4L2_FIELD_NONE;
  513. break;
  514. case V4L2_FIELD_NONE:
  515. break;
  516. default:
  517. dev_err(icd->parent, "Field type %d unsupported.\n",
  518. mf.field);
  519. ret = -EINVAL;
  520. }
  521. return ret;
  522. }
  523. static const struct soc_mbus_pixelfmt isi_camera_formats[] = {
  524. {
  525. .fourcc = V4L2_PIX_FMT_YUYV,
  526. .name = "Packed YUV422 16 bit",
  527. .bits_per_sample = 8,
  528. .packing = SOC_MBUS_PACKING_2X8_PADHI,
  529. .order = SOC_MBUS_ORDER_LE,
  530. .layout = SOC_MBUS_LAYOUT_PACKED,
  531. },
  532. };
  533. /* This will be corrected as we get more formats */
  534. static bool isi_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
  535. {
  536. return fmt->packing == SOC_MBUS_PACKING_NONE ||
  537. (fmt->bits_per_sample == 8 &&
  538. fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
  539. (fmt->bits_per_sample > 8 &&
  540. fmt->packing == SOC_MBUS_PACKING_EXTEND16);
  541. }
  542. #define ISI_BUS_PARAM (V4L2_MBUS_MASTER | \
  543. V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
  544. V4L2_MBUS_HSYNC_ACTIVE_LOW | \
  545. V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
  546. V4L2_MBUS_VSYNC_ACTIVE_LOW | \
  547. V4L2_MBUS_PCLK_SAMPLE_RISING | \
  548. V4L2_MBUS_PCLK_SAMPLE_FALLING | \
  549. V4L2_MBUS_DATA_ACTIVE_HIGH)
  550. static int isi_camera_try_bus_param(struct soc_camera_device *icd,
  551. unsigned char buswidth)
  552. {
  553. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  554. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  555. struct atmel_isi *isi = ici->priv;
  556. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  557. unsigned long common_flags;
  558. int ret;
  559. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  560. if (!ret) {
  561. common_flags = soc_mbus_config_compatible(&cfg,
  562. ISI_BUS_PARAM);
  563. if (!common_flags) {
  564. dev_warn(icd->parent,
  565. "Flags incompatible: camera 0x%x, host 0x%x\n",
  566. cfg.flags, ISI_BUS_PARAM);
  567. return -EINVAL;
  568. }
  569. } else if (ret != -ENOIOCTLCMD) {
  570. return ret;
  571. }
  572. if ((1 << (buswidth - 1)) & isi->width_flags)
  573. return 0;
  574. return -EINVAL;
  575. }
  576. static int isi_camera_get_formats(struct soc_camera_device *icd,
  577. unsigned int idx,
  578. struct soc_camera_format_xlate *xlate)
  579. {
  580. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  581. int formats = 0, ret;
  582. /* sensor format */
  583. enum v4l2_mbus_pixelcode code;
  584. /* soc camera host format */
  585. const struct soc_mbus_pixelfmt *fmt;
  586. ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
  587. if (ret < 0)
  588. /* No more formats */
  589. return 0;
  590. fmt = soc_mbus_get_fmtdesc(code);
  591. if (!fmt) {
  592. dev_err(icd->parent,
  593. "Invalid format code #%u: %d\n", idx, code);
  594. return 0;
  595. }
  596. /* This also checks support for the requested bits-per-sample */
  597. ret = isi_camera_try_bus_param(icd, fmt->bits_per_sample);
  598. if (ret < 0) {
  599. dev_err(icd->parent,
  600. "Fail to try the bus parameters.\n");
  601. return 0;
  602. }
  603. switch (code) {
  604. case V4L2_MBUS_FMT_UYVY8_2X8:
  605. case V4L2_MBUS_FMT_VYUY8_2X8:
  606. case V4L2_MBUS_FMT_YUYV8_2X8:
  607. case V4L2_MBUS_FMT_YVYU8_2X8:
  608. formats++;
  609. if (xlate) {
  610. xlate->host_fmt = &isi_camera_formats[0];
  611. xlate->code = code;
  612. xlate++;
  613. dev_dbg(icd->parent, "Providing format %s using code %d\n",
  614. isi_camera_formats[0].name, code);
  615. }
  616. break;
  617. default:
  618. if (!isi_camera_packing_supported(fmt))
  619. return 0;
  620. if (xlate)
  621. dev_dbg(icd->parent,
  622. "Providing format %s in pass-through mode\n",
  623. fmt->name);
  624. }
  625. /* Generic pass-through */
  626. formats++;
  627. if (xlate) {
  628. xlate->host_fmt = fmt;
  629. xlate->code = code;
  630. xlate++;
  631. }
  632. return formats;
  633. }
  634. /* Called with .host_lock held */
  635. static int isi_camera_add_device(struct soc_camera_device *icd)
  636. {
  637. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  638. struct atmel_isi *isi = ici->priv;
  639. int ret;
  640. if (isi->icd)
  641. return -EBUSY;
  642. ret = clk_enable(isi->pclk);
  643. if (ret)
  644. return ret;
  645. ret = clk_enable(isi->mck);
  646. if (ret) {
  647. clk_disable(isi->pclk);
  648. return ret;
  649. }
  650. isi->icd = icd;
  651. dev_dbg(icd->parent, "Atmel ISI Camera driver attached to camera %d\n",
  652. icd->devnum);
  653. return 0;
  654. }
  655. /* Called with .host_lock held */
  656. static void isi_camera_remove_device(struct soc_camera_device *icd)
  657. {
  658. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  659. struct atmel_isi *isi = ici->priv;
  660. BUG_ON(icd != isi->icd);
  661. clk_disable(isi->mck);
  662. clk_disable(isi->pclk);
  663. isi->icd = NULL;
  664. dev_dbg(icd->parent, "Atmel ISI Camera driver detached from camera %d\n",
  665. icd->devnum);
  666. }
  667. static unsigned int isi_camera_poll(struct file *file, poll_table *pt)
  668. {
  669. struct soc_camera_device *icd = file->private_data;
  670. return vb2_poll(&icd->vb2_vidq, file, pt);
  671. }
  672. static int isi_camera_querycap(struct soc_camera_host *ici,
  673. struct v4l2_capability *cap)
  674. {
  675. strcpy(cap->driver, "atmel-isi");
  676. strcpy(cap->card, "Atmel Image Sensor Interface");
  677. cap->capabilities = (V4L2_CAP_VIDEO_CAPTURE |
  678. V4L2_CAP_STREAMING);
  679. return 0;
  680. }
  681. static int isi_camera_set_bus_param(struct soc_camera_device *icd)
  682. {
  683. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  684. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  685. struct atmel_isi *isi = ici->priv;
  686. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  687. unsigned long common_flags;
  688. int ret;
  689. u32 cfg1 = 0;
  690. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  691. if (!ret) {
  692. common_flags = soc_mbus_config_compatible(&cfg,
  693. ISI_BUS_PARAM);
  694. if (!common_flags) {
  695. dev_warn(icd->parent,
  696. "Flags incompatible: camera 0x%x, host 0x%x\n",
  697. cfg.flags, ISI_BUS_PARAM);
  698. return -EINVAL;
  699. }
  700. } else if (ret != -ENOIOCTLCMD) {
  701. return ret;
  702. } else {
  703. common_flags = ISI_BUS_PARAM;
  704. }
  705. dev_dbg(icd->parent, "Flags cam: 0x%x host: 0x%x common: 0x%lx\n",
  706. cfg.flags, ISI_BUS_PARAM, common_flags);
  707. /* Make choises, based on platform preferences */
  708. if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
  709. (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
  710. if (isi->pdata->hsync_act_low)
  711. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
  712. else
  713. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
  714. }
  715. if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
  716. (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
  717. if (isi->pdata->vsync_act_low)
  718. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
  719. else
  720. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
  721. }
  722. if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
  723. (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
  724. if (isi->pdata->pclk_act_falling)
  725. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
  726. else
  727. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
  728. }
  729. cfg.flags = common_flags;
  730. ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
  731. if (ret < 0 && ret != -ENOIOCTLCMD) {
  732. dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
  733. common_flags, ret);
  734. return ret;
  735. }
  736. /* set bus param for ISI */
  737. if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  738. cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
  739. if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  740. cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
  741. if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  742. cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
  743. if (isi->pdata->has_emb_sync)
  744. cfg1 |= ISI_CFG1_EMB_SYNC;
  745. if (isi->pdata->full_mode)
  746. cfg1 |= ISI_CFG1_FULL_MODE;
  747. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  748. isi_writel(isi, ISI_CFG1, cfg1);
  749. return 0;
  750. }
  751. static struct soc_camera_host_ops isi_soc_camera_host_ops = {
  752. .owner = THIS_MODULE,
  753. .add = isi_camera_add_device,
  754. .remove = isi_camera_remove_device,
  755. .set_fmt = isi_camera_set_fmt,
  756. .try_fmt = isi_camera_try_fmt,
  757. .get_formats = isi_camera_get_formats,
  758. .init_videobuf2 = isi_camera_init_videobuf,
  759. .poll = isi_camera_poll,
  760. .querycap = isi_camera_querycap,
  761. .set_bus_param = isi_camera_set_bus_param,
  762. };
  763. /* -----------------------------------------------------------------------*/
  764. static int atmel_isi_remove(struct platform_device *pdev)
  765. {
  766. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  767. struct atmel_isi *isi = container_of(soc_host,
  768. struct atmel_isi, soc_host);
  769. free_irq(isi->irq, isi);
  770. soc_camera_host_unregister(soc_host);
  771. vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
  772. dma_free_coherent(&pdev->dev,
  773. sizeof(struct fbd) * MAX_BUFFER_NUM,
  774. isi->p_fb_descriptors,
  775. isi->fb_descriptors_phys);
  776. iounmap(isi->regs);
  777. clk_unprepare(isi->mck);
  778. clk_put(isi->mck);
  779. clk_unprepare(isi->pclk);
  780. clk_put(isi->pclk);
  781. kfree(isi);
  782. return 0;
  783. }
  784. static int atmel_isi_probe(struct platform_device *pdev)
  785. {
  786. unsigned int irq;
  787. struct atmel_isi *isi;
  788. struct clk *pclk;
  789. struct resource *regs;
  790. int ret, i;
  791. struct device *dev = &pdev->dev;
  792. struct soc_camera_host *soc_host;
  793. struct isi_platform_data *pdata;
  794. pdata = dev->platform_data;
  795. if (!pdata || !pdata->data_width_flags || !pdata->mck_hz) {
  796. dev_err(&pdev->dev,
  797. "No config available for Atmel ISI\n");
  798. return -EINVAL;
  799. }
  800. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  801. if (!regs)
  802. return -ENXIO;
  803. pclk = clk_get(&pdev->dev, "isi_clk");
  804. if (IS_ERR(pclk))
  805. return PTR_ERR(pclk);
  806. ret = clk_prepare(pclk);
  807. if (ret)
  808. goto err_clk_prepare_pclk;
  809. isi = kzalloc(sizeof(struct atmel_isi), GFP_KERNEL);
  810. if (!isi) {
  811. ret = -ENOMEM;
  812. dev_err(&pdev->dev, "Can't allocate interface!\n");
  813. goto err_alloc_isi;
  814. }
  815. isi->pclk = pclk;
  816. isi->pdata = pdata;
  817. isi->active = NULL;
  818. spin_lock_init(&isi->lock);
  819. init_waitqueue_head(&isi->vsync_wq);
  820. INIT_LIST_HEAD(&isi->video_buffer_list);
  821. INIT_LIST_HEAD(&isi->dma_desc_head);
  822. /* Get ISI_MCK, provided by programmable clock or external clock */
  823. isi->mck = clk_get(dev, "isi_mck");
  824. if (IS_ERR(isi->mck)) {
  825. dev_err(dev, "Failed to get isi_mck\n");
  826. ret = PTR_ERR(isi->mck);
  827. goto err_clk_get;
  828. }
  829. ret = clk_prepare(isi->mck);
  830. if (ret)
  831. goto err_clk_prepare_mck;
  832. /* Set ISI_MCK's frequency, it should be faster than pixel clock */
  833. ret = clk_set_rate(isi->mck, pdata->mck_hz);
  834. if (ret < 0)
  835. goto err_set_mck_rate;
  836. isi->p_fb_descriptors = dma_alloc_coherent(&pdev->dev,
  837. sizeof(struct fbd) * MAX_BUFFER_NUM,
  838. &isi->fb_descriptors_phys,
  839. GFP_KERNEL);
  840. if (!isi->p_fb_descriptors) {
  841. ret = -ENOMEM;
  842. dev_err(&pdev->dev, "Can't allocate descriptors!\n");
  843. goto err_alloc_descriptors;
  844. }
  845. for (i = 0; i < MAX_BUFFER_NUM; i++) {
  846. isi->dma_desc[i].p_fbd = isi->p_fb_descriptors + i;
  847. isi->dma_desc[i].fbd_phys = isi->fb_descriptors_phys +
  848. i * sizeof(struct fbd);
  849. list_add(&isi->dma_desc[i].list, &isi->dma_desc_head);
  850. }
  851. isi->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  852. if (IS_ERR(isi->alloc_ctx)) {
  853. ret = PTR_ERR(isi->alloc_ctx);
  854. goto err_alloc_ctx;
  855. }
  856. isi->regs = ioremap(regs->start, resource_size(regs));
  857. if (!isi->regs) {
  858. ret = -ENOMEM;
  859. goto err_ioremap;
  860. }
  861. if (pdata->data_width_flags & ISI_DATAWIDTH_8)
  862. isi->width_flags = 1 << 7;
  863. if (pdata->data_width_flags & ISI_DATAWIDTH_10)
  864. isi->width_flags |= 1 << 9;
  865. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  866. irq = platform_get_irq(pdev, 0);
  867. if (IS_ERR_VALUE(irq)) {
  868. ret = irq;
  869. goto err_req_irq;
  870. }
  871. ret = request_irq(irq, isi_interrupt, 0, "isi", isi);
  872. if (ret) {
  873. dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
  874. goto err_req_irq;
  875. }
  876. isi->irq = irq;
  877. soc_host = &isi->soc_host;
  878. soc_host->drv_name = "isi-camera";
  879. soc_host->ops = &isi_soc_camera_host_ops;
  880. soc_host->priv = isi;
  881. soc_host->v4l2_dev.dev = &pdev->dev;
  882. soc_host->nr = pdev->id;
  883. ret = soc_camera_host_register(soc_host);
  884. if (ret) {
  885. dev_err(&pdev->dev, "Unable to register soc camera host\n");
  886. goto err_register_soc_camera_host;
  887. }
  888. return 0;
  889. err_register_soc_camera_host:
  890. free_irq(isi->irq, isi);
  891. err_req_irq:
  892. iounmap(isi->regs);
  893. err_ioremap:
  894. vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
  895. err_alloc_ctx:
  896. dma_free_coherent(&pdev->dev,
  897. sizeof(struct fbd) * MAX_BUFFER_NUM,
  898. isi->p_fb_descriptors,
  899. isi->fb_descriptors_phys);
  900. err_alloc_descriptors:
  901. err_set_mck_rate:
  902. clk_unprepare(isi->mck);
  903. err_clk_prepare_mck:
  904. clk_put(isi->mck);
  905. err_clk_get:
  906. kfree(isi);
  907. err_alloc_isi:
  908. clk_unprepare(pclk);
  909. err_clk_prepare_pclk:
  910. clk_put(pclk);
  911. return ret;
  912. }
  913. static struct platform_driver atmel_isi_driver = {
  914. .remove = atmel_isi_remove,
  915. .driver = {
  916. .name = "atmel_isi",
  917. .owner = THIS_MODULE,
  918. },
  919. };
  920. module_platform_driver_probe(atmel_isi_driver, atmel_isi_probe);
  921. MODULE_AUTHOR("Josh Wu <josh.wu@atmel.com>");
  922. MODULE_DESCRIPTION("The V4L2 driver for Atmel Linux");
  923. MODULE_LICENSE("GPL");
  924. MODULE_SUPPORTED_DEVICE("video");