Kconfig 9.6 KB

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  1. #
  2. # DMA engine configuration
  3. #
  4. menuconfig DMADEVICES
  5. bool "DMA Engine support"
  6. depends on HAS_DMA
  7. help
  8. DMA engines can do asynchronous data transfers without
  9. involving the host CPU. Currently, this framework can be
  10. used to offload memory copies in the network stack and
  11. RAID operations in the MD driver. This menu only presents
  12. DMA Device drivers supported by the configured arch, it may
  13. be empty in some cases.
  14. config DMADEVICES_DEBUG
  15. bool "DMA Engine debugging"
  16. depends on DMADEVICES != n
  17. help
  18. This is an option for use by developers; most people should
  19. say N here. This enables DMA engine core and driver debugging.
  20. config DMADEVICES_VDEBUG
  21. bool "DMA Engine verbose debugging"
  22. depends on DMADEVICES_DEBUG != n
  23. help
  24. This is an option for use by developers; most people should
  25. say N here. This enables deeper (more verbose) debugging of
  26. the DMA engine core and drivers.
  27. if DMADEVICES
  28. comment "DMA Devices"
  29. config INTEL_MID_DMAC
  30. tristate "Intel MID DMA support for Peripheral DMA controllers"
  31. depends on PCI && X86
  32. select DMA_ENGINE
  33. default n
  34. help
  35. Enable support for the Intel(R) MID DMA engine present
  36. in Intel MID chipsets.
  37. Say Y here if you have such a chipset.
  38. If unsure, say N.
  39. config ASYNC_TX_ENABLE_CHANNEL_SWITCH
  40. bool
  41. config AMBA_PL08X
  42. bool "ARM PrimeCell PL080 or PL081 support"
  43. depends on ARM_AMBA
  44. select DMA_ENGINE
  45. select DMA_VIRTUAL_CHANNELS
  46. help
  47. Platform has a PL08x DMAC device
  48. which can provide DMA engine support
  49. config INTEL_IOATDMA
  50. tristate "Intel I/OAT DMA support"
  51. depends on PCI && X86
  52. select DMA_ENGINE
  53. select DCA
  54. select ASYNC_TX_DISABLE_PQ_VAL_DMA
  55. select ASYNC_TX_DISABLE_XOR_VAL_DMA
  56. help
  57. Enable support for the Intel(R) I/OAT DMA engine present
  58. in recent Intel Xeon chipsets.
  59. Say Y here if you have such a chipset.
  60. If unsure, say N.
  61. config INTEL_IOP_ADMA
  62. tristate "Intel IOP ADMA support"
  63. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
  64. select DMA_ENGINE
  65. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  66. help
  67. Enable support for the Intel(R) IOP Series RAID engines.
  68. config DW_DMAC
  69. tristate "Synopsys DesignWare AHB DMA support"
  70. depends on GENERIC_HARDIRQS
  71. select DMA_ENGINE
  72. default y if CPU_AT32AP7000
  73. help
  74. Support the Synopsys DesignWare AHB DMA controller. This
  75. can be integrated in chips such as the Atmel AT32ap7000.
  76. config DW_DMAC_BIG_ENDIAN_IO
  77. bool "Use big endian I/O register access"
  78. default y if AVR32
  79. depends on DW_DMAC
  80. help
  81. Say yes here to use big endian I/O access when reading and writing
  82. to the DMA controller registers. This is needed on some platforms,
  83. like the Atmel AVR32 architecture.
  84. If unsure, use the default setting.
  85. config AT_HDMAC
  86. tristate "Atmel AHB DMA support"
  87. depends on ARCH_AT91
  88. select DMA_ENGINE
  89. help
  90. Support the Atmel AHB DMA controller.
  91. config FSL_DMA
  92. tristate "Freescale Elo and Elo Plus DMA support"
  93. depends on FSL_SOC
  94. select DMA_ENGINE
  95. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  96. ---help---
  97. Enable support for the Freescale Elo and Elo Plus DMA controllers.
  98. The Elo is the DMA controller on some 82xx and 83xx parts, and the
  99. Elo Plus is the DMA controller on 85xx and 86xx parts.
  100. config MPC512X_DMA
  101. tristate "Freescale MPC512x built-in DMA engine support"
  102. depends on PPC_MPC512x || PPC_MPC831x
  103. select DMA_ENGINE
  104. ---help---
  105. Enable support for the Freescale MPC512x built-in DMA engine.
  106. source "drivers/dma/bestcomm/Kconfig"
  107. config MV_XOR
  108. bool "Marvell XOR engine support"
  109. depends on PLAT_ORION
  110. select DMA_ENGINE
  111. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  112. ---help---
  113. Enable support for the Marvell XOR engine.
  114. config MX3_IPU
  115. bool "MX3x Image Processing Unit support"
  116. depends on ARCH_MXC
  117. select DMA_ENGINE
  118. default y
  119. help
  120. If you plan to use the Image Processing unit in the i.MX3x, say
  121. Y here. If unsure, select Y.
  122. config MX3_IPU_IRQS
  123. int "Number of dynamically mapped interrupts for IPU"
  124. depends on MX3_IPU
  125. range 2 137
  126. default 4
  127. help
  128. Out of 137 interrupt sources on i.MX31 IPU only very few are used.
  129. To avoid bloating the irq_desc[] array we allocate a sufficient
  130. number of IRQ slots and map them dynamically to specific sources.
  131. config TXX9_DMAC
  132. tristate "Toshiba TXx9 SoC DMA support"
  133. depends on MACH_TX49XX || MACH_TX39XX
  134. select DMA_ENGINE
  135. help
  136. Support the TXx9 SoC internal DMA controller. This can be
  137. integrated in chips such as the Toshiba TX4927/38/39.
  138. config TEGRA20_APB_DMA
  139. bool "NVIDIA Tegra20 APB DMA support"
  140. depends on ARCH_TEGRA
  141. select DMA_ENGINE
  142. help
  143. Support for the NVIDIA Tegra20 APB DMA controller driver. The
  144. DMA controller is having multiple DMA channel which can be
  145. configured for different peripherals like audio, UART, SPI,
  146. I2C etc which is in APB bus.
  147. This DMA controller transfers data from memory to peripheral fifo
  148. or vice versa. It does not support memory to memory data transfer.
  149. config SH_DMAE
  150. tristate "Renesas SuperH DMAC support"
  151. depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
  152. depends on !SH_DMA_API
  153. select DMA_ENGINE
  154. help
  155. Enable support for the Renesas SuperH DMA controllers.
  156. config COH901318
  157. bool "ST-Ericsson COH901318 DMA support"
  158. select DMA_ENGINE
  159. depends on ARCH_U300
  160. help
  161. Enable support for ST-Ericsson COH 901 318 DMA.
  162. config STE_DMA40
  163. bool "ST-Ericsson DMA40 support"
  164. depends on ARCH_U8500
  165. select DMA_ENGINE
  166. help
  167. Support for ST-Ericsson DMA40 controller
  168. config AMCC_PPC440SPE_ADMA
  169. tristate "AMCC PPC440SPe ADMA support"
  170. depends on 440SPe || 440SP
  171. select DMA_ENGINE
  172. select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  173. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  174. help
  175. Enable support for the AMCC PPC440SPe RAID engines.
  176. config TIMB_DMA
  177. tristate "Timberdale FPGA DMA support"
  178. depends on MFD_TIMBERDALE || HAS_IOMEM
  179. select DMA_ENGINE
  180. help
  181. Enable support for the Timberdale FPGA DMA engine.
  182. config SIRF_DMA
  183. tristate "CSR SiRFprimaII/SiRFmarco DMA support"
  184. depends on ARCH_SIRF
  185. select DMA_ENGINE
  186. help
  187. Enable support for the CSR SiRFprimaII DMA engine.
  188. config TI_EDMA
  189. tristate "TI EDMA support"
  190. depends on ARCH_DAVINCI
  191. select DMA_ENGINE
  192. select DMA_VIRTUAL_CHANNELS
  193. default n
  194. help
  195. Enable support for the TI EDMA controller. This DMA
  196. engine is found on TI DaVinci and AM33xx parts.
  197. config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  198. bool
  199. config PL330_DMA
  200. tristate "DMA API Driver for PL330"
  201. select DMA_ENGINE
  202. depends on ARM_AMBA
  203. help
  204. Select if your platform has one or more PL330 DMACs.
  205. You need to provide platform specific settings via
  206. platform_data for a dma-pl330 device.
  207. config PCH_DMA
  208. tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
  209. depends on PCI && X86
  210. select DMA_ENGINE
  211. help
  212. Enable support for Intel EG20T PCH DMA engine.
  213. This driver also can be used for LAPIS Semiconductor IOH(Input/
  214. Output Hub), ML7213, ML7223 and ML7831.
  215. ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
  216. for MP(Media Phone) use and ML7831 IOH is for general purpose use.
  217. ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
  218. ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
  219. config IMX_SDMA
  220. tristate "i.MX SDMA support"
  221. depends on ARCH_MXC
  222. select DMA_ENGINE
  223. help
  224. Support the i.MX SDMA engine. This engine is integrated into
  225. Freescale i.MX25/31/35/51/53 chips.
  226. config IMX_DMA
  227. tristate "i.MX DMA support"
  228. depends on ARCH_MXC
  229. select DMA_ENGINE
  230. help
  231. Support the i.MX DMA engine. This engine is integrated into
  232. Freescale i.MX1/21/27 chips.
  233. config MXS_DMA
  234. bool "MXS DMA support"
  235. depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
  236. select STMP_DEVICE
  237. select DMA_ENGINE
  238. help
  239. Support the MXS DMA engine. This engine including APBH-DMA
  240. and APBX-DMA is integrated into Freescale i.MX23/28 chips.
  241. config EP93XX_DMA
  242. bool "Cirrus Logic EP93xx DMA support"
  243. depends on ARCH_EP93XX
  244. select DMA_ENGINE
  245. help
  246. Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
  247. config DMA_SA11X0
  248. tristate "SA-11x0 DMA support"
  249. depends on ARCH_SA1100
  250. select DMA_ENGINE
  251. select DMA_VIRTUAL_CHANNELS
  252. help
  253. Support the DMA engine found on Intel StrongARM SA-1100 and
  254. SA-1110 SoCs. This DMA engine can only be used with on-chip
  255. devices.
  256. config MMP_TDMA
  257. bool "MMP Two-Channel DMA support"
  258. depends on ARCH_MMP
  259. select DMA_ENGINE
  260. help
  261. Support the MMP Two-Channel DMA engine.
  262. This engine used for MMP Audio DMA and pxa910 SQU.
  263. Say Y here if you enabled MMP ADMA, otherwise say N.
  264. config DMA_OMAP
  265. tristate "OMAP DMA support"
  266. depends on ARCH_OMAP
  267. select DMA_ENGINE
  268. select DMA_VIRTUAL_CHANNELS
  269. config MMP_PDMA
  270. bool "MMP PDMA support"
  271. depends on (ARCH_MMP || ARCH_PXA)
  272. select DMA_ENGINE
  273. help
  274. Support the MMP PDMA engine for PXA and MMP platfrom.
  275. config DMA_ENGINE
  276. bool
  277. config DMA_VIRTUAL_CHANNELS
  278. tristate
  279. config DMA_OF
  280. def_bool y
  281. depends on OF
  282. comment "DMA Clients"
  283. depends on DMA_ENGINE
  284. config NET_DMA
  285. bool "Network: TCP receive copy offload"
  286. depends on DMA_ENGINE && NET
  287. default (INTEL_IOATDMA || FSL_DMA)
  288. help
  289. This enables the use of DMA engines in the network stack to
  290. offload receive copy-to-user operations, freeing CPU cycles.
  291. Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
  292. say N.
  293. config ASYNC_TX_DMA
  294. bool "Async_tx: Offload support for the async_tx api"
  295. depends on DMA_ENGINE
  296. help
  297. This allows the async_tx api to take advantage of offload engines for
  298. memcpy, memset, xor, and raid6 p+q operations. If your platform has
  299. a dma engine that can perform raid operations and you have enabled
  300. MD_RAID456 say Y.
  301. If unsure, say N.
  302. config DMATEST
  303. tristate "DMA Test client"
  304. depends on DMA_ENGINE
  305. help
  306. Simple DMA test client. Say N unless you're debugging a
  307. DMA Device driver.
  308. endif