pci_insn.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202
  1. /*
  2. * s390 specific pci instructions
  3. *
  4. * Copyright IBM Corp. 2013
  5. */
  6. #include <linux/export.h>
  7. #include <linux/errno.h>
  8. #include <linux/delay.h>
  9. #include <asm/pci_insn.h>
  10. #include <asm/processor.h>
  11. #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
  12. /* Modify PCI Function Controls */
  13. static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
  14. {
  15. u8 cc;
  16. asm volatile (
  17. " .insn rxy,0xe300000000d0,%[req],%[fib]\n"
  18. " ipm %[cc]\n"
  19. " srl %[cc],28\n"
  20. : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
  21. : : "cc");
  22. *status = req >> 24 & 0xff;
  23. return cc;
  24. }
  25. int s390pci_mod_fc(u64 req, struct zpci_fib *fib)
  26. {
  27. u8 cc, status;
  28. do {
  29. cc = __mpcifc(req, fib, &status);
  30. if (cc == 2)
  31. msleep(ZPCI_INSN_BUSY_DELAY);
  32. } while (cc == 2);
  33. if (cc)
  34. printk_once(KERN_ERR "%s: error cc: %d status: %d\n",
  35. __func__, cc, status);
  36. return (cc) ? -EIO : 0;
  37. }
  38. /* Refresh PCI Translations */
  39. static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
  40. {
  41. register u64 __addr asm("2") = addr;
  42. register u64 __range asm("3") = range;
  43. u8 cc;
  44. asm volatile (
  45. " .insn rre,0xb9d30000,%[fn],%[addr]\n"
  46. " ipm %[cc]\n"
  47. " srl %[cc],28\n"
  48. : [cc] "=d" (cc), [fn] "+d" (fn)
  49. : [addr] "d" (__addr), "d" (__range)
  50. : "cc");
  51. *status = fn >> 24 & 0xff;
  52. return cc;
  53. }
  54. int s390pci_refresh_trans(u64 fn, u64 addr, u64 range)
  55. {
  56. u8 cc, status;
  57. do {
  58. cc = __rpcit(fn, addr, range, &status);
  59. if (cc == 2)
  60. udelay(ZPCI_INSN_BUSY_DELAY);
  61. } while (cc == 2);
  62. if (cc)
  63. printk_once(KERN_ERR "%s: error cc: %d status: %d dma_addr: %Lx size: %Lx\n",
  64. __func__, cc, status, addr, range);
  65. return (cc) ? -EIO : 0;
  66. }
  67. /* Set Interruption Controls */
  68. void set_irq_ctrl(u16 ctl, char *unused, u8 isc)
  69. {
  70. asm volatile (
  71. " .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
  72. : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
  73. }
  74. /* PCI Load */
  75. static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
  76. {
  77. register u64 __req asm("2") = req;
  78. register u64 __offset asm("3") = offset;
  79. int cc = -ENXIO;
  80. u64 __data;
  81. asm volatile (
  82. " .insn rre,0xb9d20000,%[data],%[req]\n"
  83. "0: ipm %[cc]\n"
  84. " srl %[cc],28\n"
  85. "1:\n"
  86. EX_TABLE(0b, 1b)
  87. : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
  88. : "d" (__offset)
  89. : "cc");
  90. *status = __req >> 24 & 0xff;
  91. if (!cc)
  92. *data = __data;
  93. return cc;
  94. }
  95. int s390pci_load(u64 *data, u64 req, u64 offset)
  96. {
  97. u8 status;
  98. int cc;
  99. do {
  100. cc = __pcilg(data, req, offset, &status);
  101. if (cc == 2)
  102. udelay(ZPCI_INSN_BUSY_DELAY);
  103. } while (cc == 2);
  104. if (cc)
  105. printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
  106. __func__, cc, status, req, offset);
  107. return (cc > 0) ? -EIO : cc;
  108. }
  109. EXPORT_SYMBOL_GPL(s390pci_load);
  110. /* PCI Store */
  111. static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
  112. {
  113. register u64 __req asm("2") = req;
  114. register u64 __offset asm("3") = offset;
  115. int cc = -ENXIO;
  116. asm volatile (
  117. " .insn rre,0xb9d00000,%[data],%[req]\n"
  118. "0: ipm %[cc]\n"
  119. " srl %[cc],28\n"
  120. "1:\n"
  121. EX_TABLE(0b, 1b)
  122. : [cc] "+d" (cc), [req] "+d" (__req)
  123. : "d" (__offset), [data] "d" (data)
  124. : "cc");
  125. *status = __req >> 24 & 0xff;
  126. return cc;
  127. }
  128. int s390pci_store(u64 data, u64 req, u64 offset)
  129. {
  130. u8 status;
  131. int cc;
  132. do {
  133. cc = __pcistg(data, req, offset, &status);
  134. if (cc == 2)
  135. udelay(ZPCI_INSN_BUSY_DELAY);
  136. } while (cc == 2);
  137. if (cc)
  138. printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
  139. __func__, cc, status, req, offset);
  140. return (cc > 0) ? -EIO : cc;
  141. }
  142. EXPORT_SYMBOL_GPL(s390pci_store);
  143. /* PCI Store Block */
  144. static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
  145. {
  146. int cc = -ENXIO;
  147. asm volatile (
  148. " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
  149. "0: ipm %[cc]\n"
  150. " srl %[cc],28\n"
  151. "1:\n"
  152. EX_TABLE(0b, 1b)
  153. : [cc] "+d" (cc), [req] "+d" (req)
  154. : [offset] "d" (offset), [data] "Q" (*data)
  155. : "cc");
  156. *status = req >> 24 & 0xff;
  157. return cc;
  158. }
  159. int s390pci_store_block(const u64 *data, u64 req, u64 offset)
  160. {
  161. u8 status;
  162. int cc;
  163. do {
  164. cc = __pcistb(data, req, offset, &status);
  165. if (cc == 2)
  166. udelay(ZPCI_INSN_BUSY_DELAY);
  167. } while (cc == 2);
  168. if (cc)
  169. printk_once(KERN_ERR "%s: error cc: %d status: %d req: %Lx offset: %Lx\n",
  170. __func__, cc, status, req, offset);
  171. return (cc > 0) ? -EIO : cc;
  172. }
  173. EXPORT_SYMBOL_GPL(s390pci_store_block);