hugetlb.h 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. #ifndef _ASM_POWERPC_HUGETLB_H
  2. #define _ASM_POWERPC_HUGETLB_H
  3. #ifdef CONFIG_HUGETLB_PAGE
  4. #include <asm/page.h>
  5. #include <asm-generic/hugetlb.h>
  6. extern struct kmem_cache *hugepte_cache;
  7. static inline pte_t *hugepd_page(hugepd_t hpd)
  8. {
  9. BUG_ON(!hugepd_ok(hpd));
  10. return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
  11. }
  12. static inline unsigned int hugepd_shift(hugepd_t hpd)
  13. {
  14. return hpd.pd & HUGEPD_SHIFT_MASK;
  15. }
  16. static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
  17. unsigned pdshift)
  18. {
  19. /*
  20. * On FSL BookE, we have multiple higher-level table entries that
  21. * point to the same hugepte. Just use the first one since they're all
  22. * identical. So for that case, idx=0.
  23. */
  24. unsigned long idx = 0;
  25. pte_t *dir = hugepd_page(*hpdp);
  26. #ifndef CONFIG_PPC_FSL_BOOK3E
  27. idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
  28. #endif
  29. return dir + idx;
  30. }
  31. pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
  32. unsigned long addr, unsigned *shift);
  33. void flush_dcache_icache_hugepage(struct page *page);
  34. #if defined(CONFIG_PPC_MM_SLICES) || defined(CONFIG_PPC_SUBPAGE_PROT)
  35. int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
  36. unsigned long len);
  37. #else
  38. static inline int is_hugepage_only_range(struct mm_struct *mm,
  39. unsigned long addr,
  40. unsigned long len)
  41. {
  42. return 0;
  43. }
  44. #endif
  45. void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
  46. pte_t pte);
  47. void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
  48. void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
  49. unsigned long end, unsigned long floor,
  50. unsigned long ceiling);
  51. /*
  52. * The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs
  53. * to override the version in mm/hugetlb.c
  54. */
  55. #define vma_mmu_pagesize vma_mmu_pagesize
  56. /*
  57. * If the arch doesn't supply something else, assume that hugepage
  58. * size aligned regions are ok without further preparation.
  59. */
  60. static inline int prepare_hugepage_range(struct file *file,
  61. unsigned long addr, unsigned long len)
  62. {
  63. struct hstate *h = hstate_file(file);
  64. if (len & ~huge_page_mask(h))
  65. return -EINVAL;
  66. if (addr & ~huge_page_mask(h))
  67. return -EINVAL;
  68. return 0;
  69. }
  70. static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
  71. {
  72. }
  73. static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
  74. pte_t *ptep, pte_t pte)
  75. {
  76. set_pte_at(mm, addr, ptep, pte);
  77. }
  78. static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
  79. unsigned long addr, pte_t *ptep)
  80. {
  81. #ifdef CONFIG_PPC64
  82. return __pte(pte_update(mm, addr, ptep, ~0UL, 1));
  83. #else
  84. return __pte(pte_update(ptep, ~0UL, 0));
  85. #endif
  86. }
  87. static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
  88. unsigned long addr, pte_t *ptep)
  89. {
  90. pte_t pte;
  91. pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
  92. flush_tlb_page(vma, addr);
  93. }
  94. static inline int huge_pte_none(pte_t pte)
  95. {
  96. return pte_none(pte);
  97. }
  98. static inline pte_t huge_pte_wrprotect(pte_t pte)
  99. {
  100. return pte_wrprotect(pte);
  101. }
  102. static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
  103. unsigned long addr, pte_t *ptep,
  104. pte_t pte, int dirty)
  105. {
  106. #ifdef HUGETLB_NEED_PRELOAD
  107. /*
  108. * The "return 1" forces a call of update_mmu_cache, which will write a
  109. * TLB entry. Without this, platforms that don't do a write of the TLB
  110. * entry in the TLB miss handler asm will fault ad infinitum.
  111. */
  112. ptep_set_access_flags(vma, addr, ptep, pte, dirty);
  113. return 1;
  114. #else
  115. return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
  116. #endif
  117. }
  118. static inline pte_t huge_ptep_get(pte_t *ptep)
  119. {
  120. return *ptep;
  121. }
  122. static inline int arch_prepare_hugepage(struct page *page)
  123. {
  124. return 0;
  125. }
  126. static inline void arch_release_hugepage(struct page *page)
  127. {
  128. }
  129. static inline void arch_clear_hugepage_flags(struct page *page)
  130. {
  131. }
  132. #else /* ! CONFIG_HUGETLB_PAGE */
  133. static inline void flush_hugetlb_page(struct vm_area_struct *vma,
  134. unsigned long vmaddr)
  135. {
  136. }
  137. #endif /* CONFIG_HUGETLB_PAGE */
  138. /*
  139. * FSL Book3E platforms require special gpage handling - the gpages
  140. * are reserved early in the boot process by memblock instead of via
  141. * the .dts as on IBM platforms.
  142. */
  143. #if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
  144. extern void __init reserve_hugetlb_gpages(void);
  145. #else
  146. static inline void reserve_hugetlb_gpages(void)
  147. {
  148. }
  149. #endif
  150. #endif /* _ASM_POWERPC_HUGETLB_H */