devs.c 39 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/amba/pl330.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/slab.h>
  23. #include <linux/string.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/fb.h>
  26. #include <linux/gfp.h>
  27. #include <linux/mtd/mtd.h>
  28. #include <linux/mtd/onenand.h>
  29. #include <linux/mtd/partitions.h>
  30. #include <linux/mmc/host.h>
  31. #include <linux/ioport.h>
  32. #include <linux/platform_data/s3c-hsudc.h>
  33. #include <linux/platform_data/s3c-hsotg.h>
  34. #include <media/s5p_hdmi.h>
  35. #include <asm/irq.h>
  36. #include <asm/mach/arch.h>
  37. #include <asm/mach/map.h>
  38. #include <asm/mach/irq.h>
  39. #include <mach/hardware.h>
  40. #include <mach/dma.h>
  41. #include <mach/irqs.h>
  42. #include <mach/map.h>
  43. #include <plat/cpu.h>
  44. #include <plat/devs.h>
  45. #include <plat/adc.h>
  46. #include <linux/platform_data/ata-samsung_cf.h>
  47. #include <linux/platform_data/usb-ehci-s5p.h>
  48. #include <plat/fb.h>
  49. #include <plat/fb-s3c2410.h>
  50. #include <plat/hdmi.h>
  51. #include <linux/platform_data/hwmon-s3c.h>
  52. #include <linux/platform_data/i2c-s3c2410.h>
  53. #include <plat/keypad.h>
  54. #include <linux/platform_data/mmc-s3cmci.h>
  55. #include <linux/platform_data/mtd-nand-s3c2410.h>
  56. #include <plat/sdhci.h>
  57. #include <linux/platform_data/touchscreen-s3c2410.h>
  58. #include <linux/platform_data/usb-s3c2410_udc.h>
  59. #include <linux/platform_data/usb-ohci-s3c2410.h>
  60. #include <plat/usb-phy.h>
  61. #include <plat/regs-iic.h>
  62. #include <plat/regs-serial.h>
  63. #include <plat/regs-spi.h>
  64. #include <linux/platform_data/spi-s3c64xx.h>
  65. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  66. /* AC97 */
  67. #ifdef CONFIG_CPU_S3C2440
  68. static struct resource s3c_ac97_resource[] = {
  69. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  70. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  71. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  72. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  73. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  74. };
  75. struct platform_device s3c_device_ac97 = {
  76. .name = "samsung-ac97",
  77. .id = -1,
  78. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  79. .resource = s3c_ac97_resource,
  80. .dev = {
  81. .dma_mask = &samsung_device_dma_mask,
  82. .coherent_dma_mask = DMA_BIT_MASK(32),
  83. }
  84. };
  85. #endif /* CONFIG_CPU_S3C2440 */
  86. /* ADC */
  87. #ifdef CONFIG_PLAT_S3C24XX
  88. static struct resource s3c_adc_resource[] = {
  89. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  90. [1] = DEFINE_RES_IRQ(IRQ_TC),
  91. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  92. };
  93. struct platform_device s3c_device_adc = {
  94. .name = "s3c24xx-adc",
  95. .id = -1,
  96. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  97. .resource = s3c_adc_resource,
  98. };
  99. #endif /* CONFIG_PLAT_S3C24XX */
  100. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  101. static struct resource s3c_adc_resource[] = {
  102. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  103. [1] = DEFINE_RES_IRQ(IRQ_TC),
  104. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  105. };
  106. struct platform_device s3c_device_adc = {
  107. .name = "samsung-adc",
  108. .id = -1,
  109. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  110. .resource = s3c_adc_resource,
  111. };
  112. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  113. /* Camif Controller */
  114. #ifdef CONFIG_CPU_S3C2440
  115. static struct resource s3c_camif_resource[] = {
  116. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  117. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  118. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  119. };
  120. struct platform_device s3c_device_camif = {
  121. .name = "s3c2440-camif",
  122. .id = -1,
  123. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  124. .resource = s3c_camif_resource,
  125. .dev = {
  126. .dma_mask = &samsung_device_dma_mask,
  127. .coherent_dma_mask = DMA_BIT_MASK(32),
  128. }
  129. };
  130. #endif /* CONFIG_CPU_S3C2440 */
  131. /* ASOC DMA */
  132. struct platform_device samsung_asoc_idma = {
  133. .name = "samsung-idma",
  134. .id = -1,
  135. .dev = {
  136. .dma_mask = &samsung_device_dma_mask,
  137. .coherent_dma_mask = DMA_BIT_MASK(32),
  138. }
  139. };
  140. /* FB */
  141. #ifdef CONFIG_S3C_DEV_FB
  142. static struct resource s3c_fb_resource[] = {
  143. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  144. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  145. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  146. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  147. };
  148. struct platform_device s3c_device_fb = {
  149. .name = "s3c-fb",
  150. .id = -1,
  151. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  152. .resource = s3c_fb_resource,
  153. .dev = {
  154. .dma_mask = &samsung_device_dma_mask,
  155. .coherent_dma_mask = DMA_BIT_MASK(32),
  156. },
  157. };
  158. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  159. {
  160. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  161. &s3c_device_fb);
  162. }
  163. #endif /* CONFIG_S3C_DEV_FB */
  164. /* FIMC */
  165. #ifdef CONFIG_S5P_DEV_FIMC0
  166. static struct resource s5p_fimc0_resource[] = {
  167. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  168. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  169. };
  170. struct platform_device s5p_device_fimc0 = {
  171. .name = "s5p-fimc",
  172. .id = 0,
  173. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  174. .resource = s5p_fimc0_resource,
  175. .dev = {
  176. .dma_mask = &samsung_device_dma_mask,
  177. .coherent_dma_mask = DMA_BIT_MASK(32),
  178. },
  179. };
  180. struct platform_device s5p_device_fimc_md = {
  181. .name = "s5p-fimc-md",
  182. .id = -1,
  183. };
  184. #endif /* CONFIG_S5P_DEV_FIMC0 */
  185. #ifdef CONFIG_S5P_DEV_FIMC1
  186. static struct resource s5p_fimc1_resource[] = {
  187. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  188. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  189. };
  190. struct platform_device s5p_device_fimc1 = {
  191. .name = "s5p-fimc",
  192. .id = 1,
  193. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  194. .resource = s5p_fimc1_resource,
  195. .dev = {
  196. .dma_mask = &samsung_device_dma_mask,
  197. .coherent_dma_mask = DMA_BIT_MASK(32),
  198. },
  199. };
  200. #endif /* CONFIG_S5P_DEV_FIMC1 */
  201. #ifdef CONFIG_S5P_DEV_FIMC2
  202. static struct resource s5p_fimc2_resource[] = {
  203. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  204. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  205. };
  206. struct platform_device s5p_device_fimc2 = {
  207. .name = "s5p-fimc",
  208. .id = 2,
  209. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  210. .resource = s5p_fimc2_resource,
  211. .dev = {
  212. .dma_mask = &samsung_device_dma_mask,
  213. .coherent_dma_mask = DMA_BIT_MASK(32),
  214. },
  215. };
  216. #endif /* CONFIG_S5P_DEV_FIMC2 */
  217. #ifdef CONFIG_S5P_DEV_FIMC3
  218. static struct resource s5p_fimc3_resource[] = {
  219. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  220. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  221. };
  222. struct platform_device s5p_device_fimc3 = {
  223. .name = "s5p-fimc",
  224. .id = 3,
  225. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  226. .resource = s5p_fimc3_resource,
  227. .dev = {
  228. .dma_mask = &samsung_device_dma_mask,
  229. .coherent_dma_mask = DMA_BIT_MASK(32),
  230. },
  231. };
  232. #endif /* CONFIG_S5P_DEV_FIMC3 */
  233. /* G2D */
  234. #ifdef CONFIG_S5P_DEV_G2D
  235. static struct resource s5p_g2d_resource[] = {
  236. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  237. [1] = DEFINE_RES_IRQ(IRQ_2D),
  238. };
  239. struct platform_device s5p_device_g2d = {
  240. .name = "s5p-g2d",
  241. .id = 0,
  242. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  243. .resource = s5p_g2d_resource,
  244. .dev = {
  245. .dma_mask = &samsung_device_dma_mask,
  246. .coherent_dma_mask = DMA_BIT_MASK(32),
  247. },
  248. };
  249. #endif /* CONFIG_S5P_DEV_G2D */
  250. #ifdef CONFIG_S5P_DEV_JPEG
  251. static struct resource s5p_jpeg_resource[] = {
  252. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  253. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  254. };
  255. struct platform_device s5p_device_jpeg = {
  256. .name = "s5p-jpeg",
  257. .id = 0,
  258. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  259. .resource = s5p_jpeg_resource,
  260. .dev = {
  261. .dma_mask = &samsung_device_dma_mask,
  262. .coherent_dma_mask = DMA_BIT_MASK(32),
  263. },
  264. };
  265. #endif /* CONFIG_S5P_DEV_JPEG */
  266. /* FIMD0 */
  267. #ifdef CONFIG_S5P_DEV_FIMD0
  268. static struct resource s5p_fimd0_resource[] = {
  269. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  270. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  271. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  272. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  273. };
  274. struct platform_device s5p_device_fimd0 = {
  275. .name = "s5p-fb",
  276. .id = 0,
  277. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  278. .resource = s5p_fimd0_resource,
  279. .dev = {
  280. .dma_mask = &samsung_device_dma_mask,
  281. .coherent_dma_mask = DMA_BIT_MASK(32),
  282. },
  283. };
  284. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  285. {
  286. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  287. &s5p_device_fimd0);
  288. }
  289. #endif /* CONFIG_S5P_DEV_FIMD0 */
  290. /* HWMON */
  291. #ifdef CONFIG_S3C_DEV_HWMON
  292. struct platform_device s3c_device_hwmon = {
  293. .name = "s3c-hwmon",
  294. .id = -1,
  295. .dev.parent = &s3c_device_adc.dev,
  296. };
  297. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  298. {
  299. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  300. &s3c_device_hwmon);
  301. }
  302. #endif /* CONFIG_S3C_DEV_HWMON */
  303. /* HSMMC */
  304. #ifdef CONFIG_S3C_DEV_HSMMC
  305. static struct resource s3c_hsmmc_resource[] = {
  306. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  307. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  308. };
  309. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  310. .max_width = 4,
  311. .host_caps = (MMC_CAP_4_BIT_DATA |
  312. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  313. };
  314. struct platform_device s3c_device_hsmmc0 = {
  315. .name = "s3c-sdhci",
  316. .id = 0,
  317. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  318. .resource = s3c_hsmmc_resource,
  319. .dev = {
  320. .dma_mask = &samsung_device_dma_mask,
  321. .coherent_dma_mask = DMA_BIT_MASK(32),
  322. .platform_data = &s3c_hsmmc0_def_platdata,
  323. },
  324. };
  325. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  326. {
  327. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  328. }
  329. #endif /* CONFIG_S3C_DEV_HSMMC */
  330. #ifdef CONFIG_S3C_DEV_HSMMC1
  331. static struct resource s3c_hsmmc1_resource[] = {
  332. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  333. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  334. };
  335. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  336. .max_width = 4,
  337. .host_caps = (MMC_CAP_4_BIT_DATA |
  338. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  339. };
  340. struct platform_device s3c_device_hsmmc1 = {
  341. .name = "s3c-sdhci",
  342. .id = 1,
  343. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  344. .resource = s3c_hsmmc1_resource,
  345. .dev = {
  346. .dma_mask = &samsung_device_dma_mask,
  347. .coherent_dma_mask = DMA_BIT_MASK(32),
  348. .platform_data = &s3c_hsmmc1_def_platdata,
  349. },
  350. };
  351. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  352. {
  353. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  354. }
  355. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  356. /* HSMMC2 */
  357. #ifdef CONFIG_S3C_DEV_HSMMC2
  358. static struct resource s3c_hsmmc2_resource[] = {
  359. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  360. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  361. };
  362. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  363. .max_width = 4,
  364. .host_caps = (MMC_CAP_4_BIT_DATA |
  365. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  366. };
  367. struct platform_device s3c_device_hsmmc2 = {
  368. .name = "s3c-sdhci",
  369. .id = 2,
  370. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  371. .resource = s3c_hsmmc2_resource,
  372. .dev = {
  373. .dma_mask = &samsung_device_dma_mask,
  374. .coherent_dma_mask = DMA_BIT_MASK(32),
  375. .platform_data = &s3c_hsmmc2_def_platdata,
  376. },
  377. };
  378. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  379. {
  380. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  381. }
  382. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  383. #ifdef CONFIG_S3C_DEV_HSMMC3
  384. static struct resource s3c_hsmmc3_resource[] = {
  385. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  386. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  387. };
  388. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  389. .max_width = 4,
  390. .host_caps = (MMC_CAP_4_BIT_DATA |
  391. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  392. };
  393. struct platform_device s3c_device_hsmmc3 = {
  394. .name = "s3c-sdhci",
  395. .id = 3,
  396. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  397. .resource = s3c_hsmmc3_resource,
  398. .dev = {
  399. .dma_mask = &samsung_device_dma_mask,
  400. .coherent_dma_mask = DMA_BIT_MASK(32),
  401. .platform_data = &s3c_hsmmc3_def_platdata,
  402. },
  403. };
  404. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  405. {
  406. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  407. }
  408. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  409. /* I2C */
  410. static struct resource s3c_i2c0_resource[] = {
  411. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  412. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  413. };
  414. struct platform_device s3c_device_i2c0 = {
  415. .name = "s3c2410-i2c",
  416. .id = 0,
  417. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  418. .resource = s3c_i2c0_resource,
  419. };
  420. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  421. .flags = 0,
  422. .slave_addr = 0x10,
  423. .frequency = 100*1000,
  424. .sda_delay = 100,
  425. };
  426. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  427. {
  428. struct s3c2410_platform_i2c *npd;
  429. if (!pd) {
  430. pd = &default_i2c_data;
  431. pd->bus_num = 0;
  432. }
  433. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  434. &s3c_device_i2c0);
  435. if (!npd->cfg_gpio)
  436. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  437. }
  438. #ifdef CONFIG_S3C_DEV_I2C1
  439. static struct resource s3c_i2c1_resource[] = {
  440. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  441. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  442. };
  443. struct platform_device s3c_device_i2c1 = {
  444. .name = "s3c2410-i2c",
  445. .id = 1,
  446. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  447. .resource = s3c_i2c1_resource,
  448. };
  449. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  450. {
  451. struct s3c2410_platform_i2c *npd;
  452. if (!pd) {
  453. pd = &default_i2c_data;
  454. pd->bus_num = 1;
  455. }
  456. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  457. &s3c_device_i2c1);
  458. if (!npd->cfg_gpio)
  459. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  460. }
  461. #endif /* CONFIG_S3C_DEV_I2C1 */
  462. #ifdef CONFIG_S3C_DEV_I2C2
  463. static struct resource s3c_i2c2_resource[] = {
  464. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  465. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  466. };
  467. struct platform_device s3c_device_i2c2 = {
  468. .name = "s3c2410-i2c",
  469. .id = 2,
  470. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  471. .resource = s3c_i2c2_resource,
  472. };
  473. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  474. {
  475. struct s3c2410_platform_i2c *npd;
  476. if (!pd) {
  477. pd = &default_i2c_data;
  478. pd->bus_num = 2;
  479. }
  480. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  481. &s3c_device_i2c2);
  482. if (!npd->cfg_gpio)
  483. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  484. }
  485. #endif /* CONFIG_S3C_DEV_I2C2 */
  486. #ifdef CONFIG_S3C_DEV_I2C3
  487. static struct resource s3c_i2c3_resource[] = {
  488. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  489. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  490. };
  491. struct platform_device s3c_device_i2c3 = {
  492. .name = "s3c2440-i2c",
  493. .id = 3,
  494. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  495. .resource = s3c_i2c3_resource,
  496. };
  497. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  498. {
  499. struct s3c2410_platform_i2c *npd;
  500. if (!pd) {
  501. pd = &default_i2c_data;
  502. pd->bus_num = 3;
  503. }
  504. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  505. &s3c_device_i2c3);
  506. if (!npd->cfg_gpio)
  507. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  508. }
  509. #endif /*CONFIG_S3C_DEV_I2C3 */
  510. #ifdef CONFIG_S3C_DEV_I2C4
  511. static struct resource s3c_i2c4_resource[] = {
  512. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  513. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  514. };
  515. struct platform_device s3c_device_i2c4 = {
  516. .name = "s3c2440-i2c",
  517. .id = 4,
  518. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  519. .resource = s3c_i2c4_resource,
  520. };
  521. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  522. {
  523. struct s3c2410_platform_i2c *npd;
  524. if (!pd) {
  525. pd = &default_i2c_data;
  526. pd->bus_num = 4;
  527. }
  528. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  529. &s3c_device_i2c4);
  530. if (!npd->cfg_gpio)
  531. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  532. }
  533. #endif /*CONFIG_S3C_DEV_I2C4 */
  534. #ifdef CONFIG_S3C_DEV_I2C5
  535. static struct resource s3c_i2c5_resource[] = {
  536. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  537. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  538. };
  539. struct platform_device s3c_device_i2c5 = {
  540. .name = "s3c2440-i2c",
  541. .id = 5,
  542. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  543. .resource = s3c_i2c5_resource,
  544. };
  545. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  546. {
  547. struct s3c2410_platform_i2c *npd;
  548. if (!pd) {
  549. pd = &default_i2c_data;
  550. pd->bus_num = 5;
  551. }
  552. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  553. &s3c_device_i2c5);
  554. if (!npd->cfg_gpio)
  555. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  556. }
  557. #endif /*CONFIG_S3C_DEV_I2C5 */
  558. #ifdef CONFIG_S3C_DEV_I2C6
  559. static struct resource s3c_i2c6_resource[] = {
  560. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  561. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  562. };
  563. struct platform_device s3c_device_i2c6 = {
  564. .name = "s3c2440-i2c",
  565. .id = 6,
  566. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  567. .resource = s3c_i2c6_resource,
  568. };
  569. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  570. {
  571. struct s3c2410_platform_i2c *npd;
  572. if (!pd) {
  573. pd = &default_i2c_data;
  574. pd->bus_num = 6;
  575. }
  576. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  577. &s3c_device_i2c6);
  578. if (!npd->cfg_gpio)
  579. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  580. }
  581. #endif /* CONFIG_S3C_DEV_I2C6 */
  582. #ifdef CONFIG_S3C_DEV_I2C7
  583. static struct resource s3c_i2c7_resource[] = {
  584. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  585. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  586. };
  587. struct platform_device s3c_device_i2c7 = {
  588. .name = "s3c2440-i2c",
  589. .id = 7,
  590. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  591. .resource = s3c_i2c7_resource,
  592. };
  593. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  594. {
  595. struct s3c2410_platform_i2c *npd;
  596. if (!pd) {
  597. pd = &default_i2c_data;
  598. pd->bus_num = 7;
  599. }
  600. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  601. &s3c_device_i2c7);
  602. if (!npd->cfg_gpio)
  603. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  604. }
  605. #endif /* CONFIG_S3C_DEV_I2C7 */
  606. /* I2C HDMIPHY */
  607. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  608. static struct resource s5p_i2c_resource[] = {
  609. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  610. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  611. };
  612. struct platform_device s5p_device_i2c_hdmiphy = {
  613. .name = "s3c2440-hdmiphy-i2c",
  614. .id = -1,
  615. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  616. .resource = s5p_i2c_resource,
  617. };
  618. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  619. {
  620. struct s3c2410_platform_i2c *npd;
  621. if (!pd) {
  622. pd = &default_i2c_data;
  623. if (soc_is_exynos4210() ||
  624. soc_is_exynos4212() || soc_is_exynos4412())
  625. pd->bus_num = 8;
  626. else if (soc_is_s5pv210())
  627. pd->bus_num = 3;
  628. else
  629. pd->bus_num = 0;
  630. }
  631. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  632. &s5p_device_i2c_hdmiphy);
  633. }
  634. static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  635. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  636. struct i2c_board_info *mhl_info, int mhl_bus)
  637. {
  638. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  639. if (soc_is_exynos4210() ||
  640. soc_is_exynos4212() || soc_is_exynos4412())
  641. pd->hdmiphy_bus = 8;
  642. else if (soc_is_s5pv210())
  643. pd->hdmiphy_bus = 3;
  644. else
  645. pd->hdmiphy_bus = 0;
  646. pd->hdmiphy_info = hdmiphy_info;
  647. pd->mhl_info = mhl_info;
  648. pd->mhl_bus = mhl_bus;
  649. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  650. &s5p_device_hdmi);
  651. }
  652. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  653. /* I2S */
  654. #ifdef CONFIG_PLAT_S3C24XX
  655. static struct resource s3c_iis_resource[] = {
  656. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  657. };
  658. struct platform_device s3c_device_iis = {
  659. .name = "s3c24xx-iis",
  660. .id = -1,
  661. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  662. .resource = s3c_iis_resource,
  663. .dev = {
  664. .dma_mask = &samsung_device_dma_mask,
  665. .coherent_dma_mask = DMA_BIT_MASK(32),
  666. }
  667. };
  668. #endif /* CONFIG_PLAT_S3C24XX */
  669. /* IDE CFCON */
  670. #ifdef CONFIG_SAMSUNG_DEV_IDE
  671. static struct resource s3c_cfcon_resource[] = {
  672. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  673. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  674. };
  675. struct platform_device s3c_device_cfcon = {
  676. .id = 0,
  677. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  678. .resource = s3c_cfcon_resource,
  679. };
  680. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  681. {
  682. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  683. &s3c_device_cfcon);
  684. }
  685. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  686. /* KEYPAD */
  687. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  688. static struct resource samsung_keypad_resources[] = {
  689. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  690. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  691. };
  692. struct platform_device samsung_device_keypad = {
  693. .name = "samsung-keypad",
  694. .id = -1,
  695. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  696. .resource = samsung_keypad_resources,
  697. };
  698. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  699. {
  700. struct samsung_keypad_platdata *npd;
  701. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  702. &samsung_device_keypad);
  703. if (!npd->cfg_gpio)
  704. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  705. }
  706. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  707. /* LCD Controller */
  708. #ifdef CONFIG_PLAT_S3C24XX
  709. static struct resource s3c_lcd_resource[] = {
  710. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  711. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  712. };
  713. struct platform_device s3c_device_lcd = {
  714. .name = "s3c2410-lcd",
  715. .id = -1,
  716. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  717. .resource = s3c_lcd_resource,
  718. .dev = {
  719. .dma_mask = &samsung_device_dma_mask,
  720. .coherent_dma_mask = DMA_BIT_MASK(32),
  721. }
  722. };
  723. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  724. {
  725. struct s3c2410fb_mach_info *npd;
  726. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  727. if (npd) {
  728. npd->displays = kmemdup(pd->displays,
  729. sizeof(struct s3c2410fb_display) * npd->num_displays,
  730. GFP_KERNEL);
  731. if (!npd->displays)
  732. printk(KERN_ERR "no memory for LCD display data\n");
  733. } else {
  734. printk(KERN_ERR "no memory for LCD platform data\n");
  735. }
  736. }
  737. #endif /* CONFIG_PLAT_S3C24XX */
  738. /* MFC */
  739. #ifdef CONFIG_S5P_DEV_MFC
  740. static struct resource s5p_mfc_resource[] = {
  741. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  742. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  743. };
  744. struct platform_device s5p_device_mfc = {
  745. .name = "s5p-mfc",
  746. .id = -1,
  747. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  748. .resource = s5p_mfc_resource,
  749. };
  750. /*
  751. * MFC hardware has 2 memory interfaces which are modelled as two separate
  752. * platform devices to let dma-mapping distinguish between them.
  753. *
  754. * MFC parent device (s5p_device_mfc) must be registered before memory
  755. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  756. */
  757. struct platform_device s5p_device_mfc_l = {
  758. .name = "s5p-mfc-l",
  759. .id = -1,
  760. .dev = {
  761. .parent = &s5p_device_mfc.dev,
  762. .dma_mask = &samsung_device_dma_mask,
  763. .coherent_dma_mask = DMA_BIT_MASK(32),
  764. },
  765. };
  766. struct platform_device s5p_device_mfc_r = {
  767. .name = "s5p-mfc-r",
  768. .id = -1,
  769. .dev = {
  770. .parent = &s5p_device_mfc.dev,
  771. .dma_mask = &samsung_device_dma_mask,
  772. .coherent_dma_mask = DMA_BIT_MASK(32),
  773. },
  774. };
  775. #endif /* CONFIG_S5P_DEV_MFC */
  776. /* MIPI CSIS */
  777. #ifdef CONFIG_S5P_DEV_CSIS0
  778. static struct resource s5p_mipi_csis0_resource[] = {
  779. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  780. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  781. };
  782. struct platform_device s5p_device_mipi_csis0 = {
  783. .name = "s5p-mipi-csis",
  784. .id = 0,
  785. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  786. .resource = s5p_mipi_csis0_resource,
  787. };
  788. #endif /* CONFIG_S5P_DEV_CSIS0 */
  789. #ifdef CONFIG_S5P_DEV_CSIS1
  790. static struct resource s5p_mipi_csis1_resource[] = {
  791. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  792. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  793. };
  794. struct platform_device s5p_device_mipi_csis1 = {
  795. .name = "s5p-mipi-csis",
  796. .id = 1,
  797. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  798. .resource = s5p_mipi_csis1_resource,
  799. };
  800. #endif
  801. /* NAND */
  802. #ifdef CONFIG_S3C_DEV_NAND
  803. static struct resource s3c_nand_resource[] = {
  804. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  805. };
  806. struct platform_device s3c_device_nand = {
  807. .name = "s3c2410-nand",
  808. .id = -1,
  809. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  810. .resource = s3c_nand_resource,
  811. };
  812. /*
  813. * s3c_nand_copy_set() - copy nand set data
  814. * @set: The new structure, directly copied from the old.
  815. *
  816. * Copy all the fields from the NAND set field from what is probably __initdata
  817. * to new kernel memory. The code returns 0 if the copy happened correctly or
  818. * an error code for the calling function to display.
  819. *
  820. * Note, we currently do not try and look to see if we've already copied the
  821. * data in a previous set.
  822. */
  823. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  824. {
  825. void *ptr;
  826. int size;
  827. size = sizeof(struct mtd_partition) * set->nr_partitions;
  828. if (size) {
  829. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  830. set->partitions = ptr;
  831. if (!ptr)
  832. return -ENOMEM;
  833. }
  834. if (set->nr_map && set->nr_chips) {
  835. size = sizeof(int) * set->nr_chips;
  836. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  837. set->nr_map = ptr;
  838. if (!ptr)
  839. return -ENOMEM;
  840. }
  841. if (set->ecc_layout) {
  842. ptr = kmemdup(set->ecc_layout,
  843. sizeof(struct nand_ecclayout), GFP_KERNEL);
  844. set->ecc_layout = ptr;
  845. if (!ptr)
  846. return -ENOMEM;
  847. }
  848. return 0;
  849. }
  850. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  851. {
  852. struct s3c2410_platform_nand *npd;
  853. int size;
  854. int ret;
  855. /* note, if we get a failure in allocation, we simply drop out of the
  856. * function. If there is so little memory available at initialisation
  857. * time then there is little chance the system is going to run.
  858. */
  859. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  860. &s3c_device_nand);
  861. if (!npd)
  862. return;
  863. /* now see if we need to copy any of the nand set data */
  864. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  865. if (size) {
  866. struct s3c2410_nand_set *from = npd->sets;
  867. struct s3c2410_nand_set *to;
  868. int i;
  869. to = kmemdup(from, size, GFP_KERNEL);
  870. npd->sets = to; /* set, even if we failed */
  871. if (!to) {
  872. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  873. return;
  874. }
  875. for (i = 0; i < npd->nr_sets; i++) {
  876. ret = s3c_nand_copy_set(to);
  877. if (ret) {
  878. printk(KERN_ERR "%s: failed to copy set %d\n",
  879. __func__, i);
  880. return;
  881. }
  882. to++;
  883. }
  884. }
  885. }
  886. #endif /* CONFIG_S3C_DEV_NAND */
  887. /* ONENAND */
  888. #ifdef CONFIG_S3C_DEV_ONENAND
  889. static struct resource s3c_onenand_resources[] = {
  890. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  891. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  892. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  893. };
  894. struct platform_device s3c_device_onenand = {
  895. .name = "samsung-onenand",
  896. .id = 0,
  897. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  898. .resource = s3c_onenand_resources,
  899. };
  900. #endif /* CONFIG_S3C_DEV_ONENAND */
  901. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  902. static struct resource s3c64xx_onenand1_resources[] = {
  903. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  904. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  905. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  906. };
  907. struct platform_device s3c64xx_device_onenand1 = {
  908. .name = "samsung-onenand",
  909. .id = 1,
  910. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  911. .resource = s3c64xx_onenand1_resources,
  912. };
  913. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  914. {
  915. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  916. &s3c64xx_device_onenand1);
  917. }
  918. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  919. #ifdef CONFIG_S5P_DEV_ONENAND
  920. static struct resource s5p_onenand_resources[] = {
  921. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  922. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  923. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  924. };
  925. struct platform_device s5p_device_onenand = {
  926. .name = "s5pc110-onenand",
  927. .id = -1,
  928. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  929. .resource = s5p_onenand_resources,
  930. };
  931. #endif /* CONFIG_S5P_DEV_ONENAND */
  932. /* PMU */
  933. #ifdef CONFIG_PLAT_S5P
  934. static struct resource s5p_pmu_resource[] = {
  935. DEFINE_RES_IRQ(IRQ_PMU)
  936. };
  937. static struct platform_device s5p_device_pmu = {
  938. .name = "arm-pmu",
  939. .id = -1,
  940. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  941. .resource = s5p_pmu_resource,
  942. };
  943. static int __init s5p_pmu_init(void)
  944. {
  945. platform_device_register(&s5p_device_pmu);
  946. return 0;
  947. }
  948. arch_initcall(s5p_pmu_init);
  949. #endif /* CONFIG_PLAT_S5P */
  950. /* PWM Timer */
  951. #ifdef CONFIG_SAMSUNG_DEV_PWM
  952. #define TIMER_RESOURCE_SIZE (1)
  953. #define TIMER_RESOURCE(_tmr, _irq) \
  954. (struct resource [TIMER_RESOURCE_SIZE]) { \
  955. [0] = { \
  956. .start = _irq, \
  957. .end = _irq, \
  958. .flags = IORESOURCE_IRQ \
  959. } \
  960. }
  961. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  962. .name = "s3c24xx-pwm", \
  963. .id = _tmr_no, \
  964. .num_resources = TIMER_RESOURCE_SIZE, \
  965. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  966. /*
  967. * since we already have an static mapping for the timer,
  968. * we do not bother setting any IO resource for the base.
  969. */
  970. struct platform_device s3c_device_timer[] = {
  971. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  972. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  973. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  974. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  975. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  976. };
  977. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  978. /* RTC */
  979. #ifdef CONFIG_PLAT_S3C24XX
  980. static struct resource s3c_rtc_resource[] = {
  981. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  982. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  983. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  984. };
  985. struct platform_device s3c_device_rtc = {
  986. .name = "s3c2410-rtc",
  987. .id = -1,
  988. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  989. .resource = s3c_rtc_resource,
  990. };
  991. #endif /* CONFIG_PLAT_S3C24XX */
  992. #ifdef CONFIG_S3C_DEV_RTC
  993. static struct resource s3c_rtc_resource[] = {
  994. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  995. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  996. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  997. };
  998. struct platform_device s3c_device_rtc = {
  999. .name = "s3c64xx-rtc",
  1000. .id = -1,
  1001. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  1002. .resource = s3c_rtc_resource,
  1003. };
  1004. #endif /* CONFIG_S3C_DEV_RTC */
  1005. /* SDI */
  1006. #ifdef CONFIG_PLAT_S3C24XX
  1007. static struct resource s3c_sdi_resource[] = {
  1008. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1009. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1010. };
  1011. struct platform_device s3c_device_sdi = {
  1012. .name = "s3c2410-sdi",
  1013. .id = -1,
  1014. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1015. .resource = s3c_sdi_resource,
  1016. };
  1017. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1018. {
  1019. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1020. &s3c_device_sdi);
  1021. }
  1022. #endif /* CONFIG_PLAT_S3C24XX */
  1023. /* SPI */
  1024. #ifdef CONFIG_PLAT_S3C24XX
  1025. static struct resource s3c_spi0_resource[] = {
  1026. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1027. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1028. };
  1029. struct platform_device s3c_device_spi0 = {
  1030. .name = "s3c2410-spi",
  1031. .id = 0,
  1032. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1033. .resource = s3c_spi0_resource,
  1034. .dev = {
  1035. .dma_mask = &samsung_device_dma_mask,
  1036. .coherent_dma_mask = DMA_BIT_MASK(32),
  1037. }
  1038. };
  1039. static struct resource s3c_spi1_resource[] = {
  1040. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1041. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1042. };
  1043. struct platform_device s3c_device_spi1 = {
  1044. .name = "s3c2410-spi",
  1045. .id = 1,
  1046. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1047. .resource = s3c_spi1_resource,
  1048. .dev = {
  1049. .dma_mask = &samsung_device_dma_mask,
  1050. .coherent_dma_mask = DMA_BIT_MASK(32),
  1051. }
  1052. };
  1053. #endif /* CONFIG_PLAT_S3C24XX */
  1054. /* Touchscreen */
  1055. #ifdef CONFIG_PLAT_S3C24XX
  1056. static struct resource s3c_ts_resource[] = {
  1057. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1058. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1059. };
  1060. struct platform_device s3c_device_ts = {
  1061. .name = "s3c2410-ts",
  1062. .id = -1,
  1063. .dev.parent = &s3c_device_adc.dev,
  1064. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1065. .resource = s3c_ts_resource,
  1066. };
  1067. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1068. {
  1069. s3c_set_platdata(hard_s3c2410ts_info,
  1070. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1071. }
  1072. #endif /* CONFIG_PLAT_S3C24XX */
  1073. #ifdef CONFIG_SAMSUNG_DEV_TS
  1074. static struct resource s3c_ts_resource[] = {
  1075. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1076. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1077. };
  1078. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1079. .delay = 10000,
  1080. .presc = 49,
  1081. .oversampling_shift = 2,
  1082. };
  1083. struct platform_device s3c_device_ts = {
  1084. .name = "s3c64xx-ts",
  1085. .id = -1,
  1086. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1087. .resource = s3c_ts_resource,
  1088. };
  1089. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1090. {
  1091. if (!pd)
  1092. pd = &default_ts_data;
  1093. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1094. &s3c_device_ts);
  1095. }
  1096. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1097. /* TV */
  1098. #ifdef CONFIG_S5P_DEV_TV
  1099. static struct resource s5p_hdmi_resources[] = {
  1100. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1101. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1102. };
  1103. struct platform_device s5p_device_hdmi = {
  1104. .name = "s5p-hdmi",
  1105. .id = -1,
  1106. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1107. .resource = s5p_hdmi_resources,
  1108. };
  1109. static struct resource s5p_sdo_resources[] = {
  1110. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1111. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1112. };
  1113. struct platform_device s5p_device_sdo = {
  1114. .name = "s5p-sdo",
  1115. .id = -1,
  1116. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1117. .resource = s5p_sdo_resources,
  1118. };
  1119. static struct resource s5p_mixer_resources[] = {
  1120. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1121. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1122. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1123. };
  1124. struct platform_device s5p_device_mixer = {
  1125. .name = "s5p-mixer",
  1126. .id = -1,
  1127. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1128. .resource = s5p_mixer_resources,
  1129. .dev = {
  1130. .dma_mask = &samsung_device_dma_mask,
  1131. .coherent_dma_mask = DMA_BIT_MASK(32),
  1132. }
  1133. };
  1134. #endif /* CONFIG_S5P_DEV_TV */
  1135. /* USB */
  1136. #ifdef CONFIG_S3C_DEV_USB_HOST
  1137. static struct resource s3c_usb_resource[] = {
  1138. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1139. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1140. };
  1141. struct platform_device s3c_device_ohci = {
  1142. .name = "s3c2410-ohci",
  1143. .id = -1,
  1144. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1145. .resource = s3c_usb_resource,
  1146. .dev = {
  1147. .dma_mask = &samsung_device_dma_mask,
  1148. .coherent_dma_mask = DMA_BIT_MASK(32),
  1149. }
  1150. };
  1151. /*
  1152. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1153. * @info: The platform data.
  1154. *
  1155. * This call copies the @info passed in and sets the device .platform_data
  1156. * field to that copy. The @info is copied so that the original can be marked
  1157. * __initdata.
  1158. */
  1159. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1160. {
  1161. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1162. &s3c_device_ohci);
  1163. }
  1164. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1165. /* USB Device (Gadget) */
  1166. #ifdef CONFIG_PLAT_S3C24XX
  1167. static struct resource s3c_usbgadget_resource[] = {
  1168. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1169. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1170. };
  1171. struct platform_device s3c_device_usbgadget = {
  1172. .name = "s3c2410-usbgadget",
  1173. .id = -1,
  1174. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1175. .resource = s3c_usbgadget_resource,
  1176. };
  1177. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1178. {
  1179. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1180. }
  1181. #endif /* CONFIG_PLAT_S3C24XX */
  1182. /* USB EHCI Host Controller */
  1183. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1184. static struct resource s5p_ehci_resource[] = {
  1185. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1186. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1187. };
  1188. struct platform_device s5p_device_ehci = {
  1189. .name = "s5p-ehci",
  1190. .id = -1,
  1191. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1192. .resource = s5p_ehci_resource,
  1193. .dev = {
  1194. .dma_mask = &samsung_device_dma_mask,
  1195. .coherent_dma_mask = DMA_BIT_MASK(32),
  1196. }
  1197. };
  1198. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1199. {
  1200. struct s5p_ehci_platdata *npd;
  1201. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1202. &s5p_device_ehci);
  1203. if (!npd->phy_init)
  1204. npd->phy_init = s5p_usb_phy_init;
  1205. if (!npd->phy_exit)
  1206. npd->phy_exit = s5p_usb_phy_exit;
  1207. }
  1208. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1209. /* USB HSOTG */
  1210. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1211. static struct resource s3c_usb_hsotg_resources[] = {
  1212. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1213. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1214. };
  1215. struct platform_device s3c_device_usb_hsotg = {
  1216. .name = "s3c-hsotg",
  1217. .id = -1,
  1218. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1219. .resource = s3c_usb_hsotg_resources,
  1220. .dev = {
  1221. .dma_mask = &samsung_device_dma_mask,
  1222. .coherent_dma_mask = DMA_BIT_MASK(32),
  1223. },
  1224. };
  1225. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1226. {
  1227. struct s3c_hsotg_plat *npd;
  1228. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1229. &s3c_device_usb_hsotg);
  1230. if (!npd->phy_init)
  1231. npd->phy_init = s5p_usb_phy_init;
  1232. if (!npd->phy_exit)
  1233. npd->phy_exit = s5p_usb_phy_exit;
  1234. }
  1235. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1236. /* USB High Spped 2.0 Device (Gadget) */
  1237. #ifdef CONFIG_PLAT_S3C24XX
  1238. static struct resource s3c_hsudc_resource[] = {
  1239. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1240. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1241. };
  1242. struct platform_device s3c_device_usb_hsudc = {
  1243. .name = "s3c-hsudc",
  1244. .id = -1,
  1245. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1246. .resource = s3c_hsudc_resource,
  1247. .dev = {
  1248. .dma_mask = &samsung_device_dma_mask,
  1249. .coherent_dma_mask = DMA_BIT_MASK(32),
  1250. },
  1251. };
  1252. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1253. {
  1254. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1255. }
  1256. #endif /* CONFIG_PLAT_S3C24XX */
  1257. /* WDT */
  1258. #ifdef CONFIG_S3C_DEV_WDT
  1259. static struct resource s3c_wdt_resource[] = {
  1260. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1261. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1262. };
  1263. struct platform_device s3c_device_wdt = {
  1264. .name = "s3c2410-wdt",
  1265. .id = -1,
  1266. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1267. .resource = s3c_wdt_resource,
  1268. };
  1269. #endif /* CONFIG_S3C_DEV_WDT */
  1270. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1271. static struct resource s3c64xx_spi0_resource[] = {
  1272. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1273. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1274. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1275. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1276. };
  1277. struct platform_device s3c64xx_device_spi0 = {
  1278. .name = "s3c6410-spi",
  1279. .id = 0,
  1280. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1281. .resource = s3c64xx_spi0_resource,
  1282. .dev = {
  1283. .dma_mask = &samsung_device_dma_mask,
  1284. .coherent_dma_mask = DMA_BIT_MASK(32),
  1285. },
  1286. };
  1287. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1288. int num_cs)
  1289. {
  1290. struct s3c64xx_spi_info pd;
  1291. /* Reject invalid configuration */
  1292. if (!num_cs || src_clk_nr < 0) {
  1293. pr_err("%s: Invalid SPI configuration\n", __func__);
  1294. return;
  1295. }
  1296. pd.num_cs = num_cs;
  1297. pd.src_clk_nr = src_clk_nr;
  1298. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1299. #ifdef CONFIG_PL330_DMA
  1300. pd.filter = pl330_filter;
  1301. #endif
  1302. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1303. }
  1304. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1305. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1306. static struct resource s3c64xx_spi1_resource[] = {
  1307. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1308. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1309. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1310. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1311. };
  1312. struct platform_device s3c64xx_device_spi1 = {
  1313. .name = "s3c6410-spi",
  1314. .id = 1,
  1315. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1316. .resource = s3c64xx_spi1_resource,
  1317. .dev = {
  1318. .dma_mask = &samsung_device_dma_mask,
  1319. .coherent_dma_mask = DMA_BIT_MASK(32),
  1320. },
  1321. };
  1322. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1323. int num_cs)
  1324. {
  1325. struct s3c64xx_spi_info pd;
  1326. /* Reject invalid configuration */
  1327. if (!num_cs || src_clk_nr < 0) {
  1328. pr_err("%s: Invalid SPI configuration\n", __func__);
  1329. return;
  1330. }
  1331. pd.num_cs = num_cs;
  1332. pd.src_clk_nr = src_clk_nr;
  1333. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1334. #ifdef CONFIG_PL330_DMA
  1335. pd.filter = pl330_filter;
  1336. #endif
  1337. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1338. }
  1339. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1340. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1341. static struct resource s3c64xx_spi2_resource[] = {
  1342. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1343. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1344. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1345. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1346. };
  1347. struct platform_device s3c64xx_device_spi2 = {
  1348. .name = "s3c6410-spi",
  1349. .id = 2,
  1350. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1351. .resource = s3c64xx_spi2_resource,
  1352. .dev = {
  1353. .dma_mask = &samsung_device_dma_mask,
  1354. .coherent_dma_mask = DMA_BIT_MASK(32),
  1355. },
  1356. };
  1357. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1358. int num_cs)
  1359. {
  1360. struct s3c64xx_spi_info pd;
  1361. /* Reject invalid configuration */
  1362. if (!num_cs || src_clk_nr < 0) {
  1363. pr_err("%s: Invalid SPI configuration\n", __func__);
  1364. return;
  1365. }
  1366. pd.num_cs = num_cs;
  1367. pd.src_clk_nr = src_clk_nr;
  1368. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1369. #ifdef CONFIG_PL330_DMA
  1370. pd.filter = pl330_filter;
  1371. #endif
  1372. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1373. }
  1374. #endif /* CONFIG_S3C64XX_DEV_SPI2 */