imx23.dtsi 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. serial0 = &auart0;
  19. serial1 = &auart1;
  20. };
  21. cpus {
  22. cpu@0 {
  23. compatible = "arm,arm926ejs";
  24. };
  25. };
  26. apb@80000000 {
  27. compatible = "simple-bus";
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. reg = <0x80000000 0x80000>;
  31. ranges;
  32. apbh@80000000 {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. reg = <0x80000000 0x40000>;
  37. ranges;
  38. icoll: interrupt-controller@80000000 {
  39. compatible = "fsl,imx23-icoll", "fsl,icoll";
  40. interrupt-controller;
  41. #interrupt-cells = <1>;
  42. reg = <0x80000000 0x2000>;
  43. };
  44. dma-apbh@80004000 {
  45. compatible = "fsl,imx23-dma-apbh";
  46. reg = <0x80004000 0x2000>;
  47. clocks = <&clks 15>;
  48. };
  49. ecc@80008000 {
  50. reg = <0x80008000 0x2000>;
  51. status = "disabled";
  52. };
  53. gpmi-nand@8000c000 {
  54. compatible = "fsl,imx23-gpmi-nand";
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  58. reg-names = "gpmi-nand", "bch";
  59. interrupts = <13>, <56>;
  60. interrupt-names = "gpmi-dma", "bch";
  61. clocks = <&clks 34>;
  62. clock-names = "gpmi_io";
  63. fsl,gpmi-dma-channel = <4>;
  64. status = "disabled";
  65. };
  66. ssp0: ssp@80010000 {
  67. reg = <0x80010000 0x2000>;
  68. interrupts = <15 14>;
  69. clocks = <&clks 33>;
  70. fsl,ssp-dma-channel = <1>;
  71. status = "disabled";
  72. };
  73. etm@80014000 {
  74. reg = <0x80014000 0x2000>;
  75. status = "disabled";
  76. };
  77. pinctrl@80018000 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. compatible = "fsl,imx23-pinctrl", "simple-bus";
  81. reg = <0x80018000 0x2000>;
  82. gpio0: gpio@0 {
  83. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  84. interrupts = <16>;
  85. gpio-controller;
  86. #gpio-cells = <2>;
  87. interrupt-controller;
  88. #interrupt-cells = <2>;
  89. };
  90. gpio1: gpio@1 {
  91. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  92. interrupts = <17>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. interrupt-controller;
  96. #interrupt-cells = <2>;
  97. };
  98. gpio2: gpio@2 {
  99. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  100. interrupts = <18>;
  101. gpio-controller;
  102. #gpio-cells = <2>;
  103. interrupt-controller;
  104. #interrupt-cells = <2>;
  105. };
  106. duart_pins_a: duart@0 {
  107. reg = <0>;
  108. fsl,pinmux-ids = <
  109. 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
  110. 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
  111. >;
  112. fsl,drive-strength = <0>;
  113. fsl,voltage = <1>;
  114. fsl,pull-up = <0>;
  115. };
  116. auart0_pins_a: auart0@0 {
  117. reg = <0>;
  118. fsl,pinmux-ids = <
  119. 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
  120. 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
  121. 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
  122. 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
  123. >;
  124. fsl,drive-strength = <0>;
  125. fsl,voltage = <1>;
  126. fsl,pull-up = <0>;
  127. };
  128. auart0_2pins_a: auart0-2pins@0 {
  129. reg = <0>;
  130. fsl,pinmux-ids = <
  131. 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
  132. 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
  133. >;
  134. fsl,drive-strength = <0>;
  135. fsl,voltage = <1>;
  136. fsl,pull-up = <0>;
  137. };
  138. gpmi_pins_a: gpmi-nand@0 {
  139. reg = <0>;
  140. fsl,pinmux-ids = <
  141. 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
  142. 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
  143. 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
  144. 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
  145. 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
  146. 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
  147. 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
  148. 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
  149. 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
  150. 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
  151. 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
  152. 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
  153. 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
  154. 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
  155. 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
  156. 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
  157. 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
  158. >;
  159. fsl,drive-strength = <0>;
  160. fsl,voltage = <1>;
  161. fsl,pull-up = <0>;
  162. };
  163. gpmi_pins_fixup: gpmi-pins-fixup {
  164. fsl,pinmux-ids = <
  165. 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
  166. 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
  167. 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
  168. >;
  169. fsl,drive-strength = <2>;
  170. };
  171. mmc0_4bit_pins_a: mmc0-4bit@0 {
  172. reg = <0>;
  173. fsl,pinmux-ids = <
  174. 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
  175. 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
  176. 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
  177. 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
  178. 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
  179. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  180. >;
  181. fsl,drive-strength = <1>;
  182. fsl,voltage = <1>;
  183. fsl,pull-up = <1>;
  184. };
  185. mmc0_8bit_pins_a: mmc0-8bit@0 {
  186. reg = <0>;
  187. fsl,pinmux-ids = <
  188. 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
  189. 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
  190. 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
  191. 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
  192. 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
  193. 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
  194. 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
  195. 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
  196. 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
  197. 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
  198. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  199. >;
  200. fsl,drive-strength = <1>;
  201. fsl,voltage = <1>;
  202. fsl,pull-up = <1>;
  203. };
  204. mmc0_pins_fixup: mmc0-pins-fixup {
  205. fsl,pinmux-ids = <
  206. 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
  207. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  208. >;
  209. fsl,pull-up = <0>;
  210. };
  211. pwm2_pins_a: pwm2@0 {
  212. reg = <0>;
  213. fsl,pinmux-ids = <
  214. 0x11c0 /* MX23_PAD_PWM2__PWM2 */
  215. >;
  216. fsl,drive-strength = <0>;
  217. fsl,voltage = <1>;
  218. fsl,pull-up = <0>;
  219. };
  220. lcdif_24bit_pins_a: lcdif-24bit@0 {
  221. reg = <0>;
  222. fsl,pinmux-ids = <
  223. 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
  224. 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
  225. 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
  226. 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
  227. 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
  228. 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
  229. 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
  230. 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
  231. 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
  232. 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
  233. 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
  234. 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
  235. 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
  236. 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
  237. 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
  238. 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
  239. 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
  240. 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
  241. 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
  242. 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
  243. 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
  244. 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
  245. 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
  246. 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
  247. 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
  248. 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
  249. 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
  250. 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
  251. >;
  252. fsl,drive-strength = <0>;
  253. fsl,voltage = <1>;
  254. fsl,pull-up = <0>;
  255. };
  256. spi2_pins_a: spi2@0 {
  257. reg = <0>;
  258. fsl,pinmux-ids = <
  259. 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
  260. 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
  261. 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
  262. 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
  263. >;
  264. fsl,drive-strength = <1>;
  265. fsl,voltage = <1>;
  266. fsl,pull-up = <1>;
  267. };
  268. };
  269. digctl@8001c000 {
  270. reg = <0x8001c000 2000>;
  271. status = "disabled";
  272. };
  273. emi@80020000 {
  274. reg = <0x80020000 0x2000>;
  275. status = "disabled";
  276. };
  277. dma-apbx@80024000 {
  278. compatible = "fsl,imx23-dma-apbx";
  279. reg = <0x80024000 0x2000>;
  280. clocks = <&clks 16>;
  281. };
  282. dcp@80028000 {
  283. reg = <0x80028000 0x2000>;
  284. status = "disabled";
  285. };
  286. pxp@8002a000 {
  287. reg = <0x8002a000 0x2000>;
  288. status = "disabled";
  289. };
  290. ocotp@8002c000 {
  291. reg = <0x8002c000 0x2000>;
  292. status = "disabled";
  293. };
  294. axi-ahb@8002e000 {
  295. reg = <0x8002e000 0x2000>;
  296. status = "disabled";
  297. };
  298. lcdif@80030000 {
  299. compatible = "fsl,imx23-lcdif";
  300. reg = <0x80030000 2000>;
  301. interrupts = <46 45>;
  302. clocks = <&clks 38>;
  303. status = "disabled";
  304. };
  305. ssp1: ssp@80034000 {
  306. reg = <0x80034000 0x2000>;
  307. interrupts = <2 20>;
  308. clocks = <&clks 33>;
  309. fsl,ssp-dma-channel = <2>;
  310. status = "disabled";
  311. };
  312. tvenc@80038000 {
  313. reg = <0x80038000 0x2000>;
  314. status = "disabled";
  315. };
  316. };
  317. apbx@80040000 {
  318. compatible = "simple-bus";
  319. #address-cells = <1>;
  320. #size-cells = <1>;
  321. reg = <0x80040000 0x40000>;
  322. ranges;
  323. clks: clkctrl@80040000 {
  324. compatible = "fsl,imx23-clkctrl";
  325. reg = <0x80040000 0x2000>;
  326. #clock-cells = <1>;
  327. };
  328. saif0: saif@80042000 {
  329. reg = <0x80042000 0x2000>;
  330. status = "disabled";
  331. };
  332. power@80044000 {
  333. reg = <0x80044000 0x2000>;
  334. status = "disabled";
  335. };
  336. saif1: saif@80046000 {
  337. reg = <0x80046000 0x2000>;
  338. status = "disabled";
  339. };
  340. audio-out@80048000 {
  341. reg = <0x80048000 0x2000>;
  342. status = "disabled";
  343. };
  344. audio-in@8004c000 {
  345. reg = <0x8004c000 0x2000>;
  346. status = "disabled";
  347. };
  348. lradc@80050000 {
  349. compatible = "fsl,imx23-lradc";
  350. reg = <0x80050000 0x2000>;
  351. interrupts = <36 37 38 39 40 41 42 43 44>;
  352. status = "disabled";
  353. };
  354. spdif@80054000 {
  355. reg = <0x80054000 2000>;
  356. status = "disabled";
  357. };
  358. i2c@80058000 {
  359. reg = <0x80058000 0x2000>;
  360. status = "disabled";
  361. };
  362. rtc@8005c000 {
  363. compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
  364. reg = <0x8005c000 0x2000>;
  365. interrupts = <22>;
  366. };
  367. pwm: pwm@80064000 {
  368. compatible = "fsl,imx23-pwm";
  369. reg = <0x80064000 0x2000>;
  370. clocks = <&clks 30>;
  371. #pwm-cells = <2>;
  372. fsl,pwm-number = <5>;
  373. status = "disabled";
  374. };
  375. timrot@80068000 {
  376. compatible = "fsl,imx23-timrot", "fsl,timrot";
  377. reg = <0x80068000 0x2000>;
  378. interrupts = <28 29 30 31>;
  379. };
  380. auart0: serial@8006c000 {
  381. compatible = "fsl,imx23-auart";
  382. reg = <0x8006c000 0x2000>;
  383. interrupts = <24 25 23>;
  384. clocks = <&clks 32>;
  385. status = "disabled";
  386. };
  387. auart1: serial@8006e000 {
  388. compatible = "fsl,imx23-auart";
  389. reg = <0x8006e000 0x2000>;
  390. interrupts = <59 60 58>;
  391. clocks = <&clks 32>;
  392. status = "disabled";
  393. };
  394. duart: serial@80070000 {
  395. compatible = "arm,pl011", "arm,primecell";
  396. reg = <0x80070000 0x2000>;
  397. interrupts = <0>;
  398. clocks = <&clks 32>, <&clks 16>;
  399. clock-names = "uart", "apb_pclk";
  400. status = "disabled";
  401. };
  402. usbphy0: usbphy@8007c000 {
  403. compatible = "fsl,imx23-usbphy";
  404. reg = <0x8007c000 0x2000>;
  405. clocks = <&clks 41>;
  406. status = "disabled";
  407. };
  408. };
  409. };
  410. ahb@80080000 {
  411. compatible = "simple-bus";
  412. #address-cells = <1>;
  413. #size-cells = <1>;
  414. reg = <0x80080000 0x80000>;
  415. ranges;
  416. usb0: usb@80080000 {
  417. compatible = "fsl,imx23-usb", "fsl,imx27-usb";
  418. reg = <0x80080000 0x40000>;
  419. interrupts = <11>;
  420. fsl,usbphy = <&usbphy0>;
  421. clocks = <&clks 40>;
  422. status = "disabled";
  423. };
  424. };
  425. };