ecx-common.dtsi 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237
  1. /*
  2. * Copyright 2011-2012 Calxeda, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. / {
  17. chosen {
  18. bootargs = "console=ttyAMA0";
  19. };
  20. soc {
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. compatible = "simple-bus";
  24. interrupt-parent = <&intc>;
  25. sata@ffe08000 {
  26. compatible = "calxeda,hb-ahci";
  27. reg = <0xffe08000 0x10000>;
  28. interrupts = <0 83 4>;
  29. dma-coherent;
  30. calxeda,port-phys = <&combophy5 0 &combophy0 0
  31. &combophy0 1 &combophy0 2
  32. &combophy0 3>;
  33. };
  34. sdhci@ffe0e000 {
  35. compatible = "calxeda,hb-sdhci";
  36. reg = <0xffe0e000 0x1000>;
  37. interrupts = <0 90 4>;
  38. clocks = <&eclk>;
  39. status = "disabled";
  40. };
  41. memory-controller@fff00000 {
  42. compatible = "calxeda,hb-ddr-ctrl";
  43. reg = <0xfff00000 0x1000>;
  44. interrupts = <0 91 4>;
  45. };
  46. ipc@fff20000 {
  47. compatible = "arm,pl320", "arm,primecell";
  48. reg = <0xfff20000 0x1000>;
  49. interrupts = <0 7 4>;
  50. clocks = <&pclk>;
  51. clock-names = "apb_pclk";
  52. };
  53. gpioe: gpio@fff30000 {
  54. #gpio-cells = <2>;
  55. compatible = "arm,pl061", "arm,primecell";
  56. gpio-controller;
  57. reg = <0xfff30000 0x1000>;
  58. interrupts = <0 14 4>;
  59. clocks = <&pclk>;
  60. clock-names = "apb_pclk";
  61. status = "disabled";
  62. };
  63. gpiof: gpio@fff31000 {
  64. #gpio-cells = <2>;
  65. compatible = "arm,pl061", "arm,primecell";
  66. gpio-controller;
  67. reg = <0xfff31000 0x1000>;
  68. interrupts = <0 15 4>;
  69. clocks = <&pclk>;
  70. clock-names = "apb_pclk";
  71. status = "disabled";
  72. };
  73. gpiog: gpio@fff32000 {
  74. #gpio-cells = <2>;
  75. compatible = "arm,pl061", "arm,primecell";
  76. gpio-controller;
  77. reg = <0xfff32000 0x1000>;
  78. interrupts = <0 16 4>;
  79. clocks = <&pclk>;
  80. clock-names = "apb_pclk";
  81. status = "disabled";
  82. };
  83. gpioh: gpio@fff33000 {
  84. #gpio-cells = <2>;
  85. compatible = "arm,pl061", "arm,primecell";
  86. gpio-controller;
  87. reg = <0xfff33000 0x1000>;
  88. interrupts = <0 17 4>;
  89. clocks = <&pclk>;
  90. clock-names = "apb_pclk";
  91. status = "disabled";
  92. };
  93. timer@fff34000 {
  94. compatible = "arm,sp804", "arm,primecell";
  95. reg = <0xfff34000 0x1000>;
  96. interrupts = <0 18 4>;
  97. clocks = <&pclk>;
  98. clock-names = "apb_pclk";
  99. };
  100. rtc@fff35000 {
  101. compatible = "arm,pl031", "arm,primecell";
  102. reg = <0xfff35000 0x1000>;
  103. interrupts = <0 19 4>;
  104. clocks = <&pclk>;
  105. clock-names = "apb_pclk";
  106. };
  107. serial@fff36000 {
  108. compatible = "arm,pl011", "arm,primecell";
  109. reg = <0xfff36000 0x1000>;
  110. interrupts = <0 20 4>;
  111. clocks = <&pclk>;
  112. clock-names = "apb_pclk";
  113. };
  114. smic@fff3a000 {
  115. compatible = "ipmi-smic";
  116. device_type = "ipmi";
  117. reg = <0xfff3a000 0x1000>;
  118. interrupts = <0 24 4>;
  119. reg-size = <4>;
  120. reg-spacing = <4>;
  121. };
  122. sregs@fff3c000 {
  123. compatible = "calxeda,hb-sregs";
  124. reg = <0xfff3c000 0x1000>;
  125. clocks {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. osc: oscillator {
  129. #clock-cells = <0>;
  130. compatible = "fixed-clock";
  131. clock-frequency = <33333000>;
  132. };
  133. ddrpll: ddrpll {
  134. #clock-cells = <0>;
  135. compatible = "calxeda,hb-pll-clock";
  136. clocks = <&osc>;
  137. reg = <0x108>;
  138. };
  139. a9pll: a9pll {
  140. #clock-cells = <0>;
  141. compatible = "calxeda,hb-pll-clock";
  142. clocks = <&osc>;
  143. reg = <0x100>;
  144. };
  145. a9periphclk: a9periphclk {
  146. #clock-cells = <0>;
  147. compatible = "calxeda,hb-a9periph-clock";
  148. clocks = <&a9pll>;
  149. reg = <0x104>;
  150. };
  151. a9bclk: a9bclk {
  152. #clock-cells = <0>;
  153. compatible = "calxeda,hb-a9bus-clock";
  154. clocks = <&a9pll>;
  155. reg = <0x104>;
  156. };
  157. emmcpll: emmcpll {
  158. #clock-cells = <0>;
  159. compatible = "calxeda,hb-pll-clock";
  160. clocks = <&osc>;
  161. reg = <0x10C>;
  162. };
  163. eclk: eclk {
  164. #clock-cells = <0>;
  165. compatible = "calxeda,hb-emmc-clock";
  166. clocks = <&emmcpll>;
  167. reg = <0x114>;
  168. };
  169. pclk: pclk {
  170. #clock-cells = <0>;
  171. compatible = "fixed-clock";
  172. clock-frequency = <150000000>;
  173. };
  174. };
  175. };
  176. dma@fff3d000 {
  177. compatible = "arm,pl330", "arm,primecell";
  178. reg = <0xfff3d000 0x1000>;
  179. interrupts = <0 92 4>;
  180. clocks = <&pclk>;
  181. clock-names = "apb_pclk";
  182. };
  183. ethernet@fff50000 {
  184. compatible = "calxeda,hb-xgmac";
  185. reg = <0xfff50000 0x1000>;
  186. interrupts = <0 77 4 0 78 4 0 79 4>;
  187. dma-coherent;
  188. };
  189. ethernet@fff51000 {
  190. compatible = "calxeda,hb-xgmac";
  191. reg = <0xfff51000 0x1000>;
  192. interrupts = <0 80 4 0 81 4 0 82 4>;
  193. dma-coherent;
  194. };
  195. combophy0: combo-phy@fff58000 {
  196. compatible = "calxeda,hb-combophy";
  197. #phy-cells = <1>;
  198. reg = <0xfff58000 0x1000>;
  199. phydev = <5>;
  200. };
  201. combophy5: combo-phy@fff5d000 {
  202. compatible = "calxeda,hb-combophy";
  203. #phy-cells = <1>;
  204. reg = <0xfff5d000 0x1000>;
  205. phydev = <31>;
  206. };
  207. };
  208. };