at91sam9n12.dtsi 11 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. ssc0 = &ssc0;
  29. };
  30. cpus {
  31. cpu@0 {
  32. compatible = "arm,arm926ejs";
  33. };
  34. };
  35. memory {
  36. reg = <0x20000000 0x10000000>;
  37. };
  38. ahb {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. apb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. aic: interrupt-controller@fffff000 {
  49. #interrupt-cells = <3>;
  50. compatible = "atmel,at91rm9200-aic";
  51. interrupt-controller;
  52. reg = <0xfffff000 0x200>;
  53. };
  54. ramc0: ramc@ffffe800 {
  55. compatible = "atmel,at91sam9g45-ddramc";
  56. reg = <0xffffe800 0x200>;
  57. };
  58. pmc: pmc@fffffc00 {
  59. compatible = "atmel,at91rm9200-pmc";
  60. reg = <0xfffffc00 0x100>;
  61. };
  62. rstc@fffffe00 {
  63. compatible = "atmel,at91sam9g45-rstc";
  64. reg = <0xfffffe00 0x10>;
  65. };
  66. pit: timer@fffffe30 {
  67. compatible = "atmel,at91sam9260-pit";
  68. reg = <0xfffffe30 0xf>;
  69. interrupts = <1 4 7>;
  70. };
  71. shdwc@fffffe10 {
  72. compatible = "atmel,at91sam9x5-shdwc";
  73. reg = <0xfffffe10 0x10>;
  74. };
  75. mmc0: mmc@f0008000 {
  76. compatible = "atmel,hsmci";
  77. reg = <0xf0008000 0x600>;
  78. interrupts = <12 4 0>;
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. status = "disabled";
  82. };
  83. tcb0: timer@f8008000 {
  84. compatible = "atmel,at91sam9x5-tcb";
  85. reg = <0xf8008000 0x100>;
  86. interrupts = <17 4 0>;
  87. };
  88. tcb1: timer@f800c000 {
  89. compatible = "atmel,at91sam9x5-tcb";
  90. reg = <0xf800c000 0x100>;
  91. interrupts = <17 4 0>;
  92. };
  93. dma: dma-controller@ffffec00 {
  94. compatible = "atmel,at91sam9g45-dma";
  95. reg = <0xffffec00 0x200>;
  96. interrupts = <20 4 0>;
  97. };
  98. pinctrl@fffff400 {
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  102. ranges = <0xfffff400 0xfffff400 0x800>;
  103. atmel,mux-mask = <
  104. /* A B C */
  105. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  106. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  107. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  108. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  109. >;
  110. /* shared pinctrl settings */
  111. dbgu {
  112. pinctrl_dbgu: dbgu-0 {
  113. atmel,pins =
  114. <0 9 0x1 0x0 /* PA9 periph A */
  115. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  116. };
  117. };
  118. usart0 {
  119. pinctrl_usart0: usart0-0 {
  120. atmel,pins =
  121. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  122. 0 0 0x1 0x0>; /* PA0 periph A */
  123. };
  124. pinctrl_usart0_rts: usart0_rts-0 {
  125. atmel,pins =
  126. <0 2 0x1 0x0>; /* PA2 periph A */
  127. };
  128. pinctrl_usart0_cts: usart0_cts-0 {
  129. atmel,pins =
  130. <0 3 0x1 0x0>; /* PA3 periph A */
  131. };
  132. };
  133. usart1 {
  134. pinctrl_usart1: usart1-0 {
  135. atmel,pins =
  136. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  137. 0 5 0x1 0x0>; /* PA5 periph A */
  138. };
  139. };
  140. usart2 {
  141. pinctrl_usart2: usart2-0 {
  142. atmel,pins =
  143. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  144. 0 7 0x1 0x0>; /* PA7 periph A */
  145. };
  146. pinctrl_usart2_rts: usart2_rts-0 {
  147. atmel,pins =
  148. <1 0 0x2 0x0>; /* PB0 periph B */
  149. };
  150. pinctrl_usart2_cts: usart2_cts-0 {
  151. atmel,pins =
  152. <1 1 0x2 0x0>; /* PB1 periph B */
  153. };
  154. };
  155. usart3 {
  156. pinctrl_usart3: usart3-0 {
  157. atmel,pins =
  158. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  159. 2 22 0x2 0x0>; /* PC22 periph B */
  160. };
  161. pinctrl_usart3_rts: usart3_rts-0 {
  162. atmel,pins =
  163. <2 24 0x2 0x0>; /* PC24 periph B */
  164. };
  165. pinctrl_usart3_cts: usart3_cts-0 {
  166. atmel,pins =
  167. <2 25 0x2 0x0>; /* PC25 periph B */
  168. };
  169. };
  170. uart0 {
  171. pinctrl_uart0: uart0-0 {
  172. atmel,pins =
  173. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  174. 2 8 0x3 0x0>; /* PC8 periph C */
  175. };
  176. };
  177. uart1 {
  178. pinctrl_uart1: uart1-0 {
  179. atmel,pins =
  180. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  181. 2 17 0x3 0x0>; /* PC16 periph C */
  182. };
  183. };
  184. nand {
  185. pinctrl_nand: nand-0 {
  186. atmel,pins =
  187. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  188. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  189. };
  190. };
  191. mmc0 {
  192. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  193. atmel,pins =
  194. <0 17 0x1 0x0 /* PA17 periph A */
  195. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  196. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  197. };
  198. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  199. atmel,pins =
  200. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  201. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  202. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  203. };
  204. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  205. atmel,pins =
  206. <0 11 0x2 0x1 /* PA11 periph B with pullup */
  207. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  208. 0 13 0x2 0x1 /* PA13 periph B with pullup */
  209. 0 14 0x2 0x1>; /* PA14 periph B with pullup */
  210. };
  211. };
  212. ssc0 {
  213. pinctrl_ssc0_tx: ssc0_tx-0 {
  214. atmel,pins =
  215. <0 24 0x2 0x0 /* PA24 periph B */
  216. 0 25 0x2 0x0 /* PA25 periph B */
  217. 0 26 0x2 0x0>; /* PA26 periph B */
  218. };
  219. pinctrl_ssc0_rx: ssc0_rx-0 {
  220. atmel,pins =
  221. <0 27 0x2 0x0 /* PA27 periph B */
  222. 0 28 0x2 0x0 /* PA28 periph B */
  223. 0 29 0x2 0x0>; /* PA29 periph B */
  224. };
  225. };
  226. spi0 {
  227. pinctrl_spi0: spi0-0 {
  228. atmel,pins =
  229. <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
  230. 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
  231. 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
  232. };
  233. };
  234. spi1 {
  235. pinctrl_spi1: spi1-0 {
  236. atmel,pins =
  237. <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
  238. 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
  239. 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
  240. };
  241. };
  242. pioA: gpio@fffff400 {
  243. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  244. reg = <0xfffff400 0x200>;
  245. interrupts = <2 4 1>;
  246. #gpio-cells = <2>;
  247. gpio-controller;
  248. interrupt-controller;
  249. #interrupt-cells = <2>;
  250. };
  251. pioB: gpio@fffff600 {
  252. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  253. reg = <0xfffff600 0x200>;
  254. interrupts = <2 4 1>;
  255. #gpio-cells = <2>;
  256. gpio-controller;
  257. interrupt-controller;
  258. #interrupt-cells = <2>;
  259. };
  260. pioC: gpio@fffff800 {
  261. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  262. reg = <0xfffff800 0x200>;
  263. interrupts = <3 4 1>;
  264. #gpio-cells = <2>;
  265. gpio-controller;
  266. interrupt-controller;
  267. #interrupt-cells = <2>;
  268. };
  269. pioD: gpio@fffffa00 {
  270. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  271. reg = <0xfffffa00 0x200>;
  272. interrupts = <3 4 1>;
  273. #gpio-cells = <2>;
  274. gpio-controller;
  275. interrupt-controller;
  276. #interrupt-cells = <2>;
  277. };
  278. };
  279. dbgu: serial@fffff200 {
  280. compatible = "atmel,at91sam9260-usart";
  281. reg = <0xfffff200 0x200>;
  282. interrupts = <1 4 7>;
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_dbgu>;
  285. status = "disabled";
  286. };
  287. ssc0: ssc@f0010000 {
  288. compatible = "atmel,at91sam9g45-ssc";
  289. reg = <0xf0010000 0x4000>;
  290. interrupts = <28 4 5>;
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  293. status = "disabled";
  294. };
  295. usart0: serial@f801c000 {
  296. compatible = "atmel,at91sam9260-usart";
  297. reg = <0xf801c000 0x4000>;
  298. interrupts = <5 4 5>;
  299. pinctrl-names = "default";
  300. pinctrl-0 = <&pinctrl_usart0>;
  301. status = "disabled";
  302. };
  303. usart1: serial@f8020000 {
  304. compatible = "atmel,at91sam9260-usart";
  305. reg = <0xf8020000 0x4000>;
  306. interrupts = <6 4 5>;
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&pinctrl_usart1>;
  309. status = "disabled";
  310. };
  311. usart2: serial@f8024000 {
  312. compatible = "atmel,at91sam9260-usart";
  313. reg = <0xf8024000 0x4000>;
  314. interrupts = <7 4 5>;
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&pinctrl_usart2>;
  317. status = "disabled";
  318. };
  319. usart3: serial@f8028000 {
  320. compatible = "atmel,at91sam9260-usart";
  321. reg = <0xf8028000 0x4000>;
  322. interrupts = <8 4 5>;
  323. pinctrl-names = "default";
  324. pinctrl-0 = <&pinctrl_usart3>;
  325. status = "disabled";
  326. };
  327. i2c0: i2c@f8010000 {
  328. compatible = "atmel,at91sam9x5-i2c";
  329. reg = <0xf8010000 0x100>;
  330. interrupts = <9 4 6>;
  331. #address-cells = <1>;
  332. #size-cells = <0>;
  333. status = "disabled";
  334. };
  335. i2c1: i2c@f8014000 {
  336. compatible = "atmel,at91sam9x5-i2c";
  337. reg = <0xf8014000 0x100>;
  338. interrupts = <10 4 6>;
  339. #address-cells = <1>;
  340. #size-cells = <0>;
  341. status = "disabled";
  342. };
  343. spi0: spi@f0000000 {
  344. #address-cells = <1>;
  345. #size-cells = <0>;
  346. compatible = "atmel,at91rm9200-spi";
  347. reg = <0xf0000000 0x100>;
  348. interrupts = <13 4 3>;
  349. pinctrl-names = "default";
  350. pinctrl-0 = <&pinctrl_spi0>;
  351. status = "disabled";
  352. };
  353. spi1: spi@f0004000 {
  354. #address-cells = <1>;
  355. #size-cells = <0>;
  356. compatible = "atmel,at91rm9200-spi";
  357. reg = <0xf0004000 0x100>;
  358. interrupts = <14 4 3>;
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_spi1>;
  361. status = "disabled";
  362. };
  363. };
  364. nand0: nand@40000000 {
  365. compatible = "atmel,at91rm9200-nand";
  366. #address-cells = <1>;
  367. #size-cells = <1>;
  368. reg = < 0x40000000 0x10000000
  369. 0xffffe000 0x00000600
  370. 0xffffe600 0x00000200
  371. 0x00108000 0x00018000
  372. >;
  373. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  374. atmel,nand-addr-offset = <21>;
  375. atmel,nand-cmd-offset = <22>;
  376. pinctrl-names = "default";
  377. pinctrl-0 = <&pinctrl_nand>;
  378. gpios = <&pioD 5 0
  379. &pioD 4 0
  380. 0
  381. >;
  382. status = "disabled";
  383. };
  384. usb0: ohci@00500000 {
  385. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  386. reg = <0x00500000 0x00100000>;
  387. interrupts = <22 4 2>;
  388. status = "disabled";
  389. };
  390. };
  391. i2c@0 {
  392. compatible = "i2c-gpio";
  393. gpios = <&pioA 30 0 /* sda */
  394. &pioA 31 0 /* scl */
  395. >;
  396. i2c-gpio,sda-open-drain;
  397. i2c-gpio,scl-open-drain;
  398. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  399. #address-cells = <1>;
  400. #size-cells = <0>;
  401. status = "disabled";
  402. };
  403. };