at91sam9g45.dtsi 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621
  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. ssc0 = &ssc0;
  32. ssc1 = &ssc1;
  33. };
  34. cpus {
  35. cpu@0 {
  36. compatible = "arm,arm926ejs";
  37. };
  38. };
  39. memory {
  40. reg = <0x70000000 0x10000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <31>;
  58. };
  59. ramc0: ramc@ffffe400 {
  60. compatible = "atmel,at91sam9g45-ddramc";
  61. reg = <0xffffe400 0x200
  62. 0xffffe600 0x200>;
  63. };
  64. pmc: pmc@fffffc00 {
  65. compatible = "atmel,at91rm9200-pmc";
  66. reg = <0xfffffc00 0x100>;
  67. };
  68. rstc@fffffd00 {
  69. compatible = "atmel,at91sam9g45-rstc";
  70. reg = <0xfffffd00 0x10>;
  71. };
  72. pit: timer@fffffd30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffd30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. shdwc@fffffd10 {
  78. compatible = "atmel,at91sam9rl-shdwc";
  79. reg = <0xfffffd10 0x10>;
  80. };
  81. tcb0: timer@fff7c000 {
  82. compatible = "atmel,at91rm9200-tcb";
  83. reg = <0xfff7c000 0x100>;
  84. interrupts = <18 4 0>;
  85. };
  86. tcb1: timer@fffd4000 {
  87. compatible = "atmel,at91rm9200-tcb";
  88. reg = <0xfffd4000 0x100>;
  89. interrupts = <18 4 0>;
  90. };
  91. dma: dma-controller@ffffec00 {
  92. compatible = "atmel,at91sam9g45-dma";
  93. reg = <0xffffec00 0x200>;
  94. interrupts = <21 4 0>;
  95. };
  96. pinctrl@fffff200 {
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  100. ranges = <0xfffff200 0xfffff200 0xa00>;
  101. atmel,mux-mask = <
  102. /* A B */
  103. 0xffffffff 0xffc003ff /* pioA */
  104. 0xffffffff 0x800f8f00 /* pioB */
  105. 0xffffffff 0x00000e00 /* pioC */
  106. 0xffffffff 0xff0c1381 /* pioD */
  107. 0xffffffff 0x81ffff81 /* pioE */
  108. >;
  109. /* shared pinctrl settings */
  110. dbgu {
  111. pinctrl_dbgu: dbgu-0 {
  112. atmel,pins =
  113. <1 12 0x1 0x0 /* PB12 periph A */
  114. 1 13 0x1 0x0>; /* PB13 periph A */
  115. };
  116. };
  117. usart0 {
  118. pinctrl_usart0: usart0-0 {
  119. atmel,pins =
  120. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  121. 1 18 0x1 0x0>; /* PB18 periph A */
  122. };
  123. pinctrl_usart0_rts: usart0_rts-0 {
  124. atmel,pins =
  125. <1 17 0x2 0x0>; /* PB17 periph B */
  126. };
  127. pinctrl_usart0_cts: usart0_cts-0 {
  128. atmel,pins =
  129. <1 15 0x2 0x0>; /* PB15 periph B */
  130. };
  131. };
  132. uart1 {
  133. pinctrl_usart1: usart1-0 {
  134. atmel,pins =
  135. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  136. 1 5 0x1 0x0>; /* PB5 periph A */
  137. };
  138. pinctrl_usart1_rts: usart1_rts-0 {
  139. atmel,pins =
  140. <3 16 0x1 0x0>; /* PD16 periph A */
  141. };
  142. pinctrl_usart1_cts: usart1_cts-0 {
  143. atmel,pins =
  144. <3 17 0x1 0x0>; /* PD17 periph A */
  145. };
  146. };
  147. usart2 {
  148. pinctrl_usart2: usart2-0 {
  149. atmel,pins =
  150. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  151. 1 7 0x1 0x0>; /* PB7 periph A */
  152. };
  153. pinctrl_usart2_rts: usart2_rts-0 {
  154. atmel,pins =
  155. <2 9 0x2 0x0>; /* PC9 periph B */
  156. };
  157. pinctrl_usart2_cts: usart2_cts-0 {
  158. atmel,pins =
  159. <2 11 0x2 0x0>; /* PC11 periph B */
  160. };
  161. };
  162. usart3 {
  163. pinctrl_usart3: usart3-0 {
  164. atmel,pins =
  165. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  166. 1 9 0x1 0x0>; /* PB8 periph A */
  167. };
  168. pinctrl_usart3_rts: usart3_rts-0 {
  169. atmel,pins =
  170. <0 23 0x2 0x0>; /* PA23 periph B */
  171. };
  172. pinctrl_usart3_cts: usart3_cts-0 {
  173. atmel,pins =
  174. <0 24 0x2 0x0>; /* PA24 periph B */
  175. };
  176. };
  177. nand {
  178. pinctrl_nand: nand-0 {
  179. atmel,pins =
  180. <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
  181. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  182. };
  183. };
  184. macb {
  185. pinctrl_macb_rmii: macb_rmii-0 {
  186. atmel,pins =
  187. <0 10 0x1 0x0 /* PA10 periph A */
  188. 0 11 0x1 0x0 /* PA11 periph A */
  189. 0 12 0x1 0x0 /* PA12 periph A */
  190. 0 13 0x1 0x0 /* PA13 periph A */
  191. 0 14 0x1 0x0 /* PA14 periph A */
  192. 0 15 0x1 0x0 /* PA15 periph A */
  193. 0 16 0x1 0x0 /* PA16 periph A */
  194. 0 17 0x1 0x0 /* PA17 periph A */
  195. 0 18 0x1 0x0 /* PA18 periph A */
  196. 0 19 0x1 0x0>; /* PA19 periph A */
  197. };
  198. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  199. atmel,pins =
  200. <0 6 0x2 0x0 /* PA6 periph B */
  201. 0 7 0x2 0x0 /* PA7 periph B */
  202. 0 8 0x2 0x0 /* PA8 periph B */
  203. 0 9 0x2 0x0 /* PA9 periph B */
  204. 0 27 0x2 0x0 /* PA27 periph B */
  205. 0 28 0x2 0x0 /* PA28 periph B */
  206. 0 29 0x2 0x0 /* PA29 periph B */
  207. 0 30 0x2 0x0>; /* PA30 periph B */
  208. };
  209. };
  210. mmc0 {
  211. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  212. atmel,pins =
  213. <0 0 0x1 0x0 /* PA0 periph A */
  214. 0 1 0x1 0x1 /* PA1 periph A with pullup */
  215. 0 2 0x1 0x1>; /* PA2 periph A with pullup */
  216. };
  217. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  218. atmel,pins =
  219. <0 3 0x1 0x1 /* PA3 periph A with pullup */
  220. 0 4 0x1 0x1 /* PA4 periph A with pullup */
  221. 0 5 0x1 0x1>; /* PA5 periph A with pullup */
  222. };
  223. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  224. atmel,pins =
  225. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  226. 0 7 0x1 0x1 /* PA7 periph A with pullup */
  227. 0 8 0x1 0x1 /* PA8 periph A with pullup */
  228. 0 9 0x1 0x1>; /* PA9 periph A with pullup */
  229. };
  230. };
  231. mmc1 {
  232. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  233. atmel,pins =
  234. <0 31 0x1 0x0 /* PA31 periph A */
  235. 0 22 0x1 0x1 /* PA22 periph A with pullup */
  236. 0 23 0x1 0x1>; /* PA23 periph A with pullup */
  237. };
  238. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  239. atmel,pins =
  240. <0 24 0x1 0x1 /* PA24 periph A with pullup */
  241. 0 25 0x1 0x1 /* PA25 periph A with pullup */
  242. 0 26 0x1 0x1>; /* PA26 periph A with pullup */
  243. };
  244. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  245. atmel,pins =
  246. <0 27 0x1 0x1 /* PA27 periph A with pullup */
  247. 0 28 0x1 0x1 /* PA28 periph A with pullup */
  248. 0 29 0x1 0x1 /* PA29 periph A with pullup */
  249. 0 20 0x1 0x1>; /* PA30 periph A with pullup */
  250. };
  251. };
  252. ssc0 {
  253. pinctrl_ssc0_tx: ssc0_tx-0 {
  254. atmel,pins =
  255. <3 0 0x1 0x0 /* PD0 periph A */
  256. 3 1 0x1 0x0 /* PD1 periph A */
  257. 3 2 0x1 0x0>; /* PD2 periph A */
  258. };
  259. pinctrl_ssc0_rx: ssc0_rx-0 {
  260. atmel,pins =
  261. <3 3 0x1 0x0 /* PD3 periph A */
  262. 3 4 0x1 0x0 /* PD4 periph A */
  263. 3 5 0x1 0x0>; /* PD5 periph A */
  264. };
  265. };
  266. ssc1 {
  267. pinctrl_ssc1_tx: ssc1_tx-0 {
  268. atmel,pins =
  269. <3 10 0x1 0x0 /* PD10 periph A */
  270. 3 11 0x1 0x0 /* PD11 periph A */
  271. 3 12 0x1 0x0>; /* PD12 periph A */
  272. };
  273. pinctrl_ssc1_rx: ssc1_rx-0 {
  274. atmel,pins =
  275. <3 13 0x1 0x0 /* PD13 periph A */
  276. 3 14 0x1 0x0 /* PD14 periph A */
  277. 3 15 0x1 0x0>; /* PD15 periph A */
  278. };
  279. };
  280. spi0 {
  281. pinctrl_spi0: spi0-0 {
  282. atmel,pins =
  283. <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */
  284. 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */
  285. 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */
  286. };
  287. };
  288. spi1 {
  289. pinctrl_spi1: spi1-0 {
  290. atmel,pins =
  291. <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */
  292. 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */
  293. 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
  294. };
  295. };
  296. pioA: gpio@fffff200 {
  297. compatible = "atmel,at91rm9200-gpio";
  298. reg = <0xfffff200 0x200>;
  299. interrupts = <2 4 1>;
  300. #gpio-cells = <2>;
  301. gpio-controller;
  302. interrupt-controller;
  303. #interrupt-cells = <2>;
  304. };
  305. pioB: gpio@fffff400 {
  306. compatible = "atmel,at91rm9200-gpio";
  307. reg = <0xfffff400 0x200>;
  308. interrupts = <3 4 1>;
  309. #gpio-cells = <2>;
  310. gpio-controller;
  311. interrupt-controller;
  312. #interrupt-cells = <2>;
  313. };
  314. pioC: gpio@fffff600 {
  315. compatible = "atmel,at91rm9200-gpio";
  316. reg = <0xfffff600 0x200>;
  317. interrupts = <4 4 1>;
  318. #gpio-cells = <2>;
  319. gpio-controller;
  320. interrupt-controller;
  321. #interrupt-cells = <2>;
  322. };
  323. pioD: gpio@fffff800 {
  324. compatible = "atmel,at91rm9200-gpio";
  325. reg = <0xfffff800 0x200>;
  326. interrupts = <5 4 1>;
  327. #gpio-cells = <2>;
  328. gpio-controller;
  329. interrupt-controller;
  330. #interrupt-cells = <2>;
  331. };
  332. pioE: gpio@fffffa00 {
  333. compatible = "atmel,at91rm9200-gpio";
  334. reg = <0xfffffa00 0x200>;
  335. interrupts = <5 4 1>;
  336. #gpio-cells = <2>;
  337. gpio-controller;
  338. interrupt-controller;
  339. #interrupt-cells = <2>;
  340. };
  341. };
  342. dbgu: serial@ffffee00 {
  343. compatible = "atmel,at91sam9260-usart";
  344. reg = <0xffffee00 0x200>;
  345. interrupts = <1 4 7>;
  346. pinctrl-names = "default";
  347. pinctrl-0 = <&pinctrl_dbgu>;
  348. status = "disabled";
  349. };
  350. usart0: serial@fff8c000 {
  351. compatible = "atmel,at91sam9260-usart";
  352. reg = <0xfff8c000 0x200>;
  353. interrupts = <7 4 5>;
  354. atmel,use-dma-rx;
  355. atmel,use-dma-tx;
  356. pinctrl-names = "default";
  357. pinctrl-0 = <&pinctrl_usart0>;
  358. status = "disabled";
  359. };
  360. usart1: serial@fff90000 {
  361. compatible = "atmel,at91sam9260-usart";
  362. reg = <0xfff90000 0x200>;
  363. interrupts = <8 4 5>;
  364. atmel,use-dma-rx;
  365. atmel,use-dma-tx;
  366. pinctrl-names = "default";
  367. pinctrl-0 = <&pinctrl_usart1>;
  368. status = "disabled";
  369. };
  370. usart2: serial@fff94000 {
  371. compatible = "atmel,at91sam9260-usart";
  372. reg = <0xfff94000 0x200>;
  373. interrupts = <9 4 5>;
  374. atmel,use-dma-rx;
  375. atmel,use-dma-tx;
  376. pinctrl-names = "default";
  377. pinctrl-0 = <&pinctrl_usart2>;
  378. status = "disabled";
  379. };
  380. usart3: serial@fff98000 {
  381. compatible = "atmel,at91sam9260-usart";
  382. reg = <0xfff98000 0x200>;
  383. interrupts = <10 4 5>;
  384. atmel,use-dma-rx;
  385. atmel,use-dma-tx;
  386. pinctrl-names = "default";
  387. pinctrl-0 = <&pinctrl_usart3>;
  388. status = "disabled";
  389. };
  390. macb0: ethernet@fffbc000 {
  391. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  392. reg = <0xfffbc000 0x100>;
  393. interrupts = <25 4 3>;
  394. pinctrl-names = "default";
  395. pinctrl-0 = <&pinctrl_macb_rmii>;
  396. status = "disabled";
  397. };
  398. i2c0: i2c@fff84000 {
  399. compatible = "atmel,at91sam9g10-i2c";
  400. reg = <0xfff84000 0x100>;
  401. interrupts = <12 4 6>;
  402. #address-cells = <1>;
  403. #size-cells = <0>;
  404. status = "disabled";
  405. };
  406. i2c1: i2c@fff88000 {
  407. compatible = "atmel,at91sam9g10-i2c";
  408. reg = <0xfff88000 0x100>;
  409. interrupts = <13 4 6>;
  410. #address-cells = <1>;
  411. #size-cells = <0>;
  412. status = "disabled";
  413. };
  414. ssc0: ssc@fff9c000 {
  415. compatible = "atmel,at91sam9g45-ssc";
  416. reg = <0xfff9c000 0x4000>;
  417. interrupts = <16 4 5>;
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  420. status = "disabled";
  421. };
  422. ssc1: ssc@fffa0000 {
  423. compatible = "atmel,at91sam9g45-ssc";
  424. reg = <0xfffa0000 0x4000>;
  425. interrupts = <17 4 5>;
  426. pinctrl-names = "default";
  427. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  428. status = "disabled";
  429. };
  430. adc0: adc@fffb0000 {
  431. compatible = "atmel,at91sam9260-adc";
  432. reg = <0xfffb0000 0x100>;
  433. interrupts = <20 4 0>;
  434. atmel,adc-use-external-triggers;
  435. atmel,adc-channels-used = <0xff>;
  436. atmel,adc-vref = <3300>;
  437. atmel,adc-num-channels = <8>;
  438. atmel,adc-startup-time = <40>;
  439. atmel,adc-channel-base = <0x30>;
  440. atmel,adc-drdy-mask = <0x10000>;
  441. atmel,adc-status-register = <0x1c>;
  442. atmel,adc-trigger-register = <0x08>;
  443. trigger@0 {
  444. trigger-name = "external-rising";
  445. trigger-value = <0x1>;
  446. trigger-external;
  447. };
  448. trigger@1 {
  449. trigger-name = "external-falling";
  450. trigger-value = <0x2>;
  451. trigger-external;
  452. };
  453. trigger@2 {
  454. trigger-name = "external-any";
  455. trigger-value = <0x3>;
  456. trigger-external;
  457. };
  458. trigger@3 {
  459. trigger-name = "continuous";
  460. trigger-value = <0x6>;
  461. };
  462. };
  463. mmc0: mmc@fff80000 {
  464. compatible = "atmel,hsmci";
  465. reg = <0xfff80000 0x600>;
  466. interrupts = <11 4 0>;
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. status = "disabled";
  470. };
  471. mmc1: mmc@fffd0000 {
  472. compatible = "atmel,hsmci";
  473. reg = <0xfffd0000 0x600>;
  474. interrupts = <29 4 0>;
  475. #address-cells = <1>;
  476. #size-cells = <0>;
  477. status = "disabled";
  478. };
  479. watchdog@fffffd40 {
  480. compatible = "atmel,at91sam9260-wdt";
  481. reg = <0xfffffd40 0x10>;
  482. status = "disabled";
  483. };
  484. spi0: spi@fffa4000 {
  485. #address-cells = <1>;
  486. #size-cells = <0>;
  487. compatible = "atmel,at91rm9200-spi";
  488. reg = <0xfffa4000 0x200>;
  489. interrupts = <14 4 3>;
  490. pinctrl-names = "default";
  491. pinctrl-0 = <&pinctrl_spi0>;
  492. status = "disabled";
  493. };
  494. spi1: spi@fffa8000 {
  495. #address-cells = <1>;
  496. #size-cells = <0>;
  497. compatible = "atmel,at91rm9200-spi";
  498. reg = <0xfffa8000 0x200>;
  499. interrupts = <15 4 3>;
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_spi1>;
  502. status = "disabled";
  503. };
  504. };
  505. nand0: nand@40000000 {
  506. compatible = "atmel,at91rm9200-nand";
  507. #address-cells = <1>;
  508. #size-cells = <1>;
  509. reg = <0x40000000 0x10000000
  510. 0xffffe200 0x200
  511. >;
  512. atmel,nand-addr-offset = <21>;
  513. atmel,nand-cmd-offset = <22>;
  514. pinctrl-names = "default";
  515. pinctrl-0 = <&pinctrl_nand>;
  516. gpios = <&pioC 8 0
  517. &pioC 14 0
  518. 0
  519. >;
  520. status = "disabled";
  521. };
  522. usb0: ohci@00700000 {
  523. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  524. reg = <0x00700000 0x100000>;
  525. interrupts = <22 4 2>;
  526. status = "disabled";
  527. };
  528. usb1: ehci@00800000 {
  529. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  530. reg = <0x00800000 0x100000>;
  531. interrupts = <22 4 2>;
  532. status = "disabled";
  533. };
  534. };
  535. i2c@0 {
  536. compatible = "i2c-gpio";
  537. gpios = <&pioA 20 0 /* sda */
  538. &pioA 21 0 /* scl */
  539. >;
  540. i2c-gpio,sda-open-drain;
  541. i2c-gpio,scl-open-drain;
  542. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  543. #address-cells = <1>;
  544. #size-cells = <0>;
  545. status = "disabled";
  546. };
  547. };