armada-xp-db.dts 2.2 KB

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  1. /*
  2. * Device Tree file for Marvell Armada XP evaluation board
  3. * (DB-78460-BP)
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Lior Amsalem <alior@marvell.com>
  8. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. /dts-v1/;
  16. /include/ "armada-xp-mv78460.dtsi"
  17. / {
  18. model = "Marvell Armada XP Evaluation Board";
  19. compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  20. chosen {
  21. bootargs = "console=ttyS0,115200 earlyprintk";
  22. };
  23. memory {
  24. device_type = "memory";
  25. reg = <0x00000000 0x80000000>; /* 2 GB */
  26. };
  27. soc {
  28. serial@d0012000 {
  29. clock-frequency = <250000000>;
  30. status = "okay";
  31. };
  32. serial@d0012100 {
  33. clock-frequency = <250000000>;
  34. status = "okay";
  35. };
  36. serial@d0012200 {
  37. clock-frequency = <250000000>;
  38. status = "okay";
  39. };
  40. serial@d0012300 {
  41. clock-frequency = <250000000>;
  42. status = "okay";
  43. };
  44. sata@d00a0000 {
  45. nr-ports = <2>;
  46. status = "okay";
  47. };
  48. mdio {
  49. phy0: ethernet-phy@0 {
  50. reg = <0>;
  51. };
  52. phy1: ethernet-phy@1 {
  53. reg = <1>;
  54. };
  55. phy2: ethernet-phy@2 {
  56. reg = <25>;
  57. };
  58. phy3: ethernet-phy@3 {
  59. reg = <27>;
  60. };
  61. };
  62. ethernet@d0070000 {
  63. status = "okay";
  64. phy = <&phy0>;
  65. phy-mode = "rgmii-id";
  66. };
  67. ethernet@d0074000 {
  68. status = "okay";
  69. phy = <&phy1>;
  70. phy-mode = "rgmii-id";
  71. };
  72. ethernet@d0030000 {
  73. status = "okay";
  74. phy = <&phy2>;
  75. phy-mode = "sgmii";
  76. };
  77. ethernet@d0034000 {
  78. status = "okay";
  79. phy = <&phy3>;
  80. phy-mode = "sgmii";
  81. };
  82. mvsdio@d00d4000 {
  83. pinctrl-0 = <&sdio_pins>;
  84. pinctrl-names = "default";
  85. status = "okay";
  86. /* No CD or WP GPIOs */
  87. };
  88. usb@d0050000 {
  89. status = "okay";
  90. };
  91. usb@d0051000 {
  92. status = "okay";
  93. };
  94. usb@d0052000 {
  95. status = "okay";
  96. };
  97. spi0: spi@d0010600 {
  98. status = "okay";
  99. spi-flash@0 {
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. compatible = "m25p64";
  103. reg = <0>; /* Chip select 0 */
  104. spi-max-frequency = <20000000>;
  105. };
  106. };
  107. };
  108. };