ftmac100.c 30 KB

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  1. /*
  2. * Faraday FTMAC100 10/100 Ethernet
  3. *
  4. * (C) Copyright 2009-2011 Faraday Technology
  5. * Po-Yu Chuang <ratbert@faraday-tech.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/dma-mapping.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/init.h>
  26. #include <linux/io.h>
  27. #include <linux/mii.h>
  28. #include <linux/module.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/platform_device.h>
  31. #include "ftmac100.h"
  32. #define DRV_NAME "ftmac100"
  33. #define DRV_VERSION "0.2"
  34. #define RX_QUEUE_ENTRIES 128 /* must be power of 2 */
  35. #define TX_QUEUE_ENTRIES 16 /* must be power of 2 */
  36. #define MAX_PKT_SIZE 1518
  37. #define RX_BUF_SIZE 2044 /* must be smaller than 0x7ff */
  38. #if MAX_PKT_SIZE > 0x7ff
  39. #error invalid MAX_PKT_SIZE
  40. #endif
  41. #if RX_BUF_SIZE > 0x7ff || RX_BUF_SIZE > PAGE_SIZE
  42. #error invalid RX_BUF_SIZE
  43. #endif
  44. /******************************************************************************
  45. * private data
  46. *****************************************************************************/
  47. struct ftmac100_descs {
  48. struct ftmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
  49. struct ftmac100_txdes txdes[TX_QUEUE_ENTRIES];
  50. };
  51. struct ftmac100 {
  52. struct resource *res;
  53. void __iomem *base;
  54. int irq;
  55. struct ftmac100_descs *descs;
  56. dma_addr_t descs_dma_addr;
  57. unsigned int rx_pointer;
  58. unsigned int tx_clean_pointer;
  59. unsigned int tx_pointer;
  60. unsigned int tx_pending;
  61. spinlock_t tx_lock;
  62. struct net_device *netdev;
  63. struct device *dev;
  64. struct napi_struct napi;
  65. struct mii_if_info mii;
  66. };
  67. static int ftmac100_alloc_rx_page(struct ftmac100 *priv, struct ftmac100_rxdes *rxdes);
  68. /******************************************************************************
  69. * internal functions (hardware register access)
  70. *****************************************************************************/
  71. #define INT_MASK_ALL_ENABLED (FTMAC100_INT_RPKT_FINISH | \
  72. FTMAC100_INT_NORXBUF | \
  73. FTMAC100_INT_XPKT_OK | \
  74. FTMAC100_INT_XPKT_LOST | \
  75. FTMAC100_INT_RPKT_LOST | \
  76. FTMAC100_INT_AHB_ERR | \
  77. FTMAC100_INT_PHYSTS_CHG)
  78. #define INT_MASK_ALL_DISABLED 0
  79. static void ftmac100_enable_all_int(struct ftmac100 *priv)
  80. {
  81. iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTMAC100_OFFSET_IMR);
  82. }
  83. static void ftmac100_disable_all_int(struct ftmac100 *priv)
  84. {
  85. iowrite32(INT_MASK_ALL_DISABLED, priv->base + FTMAC100_OFFSET_IMR);
  86. }
  87. static void ftmac100_set_rx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  88. {
  89. iowrite32(addr, priv->base + FTMAC100_OFFSET_RXR_BADR);
  90. }
  91. static void ftmac100_set_tx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  92. {
  93. iowrite32(addr, priv->base + FTMAC100_OFFSET_TXR_BADR);
  94. }
  95. static void ftmac100_txdma_start_polling(struct ftmac100 *priv)
  96. {
  97. iowrite32(1, priv->base + FTMAC100_OFFSET_TXPD);
  98. }
  99. static int ftmac100_reset(struct ftmac100 *priv)
  100. {
  101. struct net_device *netdev = priv->netdev;
  102. int i;
  103. /* NOTE: reset clears all registers */
  104. iowrite32(FTMAC100_MACCR_SW_RST, priv->base + FTMAC100_OFFSET_MACCR);
  105. for (i = 0; i < 5; i++) {
  106. unsigned int maccr;
  107. maccr = ioread32(priv->base + FTMAC100_OFFSET_MACCR);
  108. if (!(maccr & FTMAC100_MACCR_SW_RST)) {
  109. /*
  110. * FTMAC100_MACCR_SW_RST cleared does not indicate
  111. * that hardware reset completed (what the f*ck).
  112. * We still need to wait for a while.
  113. */
  114. usleep_range(500, 1000);
  115. return 0;
  116. }
  117. usleep_range(1000, 10000);
  118. }
  119. netdev_err(netdev, "software reset failed\n");
  120. return -EIO;
  121. }
  122. static void ftmac100_set_mac(struct ftmac100 *priv, const unsigned char *mac)
  123. {
  124. unsigned int maddr = mac[0] << 8 | mac[1];
  125. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  126. iowrite32(maddr, priv->base + FTMAC100_OFFSET_MAC_MADR);
  127. iowrite32(laddr, priv->base + FTMAC100_OFFSET_MAC_LADR);
  128. }
  129. #define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \
  130. FTMAC100_MACCR_RCV_EN | \
  131. FTMAC100_MACCR_XDMA_EN | \
  132. FTMAC100_MACCR_RDMA_EN | \
  133. FTMAC100_MACCR_CRC_APD | \
  134. FTMAC100_MACCR_FULLDUP | \
  135. FTMAC100_MACCR_RX_RUNT | \
  136. FTMAC100_MACCR_RX_BROADPKT)
  137. static int ftmac100_start_hw(struct ftmac100 *priv)
  138. {
  139. struct net_device *netdev = priv->netdev;
  140. if (ftmac100_reset(priv))
  141. return -EIO;
  142. /* setup ring buffer base registers */
  143. ftmac100_set_rx_ring_base(priv,
  144. priv->descs_dma_addr +
  145. offsetof(struct ftmac100_descs, rxdes));
  146. ftmac100_set_tx_ring_base(priv,
  147. priv->descs_dma_addr +
  148. offsetof(struct ftmac100_descs, txdes));
  149. iowrite32(FTMAC100_APTC_RXPOLL_CNT(1), priv->base + FTMAC100_OFFSET_APTC);
  150. ftmac100_set_mac(priv, netdev->dev_addr);
  151. iowrite32(MACCR_ENABLE_ALL, priv->base + FTMAC100_OFFSET_MACCR);
  152. return 0;
  153. }
  154. static void ftmac100_stop_hw(struct ftmac100 *priv)
  155. {
  156. iowrite32(0, priv->base + FTMAC100_OFFSET_MACCR);
  157. }
  158. /******************************************************************************
  159. * internal functions (receive descriptor)
  160. *****************************************************************************/
  161. static bool ftmac100_rxdes_first_segment(struct ftmac100_rxdes *rxdes)
  162. {
  163. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FRS);
  164. }
  165. static bool ftmac100_rxdes_last_segment(struct ftmac100_rxdes *rxdes)
  166. {
  167. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_LRS);
  168. }
  169. static bool ftmac100_rxdes_owned_by_dma(struct ftmac100_rxdes *rxdes)
  170. {
  171. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  172. }
  173. static void ftmac100_rxdes_set_dma_own(struct ftmac100_rxdes *rxdes)
  174. {
  175. /* clear status bits */
  176. rxdes->rxdes0 = cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  177. }
  178. static bool ftmac100_rxdes_rx_error(struct ftmac100_rxdes *rxdes)
  179. {
  180. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ERR);
  181. }
  182. static bool ftmac100_rxdes_crc_error(struct ftmac100_rxdes *rxdes)
  183. {
  184. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_CRC_ERR);
  185. }
  186. static bool ftmac100_rxdes_frame_too_long(struct ftmac100_rxdes *rxdes)
  187. {
  188. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FTL);
  189. }
  190. static bool ftmac100_rxdes_runt(struct ftmac100_rxdes *rxdes)
  191. {
  192. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RUNT);
  193. }
  194. static bool ftmac100_rxdes_odd_nibble(struct ftmac100_rxdes *rxdes)
  195. {
  196. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ODD_NB);
  197. }
  198. static unsigned int ftmac100_rxdes_frame_length(struct ftmac100_rxdes *rxdes)
  199. {
  200. return le32_to_cpu(rxdes->rxdes0) & FTMAC100_RXDES0_RFL;
  201. }
  202. static bool ftmac100_rxdes_multicast(struct ftmac100_rxdes *rxdes)
  203. {
  204. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_MULTICAST);
  205. }
  206. static void ftmac100_rxdes_set_buffer_size(struct ftmac100_rxdes *rxdes,
  207. unsigned int size)
  208. {
  209. rxdes->rxdes1 &= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  210. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_RXBUF_SIZE(size));
  211. }
  212. static void ftmac100_rxdes_set_end_of_ring(struct ftmac100_rxdes *rxdes)
  213. {
  214. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  215. }
  216. static void ftmac100_rxdes_set_dma_addr(struct ftmac100_rxdes *rxdes,
  217. dma_addr_t addr)
  218. {
  219. rxdes->rxdes2 = cpu_to_le32(addr);
  220. }
  221. static dma_addr_t ftmac100_rxdes_get_dma_addr(struct ftmac100_rxdes *rxdes)
  222. {
  223. return le32_to_cpu(rxdes->rxdes2);
  224. }
  225. /*
  226. * rxdes3 is not used by hardware. We use it to keep track of page.
  227. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  228. */
  229. static void ftmac100_rxdes_set_page(struct ftmac100_rxdes *rxdes, struct page *page)
  230. {
  231. rxdes->rxdes3 = (unsigned int)page;
  232. }
  233. static struct page *ftmac100_rxdes_get_page(struct ftmac100_rxdes *rxdes)
  234. {
  235. return (struct page *)rxdes->rxdes3;
  236. }
  237. /******************************************************************************
  238. * internal functions (receive)
  239. *****************************************************************************/
  240. static int ftmac100_next_rx_pointer(int pointer)
  241. {
  242. return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
  243. }
  244. static void ftmac100_rx_pointer_advance(struct ftmac100 *priv)
  245. {
  246. priv->rx_pointer = ftmac100_next_rx_pointer(priv->rx_pointer);
  247. }
  248. static struct ftmac100_rxdes *ftmac100_current_rxdes(struct ftmac100 *priv)
  249. {
  250. return &priv->descs->rxdes[priv->rx_pointer];
  251. }
  252. static struct ftmac100_rxdes *
  253. ftmac100_rx_locate_first_segment(struct ftmac100 *priv)
  254. {
  255. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  256. while (!ftmac100_rxdes_owned_by_dma(rxdes)) {
  257. if (ftmac100_rxdes_first_segment(rxdes))
  258. return rxdes;
  259. ftmac100_rxdes_set_dma_own(rxdes);
  260. ftmac100_rx_pointer_advance(priv);
  261. rxdes = ftmac100_current_rxdes(priv);
  262. }
  263. return NULL;
  264. }
  265. static bool ftmac100_rx_packet_error(struct ftmac100 *priv,
  266. struct ftmac100_rxdes *rxdes)
  267. {
  268. struct net_device *netdev = priv->netdev;
  269. bool error = false;
  270. if (unlikely(ftmac100_rxdes_rx_error(rxdes))) {
  271. if (net_ratelimit())
  272. netdev_info(netdev, "rx err\n");
  273. netdev->stats.rx_errors++;
  274. error = true;
  275. }
  276. if (unlikely(ftmac100_rxdes_crc_error(rxdes))) {
  277. if (net_ratelimit())
  278. netdev_info(netdev, "rx crc err\n");
  279. netdev->stats.rx_crc_errors++;
  280. error = true;
  281. }
  282. if (unlikely(ftmac100_rxdes_frame_too_long(rxdes))) {
  283. if (net_ratelimit())
  284. netdev_info(netdev, "rx frame too long\n");
  285. netdev->stats.rx_length_errors++;
  286. error = true;
  287. } else if (unlikely(ftmac100_rxdes_runt(rxdes))) {
  288. if (net_ratelimit())
  289. netdev_info(netdev, "rx runt\n");
  290. netdev->stats.rx_length_errors++;
  291. error = true;
  292. } else if (unlikely(ftmac100_rxdes_odd_nibble(rxdes))) {
  293. if (net_ratelimit())
  294. netdev_info(netdev, "rx odd nibble\n");
  295. netdev->stats.rx_length_errors++;
  296. error = true;
  297. }
  298. return error;
  299. }
  300. static void ftmac100_rx_drop_packet(struct ftmac100 *priv)
  301. {
  302. struct net_device *netdev = priv->netdev;
  303. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  304. bool done = false;
  305. if (net_ratelimit())
  306. netdev_dbg(netdev, "drop packet %p\n", rxdes);
  307. do {
  308. if (ftmac100_rxdes_last_segment(rxdes))
  309. done = true;
  310. ftmac100_rxdes_set_dma_own(rxdes);
  311. ftmac100_rx_pointer_advance(priv);
  312. rxdes = ftmac100_current_rxdes(priv);
  313. } while (!done && !ftmac100_rxdes_owned_by_dma(rxdes));
  314. netdev->stats.rx_dropped++;
  315. }
  316. static bool ftmac100_rx_packet(struct ftmac100 *priv, int *processed)
  317. {
  318. struct net_device *netdev = priv->netdev;
  319. struct ftmac100_rxdes *rxdes;
  320. struct sk_buff *skb;
  321. struct page *page;
  322. dma_addr_t map;
  323. int length;
  324. rxdes = ftmac100_rx_locate_first_segment(priv);
  325. if (!rxdes)
  326. return false;
  327. if (unlikely(ftmac100_rx_packet_error(priv, rxdes))) {
  328. ftmac100_rx_drop_packet(priv);
  329. return true;
  330. }
  331. /*
  332. * It is impossible to get multi-segment packets
  333. * because we always provide big enough receive buffers.
  334. */
  335. if (unlikely(!ftmac100_rxdes_last_segment(rxdes)))
  336. BUG();
  337. /* start processing */
  338. skb = netdev_alloc_skb_ip_align(netdev, 128);
  339. if (unlikely(!skb)) {
  340. if (net_ratelimit())
  341. netdev_err(netdev, "rx skb alloc failed\n");
  342. ftmac100_rx_drop_packet(priv);
  343. return true;
  344. }
  345. if (unlikely(ftmac100_rxdes_multicast(rxdes)))
  346. netdev->stats.multicast++;
  347. map = ftmac100_rxdes_get_dma_addr(rxdes);
  348. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  349. length = ftmac100_rxdes_frame_length(rxdes);
  350. page = ftmac100_rxdes_get_page(rxdes);
  351. skb_fill_page_desc(skb, 0, page, 0, length);
  352. skb->len += length;
  353. skb->data_len += length;
  354. skb->truesize += length;
  355. __pskb_pull_tail(skb, min(length, 64));
  356. ftmac100_alloc_rx_page(priv, rxdes);
  357. ftmac100_rx_pointer_advance(priv);
  358. skb->protocol = eth_type_trans(skb, netdev);
  359. netdev->stats.rx_packets++;
  360. netdev->stats.rx_bytes += skb->len;
  361. /* push packet to protocol stack */
  362. netif_receive_skb(skb);
  363. (*processed)++;
  364. return true;
  365. }
  366. /******************************************************************************
  367. * internal functions (transmit descriptor)
  368. *****************************************************************************/
  369. static void ftmac100_txdes_reset(struct ftmac100_txdes *txdes)
  370. {
  371. /* clear all except end of ring bit */
  372. txdes->txdes0 = 0;
  373. txdes->txdes1 &= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  374. txdes->txdes2 = 0;
  375. txdes->txdes3 = 0;
  376. }
  377. static bool ftmac100_txdes_owned_by_dma(struct ftmac100_txdes *txdes)
  378. {
  379. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  380. }
  381. static void ftmac100_txdes_set_dma_own(struct ftmac100_txdes *txdes)
  382. {
  383. /*
  384. * Make sure dma own bit will not be set before any other
  385. * descriptor fields.
  386. */
  387. wmb();
  388. txdes->txdes0 |= cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  389. }
  390. static bool ftmac100_txdes_excessive_collision(struct ftmac100_txdes *txdes)
  391. {
  392. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_EXSCOL);
  393. }
  394. static bool ftmac100_txdes_late_collision(struct ftmac100_txdes *txdes)
  395. {
  396. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_LATECOL);
  397. }
  398. static void ftmac100_txdes_set_end_of_ring(struct ftmac100_txdes *txdes)
  399. {
  400. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  401. }
  402. static void ftmac100_txdes_set_first_segment(struct ftmac100_txdes *txdes)
  403. {
  404. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_FTS);
  405. }
  406. static void ftmac100_txdes_set_last_segment(struct ftmac100_txdes *txdes)
  407. {
  408. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_LTS);
  409. }
  410. static void ftmac100_txdes_set_txint(struct ftmac100_txdes *txdes)
  411. {
  412. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXIC);
  413. }
  414. static void ftmac100_txdes_set_buffer_size(struct ftmac100_txdes *txdes,
  415. unsigned int len)
  416. {
  417. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXBUF_SIZE(len));
  418. }
  419. static void ftmac100_txdes_set_dma_addr(struct ftmac100_txdes *txdes,
  420. dma_addr_t addr)
  421. {
  422. txdes->txdes2 = cpu_to_le32(addr);
  423. }
  424. static dma_addr_t ftmac100_txdes_get_dma_addr(struct ftmac100_txdes *txdes)
  425. {
  426. return le32_to_cpu(txdes->txdes2);
  427. }
  428. /*
  429. * txdes3 is not used by hardware. We use it to keep track of socket buffer.
  430. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  431. */
  432. static void ftmac100_txdes_set_skb(struct ftmac100_txdes *txdes, struct sk_buff *skb)
  433. {
  434. txdes->txdes3 = (unsigned int)skb;
  435. }
  436. static struct sk_buff *ftmac100_txdes_get_skb(struct ftmac100_txdes *txdes)
  437. {
  438. return (struct sk_buff *)txdes->txdes3;
  439. }
  440. /******************************************************************************
  441. * internal functions (transmit)
  442. *****************************************************************************/
  443. static int ftmac100_next_tx_pointer(int pointer)
  444. {
  445. return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  446. }
  447. static void ftmac100_tx_pointer_advance(struct ftmac100 *priv)
  448. {
  449. priv->tx_pointer = ftmac100_next_tx_pointer(priv->tx_pointer);
  450. }
  451. static void ftmac100_tx_clean_pointer_advance(struct ftmac100 *priv)
  452. {
  453. priv->tx_clean_pointer = ftmac100_next_tx_pointer(priv->tx_clean_pointer);
  454. }
  455. static struct ftmac100_txdes *ftmac100_current_txdes(struct ftmac100 *priv)
  456. {
  457. return &priv->descs->txdes[priv->tx_pointer];
  458. }
  459. static struct ftmac100_txdes *ftmac100_current_clean_txdes(struct ftmac100 *priv)
  460. {
  461. return &priv->descs->txdes[priv->tx_clean_pointer];
  462. }
  463. static bool ftmac100_tx_complete_packet(struct ftmac100 *priv)
  464. {
  465. struct net_device *netdev = priv->netdev;
  466. struct ftmac100_txdes *txdes;
  467. struct sk_buff *skb;
  468. dma_addr_t map;
  469. if (priv->tx_pending == 0)
  470. return false;
  471. txdes = ftmac100_current_clean_txdes(priv);
  472. if (ftmac100_txdes_owned_by_dma(txdes))
  473. return false;
  474. skb = ftmac100_txdes_get_skb(txdes);
  475. map = ftmac100_txdes_get_dma_addr(txdes);
  476. if (unlikely(ftmac100_txdes_excessive_collision(txdes) ||
  477. ftmac100_txdes_late_collision(txdes))) {
  478. /*
  479. * packet transmitted to ethernet lost due to late collision
  480. * or excessive collision
  481. */
  482. netdev->stats.tx_aborted_errors++;
  483. } else {
  484. netdev->stats.tx_packets++;
  485. netdev->stats.tx_bytes += skb->len;
  486. }
  487. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  488. dev_kfree_skb(skb);
  489. ftmac100_txdes_reset(txdes);
  490. ftmac100_tx_clean_pointer_advance(priv);
  491. spin_lock(&priv->tx_lock);
  492. priv->tx_pending--;
  493. spin_unlock(&priv->tx_lock);
  494. netif_wake_queue(netdev);
  495. return true;
  496. }
  497. static void ftmac100_tx_complete(struct ftmac100 *priv)
  498. {
  499. while (ftmac100_tx_complete_packet(priv))
  500. ;
  501. }
  502. static int ftmac100_xmit(struct ftmac100 *priv, struct sk_buff *skb,
  503. dma_addr_t map)
  504. {
  505. struct net_device *netdev = priv->netdev;
  506. struct ftmac100_txdes *txdes;
  507. unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
  508. txdes = ftmac100_current_txdes(priv);
  509. ftmac100_tx_pointer_advance(priv);
  510. /* setup TX descriptor */
  511. ftmac100_txdes_set_skb(txdes, skb);
  512. ftmac100_txdes_set_dma_addr(txdes, map);
  513. ftmac100_txdes_set_first_segment(txdes);
  514. ftmac100_txdes_set_last_segment(txdes);
  515. ftmac100_txdes_set_txint(txdes);
  516. ftmac100_txdes_set_buffer_size(txdes, len);
  517. spin_lock(&priv->tx_lock);
  518. priv->tx_pending++;
  519. if (priv->tx_pending == TX_QUEUE_ENTRIES)
  520. netif_stop_queue(netdev);
  521. /* start transmit */
  522. ftmac100_txdes_set_dma_own(txdes);
  523. spin_unlock(&priv->tx_lock);
  524. ftmac100_txdma_start_polling(priv);
  525. return NETDEV_TX_OK;
  526. }
  527. /******************************************************************************
  528. * internal functions (buffer)
  529. *****************************************************************************/
  530. static int ftmac100_alloc_rx_page(struct ftmac100 *priv, struct ftmac100_rxdes *rxdes)
  531. {
  532. struct net_device *netdev = priv->netdev;
  533. struct page *page;
  534. dma_addr_t map;
  535. page = alloc_page(GFP_KERNEL);
  536. if (!page) {
  537. if (net_ratelimit())
  538. netdev_err(netdev, "failed to allocate rx page\n");
  539. return -ENOMEM;
  540. }
  541. map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
  542. if (unlikely(dma_mapping_error(priv->dev, map))) {
  543. if (net_ratelimit())
  544. netdev_err(netdev, "failed to map rx page\n");
  545. __free_page(page);
  546. return -ENOMEM;
  547. }
  548. ftmac100_rxdes_set_page(rxdes, page);
  549. ftmac100_rxdes_set_dma_addr(rxdes, map);
  550. ftmac100_rxdes_set_buffer_size(rxdes, RX_BUF_SIZE);
  551. ftmac100_rxdes_set_dma_own(rxdes);
  552. return 0;
  553. }
  554. static void ftmac100_free_buffers(struct ftmac100 *priv)
  555. {
  556. int i;
  557. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  558. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  559. struct page *page = ftmac100_rxdes_get_page(rxdes);
  560. dma_addr_t map = ftmac100_rxdes_get_dma_addr(rxdes);
  561. if (!page)
  562. continue;
  563. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  564. __free_page(page);
  565. }
  566. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  567. struct ftmac100_txdes *txdes = &priv->descs->txdes[i];
  568. struct sk_buff *skb = ftmac100_txdes_get_skb(txdes);
  569. dma_addr_t map = ftmac100_txdes_get_dma_addr(txdes);
  570. if (!skb)
  571. continue;
  572. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  573. dev_kfree_skb(skb);
  574. }
  575. dma_free_coherent(priv->dev, sizeof(struct ftmac100_descs),
  576. priv->descs, priv->descs_dma_addr);
  577. }
  578. static int ftmac100_alloc_buffers(struct ftmac100 *priv)
  579. {
  580. int i;
  581. priv->descs = dma_alloc_coherent(priv->dev, sizeof(struct ftmac100_descs),
  582. &priv->descs_dma_addr, GFP_KERNEL);
  583. if (!priv->descs)
  584. return -ENOMEM;
  585. memset(priv->descs, 0, sizeof(struct ftmac100_descs));
  586. /* initialize RX ring */
  587. ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
  588. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  589. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  590. if (ftmac100_alloc_rx_page(priv, rxdes))
  591. goto err;
  592. }
  593. /* initialize TX ring */
  594. ftmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
  595. return 0;
  596. err:
  597. ftmac100_free_buffers(priv);
  598. return -ENOMEM;
  599. }
  600. /******************************************************************************
  601. * struct mii_if_info functions
  602. *****************************************************************************/
  603. static int ftmac100_mdio_read(struct net_device *netdev, int phy_id, int reg)
  604. {
  605. struct ftmac100 *priv = netdev_priv(netdev);
  606. unsigned int phycr;
  607. int i;
  608. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  609. FTMAC100_PHYCR_REGAD(reg) |
  610. FTMAC100_PHYCR_MIIRD;
  611. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  612. for (i = 0; i < 10; i++) {
  613. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  614. if ((phycr & FTMAC100_PHYCR_MIIRD) == 0)
  615. return phycr & FTMAC100_PHYCR_MIIRDATA;
  616. usleep_range(100, 1000);
  617. }
  618. netdev_err(netdev, "mdio read timed out\n");
  619. return 0;
  620. }
  621. static void ftmac100_mdio_write(struct net_device *netdev, int phy_id, int reg,
  622. int data)
  623. {
  624. struct ftmac100 *priv = netdev_priv(netdev);
  625. unsigned int phycr;
  626. int i;
  627. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  628. FTMAC100_PHYCR_REGAD(reg) |
  629. FTMAC100_PHYCR_MIIWR;
  630. data = FTMAC100_PHYWDATA_MIIWDATA(data);
  631. iowrite32(data, priv->base + FTMAC100_OFFSET_PHYWDATA);
  632. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  633. for (i = 0; i < 10; i++) {
  634. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  635. if ((phycr & FTMAC100_PHYCR_MIIWR) == 0)
  636. return;
  637. usleep_range(100, 1000);
  638. }
  639. netdev_err(netdev, "mdio write timed out\n");
  640. }
  641. /******************************************************************************
  642. * struct ethtool_ops functions
  643. *****************************************************************************/
  644. static void ftmac100_get_drvinfo(struct net_device *netdev,
  645. struct ethtool_drvinfo *info)
  646. {
  647. strcpy(info->driver, DRV_NAME);
  648. strcpy(info->version, DRV_VERSION);
  649. strcpy(info->bus_info, dev_name(&netdev->dev));
  650. }
  651. static int ftmac100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  652. {
  653. struct ftmac100 *priv = netdev_priv(netdev);
  654. return mii_ethtool_gset(&priv->mii, cmd);
  655. }
  656. static int ftmac100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  657. {
  658. struct ftmac100 *priv = netdev_priv(netdev);
  659. return mii_ethtool_sset(&priv->mii, cmd);
  660. }
  661. static int ftmac100_nway_reset(struct net_device *netdev)
  662. {
  663. struct ftmac100 *priv = netdev_priv(netdev);
  664. return mii_nway_restart(&priv->mii);
  665. }
  666. static u32 ftmac100_get_link(struct net_device *netdev)
  667. {
  668. struct ftmac100 *priv = netdev_priv(netdev);
  669. return mii_link_ok(&priv->mii);
  670. }
  671. static const struct ethtool_ops ftmac100_ethtool_ops = {
  672. .set_settings = ftmac100_set_settings,
  673. .get_settings = ftmac100_get_settings,
  674. .get_drvinfo = ftmac100_get_drvinfo,
  675. .nway_reset = ftmac100_nway_reset,
  676. .get_link = ftmac100_get_link,
  677. };
  678. /******************************************************************************
  679. * interrupt handler
  680. *****************************************************************************/
  681. static irqreturn_t ftmac100_interrupt(int irq, void *dev_id)
  682. {
  683. struct net_device *netdev = dev_id;
  684. struct ftmac100 *priv = netdev_priv(netdev);
  685. if (likely(netif_running(netdev))) {
  686. /* Disable interrupts for polling */
  687. ftmac100_disable_all_int(priv);
  688. napi_schedule(&priv->napi);
  689. }
  690. return IRQ_HANDLED;
  691. }
  692. /******************************************************************************
  693. * struct napi_struct functions
  694. *****************************************************************************/
  695. static int ftmac100_poll(struct napi_struct *napi, int budget)
  696. {
  697. struct ftmac100 *priv = container_of(napi, struct ftmac100, napi);
  698. struct net_device *netdev = priv->netdev;
  699. unsigned int status;
  700. bool completed = true;
  701. int rx = 0;
  702. status = ioread32(priv->base + FTMAC100_OFFSET_ISR);
  703. if (status & (FTMAC100_INT_RPKT_FINISH | FTMAC100_INT_NORXBUF)) {
  704. /*
  705. * FTMAC100_INT_RPKT_FINISH:
  706. * RX DMA has received packets into RX buffer successfully
  707. *
  708. * FTMAC100_INT_NORXBUF:
  709. * RX buffer unavailable
  710. */
  711. bool retry;
  712. do {
  713. retry = ftmac100_rx_packet(priv, &rx);
  714. } while (retry && rx < budget);
  715. if (retry && rx == budget)
  716. completed = false;
  717. }
  718. if (status & (FTMAC100_INT_XPKT_OK | FTMAC100_INT_XPKT_LOST)) {
  719. /*
  720. * FTMAC100_INT_XPKT_OK:
  721. * packet transmitted to ethernet successfully
  722. *
  723. * FTMAC100_INT_XPKT_LOST:
  724. * packet transmitted to ethernet lost due to late
  725. * collision or excessive collision
  726. */
  727. ftmac100_tx_complete(priv);
  728. }
  729. if (status & (FTMAC100_INT_NORXBUF | FTMAC100_INT_RPKT_LOST |
  730. FTMAC100_INT_AHB_ERR | FTMAC100_INT_PHYSTS_CHG)) {
  731. if (net_ratelimit())
  732. netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
  733. status & FTMAC100_INT_NORXBUF ? "NORXBUF " : "",
  734. status & FTMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
  735. status & FTMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
  736. status & FTMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
  737. if (status & FTMAC100_INT_NORXBUF) {
  738. /* RX buffer unavailable */
  739. netdev->stats.rx_over_errors++;
  740. }
  741. if (status & FTMAC100_INT_RPKT_LOST) {
  742. /* received packet lost due to RX FIFO full */
  743. netdev->stats.rx_fifo_errors++;
  744. }
  745. if (status & FTMAC100_INT_PHYSTS_CHG) {
  746. /* PHY link status change */
  747. mii_check_link(&priv->mii);
  748. }
  749. }
  750. if (completed) {
  751. /* stop polling */
  752. napi_complete(napi);
  753. ftmac100_enable_all_int(priv);
  754. }
  755. return rx;
  756. }
  757. /******************************************************************************
  758. * struct net_device_ops functions
  759. *****************************************************************************/
  760. static int ftmac100_open(struct net_device *netdev)
  761. {
  762. struct ftmac100 *priv = netdev_priv(netdev);
  763. int err;
  764. err = ftmac100_alloc_buffers(priv);
  765. if (err) {
  766. netdev_err(netdev, "failed to allocate buffers\n");
  767. goto err_alloc;
  768. }
  769. err = request_irq(priv->irq, ftmac100_interrupt, 0, netdev->name, netdev);
  770. if (err) {
  771. netdev_err(netdev, "failed to request irq %d\n", priv->irq);
  772. goto err_irq;
  773. }
  774. priv->rx_pointer = 0;
  775. priv->tx_clean_pointer = 0;
  776. priv->tx_pointer = 0;
  777. priv->tx_pending = 0;
  778. err = ftmac100_start_hw(priv);
  779. if (err)
  780. goto err_hw;
  781. napi_enable(&priv->napi);
  782. netif_start_queue(netdev);
  783. ftmac100_enable_all_int(priv);
  784. return 0;
  785. err_hw:
  786. free_irq(priv->irq, netdev);
  787. err_irq:
  788. ftmac100_free_buffers(priv);
  789. err_alloc:
  790. return err;
  791. }
  792. static int ftmac100_stop(struct net_device *netdev)
  793. {
  794. struct ftmac100 *priv = netdev_priv(netdev);
  795. ftmac100_disable_all_int(priv);
  796. netif_stop_queue(netdev);
  797. napi_disable(&priv->napi);
  798. ftmac100_stop_hw(priv);
  799. free_irq(priv->irq, netdev);
  800. ftmac100_free_buffers(priv);
  801. return 0;
  802. }
  803. static int ftmac100_hard_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  804. {
  805. struct ftmac100 *priv = netdev_priv(netdev);
  806. dma_addr_t map;
  807. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  808. if (net_ratelimit())
  809. netdev_dbg(netdev, "tx packet too big\n");
  810. netdev->stats.tx_dropped++;
  811. dev_kfree_skb(skb);
  812. return NETDEV_TX_OK;
  813. }
  814. map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
  815. if (unlikely(dma_mapping_error(priv->dev, map))) {
  816. /* drop packet */
  817. if (net_ratelimit())
  818. netdev_err(netdev, "map socket buffer failed\n");
  819. netdev->stats.tx_dropped++;
  820. dev_kfree_skb(skb);
  821. return NETDEV_TX_OK;
  822. }
  823. return ftmac100_xmit(priv, skb, map);
  824. }
  825. /* optional */
  826. static int ftmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  827. {
  828. struct ftmac100 *priv = netdev_priv(netdev);
  829. struct mii_ioctl_data *data = if_mii(ifr);
  830. return generic_mii_ioctl(&priv->mii, data, cmd, NULL);
  831. }
  832. static const struct net_device_ops ftmac100_netdev_ops = {
  833. .ndo_open = ftmac100_open,
  834. .ndo_stop = ftmac100_stop,
  835. .ndo_start_xmit = ftmac100_hard_start_xmit,
  836. .ndo_set_mac_address = eth_mac_addr,
  837. .ndo_validate_addr = eth_validate_addr,
  838. .ndo_do_ioctl = ftmac100_do_ioctl,
  839. };
  840. /******************************************************************************
  841. * struct platform_driver functions
  842. *****************************************************************************/
  843. static int ftmac100_probe(struct platform_device *pdev)
  844. {
  845. struct resource *res;
  846. int irq;
  847. struct net_device *netdev;
  848. struct ftmac100 *priv;
  849. int err;
  850. if (!pdev)
  851. return -ENODEV;
  852. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  853. if (!res)
  854. return -ENXIO;
  855. irq = platform_get_irq(pdev, 0);
  856. if (irq < 0)
  857. return irq;
  858. /* setup net_device */
  859. netdev = alloc_etherdev(sizeof(*priv));
  860. if (!netdev) {
  861. err = -ENOMEM;
  862. goto err_alloc_etherdev;
  863. }
  864. SET_NETDEV_DEV(netdev, &pdev->dev);
  865. SET_ETHTOOL_OPS(netdev, &ftmac100_ethtool_ops);
  866. netdev->netdev_ops = &ftmac100_netdev_ops;
  867. platform_set_drvdata(pdev, netdev);
  868. /* setup private data */
  869. priv = netdev_priv(netdev);
  870. priv->netdev = netdev;
  871. priv->dev = &pdev->dev;
  872. spin_lock_init(&priv->tx_lock);
  873. /* initialize NAPI */
  874. netif_napi_add(netdev, &priv->napi, ftmac100_poll, 64);
  875. /* map io memory */
  876. priv->res = request_mem_region(res->start, resource_size(res),
  877. dev_name(&pdev->dev));
  878. if (!priv->res) {
  879. dev_err(&pdev->dev, "Could not reserve memory region\n");
  880. err = -ENOMEM;
  881. goto err_req_mem;
  882. }
  883. priv->base = ioremap(res->start, res->end - res->start);
  884. if (!priv->base) {
  885. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  886. err = -EIO;
  887. goto err_ioremap;
  888. }
  889. priv->irq = irq;
  890. /* initialize struct mii_if_info */
  891. priv->mii.phy_id = 0;
  892. priv->mii.phy_id_mask = 0x1f;
  893. priv->mii.reg_num_mask = 0x1f;
  894. priv->mii.dev = netdev;
  895. priv->mii.mdio_read = ftmac100_mdio_read;
  896. priv->mii.mdio_write = ftmac100_mdio_write;
  897. /* register network device */
  898. err = register_netdev(netdev);
  899. if (err) {
  900. dev_err(&pdev->dev, "Failed to register netdev\n");
  901. goto err_register_netdev;
  902. }
  903. netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
  904. if (!is_valid_ether_addr(netdev->dev_addr)) {
  905. random_ether_addr(netdev->dev_addr);
  906. netdev_info(netdev, "generated random MAC address %pM\n",
  907. netdev->dev_addr);
  908. }
  909. return 0;
  910. err_register_netdev:
  911. iounmap(priv->base);
  912. err_ioremap:
  913. release_resource(priv->res);
  914. err_req_mem:
  915. netif_napi_del(&priv->napi);
  916. platform_set_drvdata(pdev, NULL);
  917. free_netdev(netdev);
  918. err_alloc_etherdev:
  919. return err;
  920. }
  921. static int __exit ftmac100_remove(struct platform_device *pdev)
  922. {
  923. struct net_device *netdev;
  924. struct ftmac100 *priv;
  925. netdev = platform_get_drvdata(pdev);
  926. priv = netdev_priv(netdev);
  927. unregister_netdev(netdev);
  928. iounmap(priv->base);
  929. release_resource(priv->res);
  930. netif_napi_del(&priv->napi);
  931. platform_set_drvdata(pdev, NULL);
  932. free_netdev(netdev);
  933. return 0;
  934. }
  935. static struct platform_driver ftmac100_driver = {
  936. .probe = ftmac100_probe,
  937. .remove = __exit_p(ftmac100_remove),
  938. .driver = {
  939. .name = DRV_NAME,
  940. .owner = THIS_MODULE,
  941. },
  942. };
  943. /******************************************************************************
  944. * initialization / finalization
  945. *****************************************************************************/
  946. static int __init ftmac100_init(void)
  947. {
  948. pr_info("Loading version " DRV_VERSION " ...\n");
  949. return platform_driver_register(&ftmac100_driver);
  950. }
  951. static void __exit ftmac100_exit(void)
  952. {
  953. platform_driver_unregister(&ftmac100_driver);
  954. }
  955. module_init(ftmac100_init);
  956. module_exit(ftmac100_exit);
  957. MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
  958. MODULE_DESCRIPTION("FTMAC100 driver");
  959. MODULE_LICENSE("GPL");