iwl-agn-lib.c 70 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394
  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/sched.h>
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-helpers.h"
  38. #include "iwl-agn-hw.h"
  39. #include "iwl-agn.h"
  40. #include "iwl-sta.h"
  41. static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  42. {
  43. return le32_to_cpup((__le32 *)&tx_resp->status +
  44. tx_resp->frame_count) & MAX_SN;
  45. }
  46. static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  47. {
  48. status &= TX_STATUS_MSK;
  49. switch (status) {
  50. case TX_STATUS_POSTPONE_DELAY:
  51. priv->_agn.reply_tx_stats.pp_delay++;
  52. break;
  53. case TX_STATUS_POSTPONE_FEW_BYTES:
  54. priv->_agn.reply_tx_stats.pp_few_bytes++;
  55. break;
  56. case TX_STATUS_POSTPONE_BT_PRIO:
  57. priv->_agn.reply_tx_stats.pp_bt_prio++;
  58. break;
  59. case TX_STATUS_POSTPONE_QUIET_PERIOD:
  60. priv->_agn.reply_tx_stats.pp_quiet_period++;
  61. break;
  62. case TX_STATUS_POSTPONE_CALC_TTAK:
  63. priv->_agn.reply_tx_stats.pp_calc_ttak++;
  64. break;
  65. case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  66. priv->_agn.reply_tx_stats.int_crossed_retry++;
  67. break;
  68. case TX_STATUS_FAIL_SHORT_LIMIT:
  69. priv->_agn.reply_tx_stats.short_limit++;
  70. break;
  71. case TX_STATUS_FAIL_LONG_LIMIT:
  72. priv->_agn.reply_tx_stats.long_limit++;
  73. break;
  74. case TX_STATUS_FAIL_FIFO_UNDERRUN:
  75. priv->_agn.reply_tx_stats.fifo_underrun++;
  76. break;
  77. case TX_STATUS_FAIL_DRAIN_FLOW:
  78. priv->_agn.reply_tx_stats.drain_flow++;
  79. break;
  80. case TX_STATUS_FAIL_RFKILL_FLUSH:
  81. priv->_agn.reply_tx_stats.rfkill_flush++;
  82. break;
  83. case TX_STATUS_FAIL_LIFE_EXPIRE:
  84. priv->_agn.reply_tx_stats.life_expire++;
  85. break;
  86. case TX_STATUS_FAIL_DEST_PS:
  87. priv->_agn.reply_tx_stats.dest_ps++;
  88. break;
  89. case TX_STATUS_FAIL_HOST_ABORTED:
  90. priv->_agn.reply_tx_stats.host_abort++;
  91. break;
  92. case TX_STATUS_FAIL_BT_RETRY:
  93. priv->_agn.reply_tx_stats.bt_retry++;
  94. break;
  95. case TX_STATUS_FAIL_STA_INVALID:
  96. priv->_agn.reply_tx_stats.sta_invalid++;
  97. break;
  98. case TX_STATUS_FAIL_FRAG_DROPPED:
  99. priv->_agn.reply_tx_stats.frag_drop++;
  100. break;
  101. case TX_STATUS_FAIL_TID_DISABLE:
  102. priv->_agn.reply_tx_stats.tid_disable++;
  103. break;
  104. case TX_STATUS_FAIL_FIFO_FLUSHED:
  105. priv->_agn.reply_tx_stats.fifo_flush++;
  106. break;
  107. case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
  108. priv->_agn.reply_tx_stats.insuff_cf_poll++;
  109. break;
  110. case TX_STATUS_FAIL_PASSIVE_NO_RX:
  111. priv->_agn.reply_tx_stats.fail_hw_drop++;
  112. break;
  113. case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
  114. priv->_agn.reply_tx_stats.sta_color_mismatch++;
  115. break;
  116. default:
  117. priv->_agn.reply_tx_stats.unknown++;
  118. break;
  119. }
  120. }
  121. static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
  122. {
  123. status &= AGG_TX_STATUS_MSK;
  124. switch (status) {
  125. case AGG_TX_STATE_UNDERRUN_MSK:
  126. priv->_agn.reply_agg_tx_stats.underrun++;
  127. break;
  128. case AGG_TX_STATE_BT_PRIO_MSK:
  129. priv->_agn.reply_agg_tx_stats.bt_prio++;
  130. break;
  131. case AGG_TX_STATE_FEW_BYTES_MSK:
  132. priv->_agn.reply_agg_tx_stats.few_bytes++;
  133. break;
  134. case AGG_TX_STATE_ABORT_MSK:
  135. priv->_agn.reply_agg_tx_stats.abort++;
  136. break;
  137. case AGG_TX_STATE_LAST_SENT_TTL_MSK:
  138. priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
  139. break;
  140. case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
  141. priv->_agn.reply_agg_tx_stats.last_sent_try++;
  142. break;
  143. case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
  144. priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
  145. break;
  146. case AGG_TX_STATE_SCD_QUERY_MSK:
  147. priv->_agn.reply_agg_tx_stats.scd_query++;
  148. break;
  149. case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
  150. priv->_agn.reply_agg_tx_stats.bad_crc32++;
  151. break;
  152. case AGG_TX_STATE_RESPONSE_MSK:
  153. priv->_agn.reply_agg_tx_stats.response++;
  154. break;
  155. case AGG_TX_STATE_DUMP_TX_MSK:
  156. priv->_agn.reply_agg_tx_stats.dump_tx++;
  157. break;
  158. case AGG_TX_STATE_DELAY_TX_MSK:
  159. priv->_agn.reply_agg_tx_stats.delay_tx++;
  160. break;
  161. default:
  162. priv->_agn.reply_agg_tx_stats.unknown++;
  163. break;
  164. }
  165. }
  166. static void iwlagn_set_tx_status(struct iwl_priv *priv,
  167. struct ieee80211_tx_info *info,
  168. struct iwlagn_tx_resp *tx_resp,
  169. int txq_id, bool is_agg)
  170. {
  171. u16 status = le16_to_cpu(tx_resp->status.status);
  172. info->status.rates[0].count = tx_resp->failure_frame + 1;
  173. if (is_agg)
  174. info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  175. info->flags |= iwl_tx_status_to_mac80211(status);
  176. iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
  177. info);
  178. if (!iwl_is_tx_success(status))
  179. iwlagn_count_tx_err_status(priv, status);
  180. IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
  181. "0x%x retries %d\n",
  182. txq_id,
  183. iwl_get_tx_fail_reason(status), status,
  184. le32_to_cpu(tx_resp->rate_n_flags),
  185. tx_resp->failure_frame);
  186. }
  187. #ifdef CONFIG_IWLWIFI_DEBUG
  188. #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
  189. const char *iwl_get_agg_tx_fail_reason(u16 status)
  190. {
  191. status &= AGG_TX_STATUS_MSK;
  192. switch (status) {
  193. case AGG_TX_STATE_TRANSMITTED:
  194. return "SUCCESS";
  195. AGG_TX_STATE_FAIL(UNDERRUN_MSK);
  196. AGG_TX_STATE_FAIL(BT_PRIO_MSK);
  197. AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
  198. AGG_TX_STATE_FAIL(ABORT_MSK);
  199. AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
  200. AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
  201. AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
  202. AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
  203. AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
  204. AGG_TX_STATE_FAIL(RESPONSE_MSK);
  205. AGG_TX_STATE_FAIL(DUMP_TX_MSK);
  206. AGG_TX_STATE_FAIL(DELAY_TX_MSK);
  207. }
  208. return "UNKNOWN";
  209. }
  210. #endif /* CONFIG_IWLWIFI_DEBUG */
  211. static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
  212. struct iwl_ht_agg *agg,
  213. struct iwlagn_tx_resp *tx_resp,
  214. int txq_id, u16 start_idx)
  215. {
  216. u16 status;
  217. struct agg_tx_status *frame_status = &tx_resp->status;
  218. struct ieee80211_hdr *hdr = NULL;
  219. int i, sh, idx;
  220. u16 seq;
  221. if (agg->wait_for_ba)
  222. IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
  223. agg->frame_count = tx_resp->frame_count;
  224. agg->start_idx = start_idx;
  225. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  226. agg->bitmap = 0;
  227. /* # frames attempted by Tx command */
  228. if (agg->frame_count == 1) {
  229. /* Only one frame was attempted; no block-ack will arrive */
  230. idx = start_idx;
  231. IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
  232. agg->frame_count, agg->start_idx, idx);
  233. iwlagn_set_tx_status(priv,
  234. IEEE80211_SKB_CB(
  235. priv->txq[txq_id].txb[idx].skb),
  236. tx_resp, txq_id, true);
  237. agg->wait_for_ba = 0;
  238. } else {
  239. /* Two or more frames were attempted; expect block-ack */
  240. u64 bitmap = 0;
  241. /*
  242. * Start is the lowest frame sent. It may not be the first
  243. * frame in the batch; we figure this out dynamically during
  244. * the following loop.
  245. */
  246. int start = agg->start_idx;
  247. /* Construct bit-map of pending frames within Tx window */
  248. for (i = 0; i < agg->frame_count; i++) {
  249. u16 sc;
  250. status = le16_to_cpu(frame_status[i].status);
  251. seq = le16_to_cpu(frame_status[i].sequence);
  252. idx = SEQ_TO_INDEX(seq);
  253. txq_id = SEQ_TO_QUEUE(seq);
  254. if (status & AGG_TX_STATUS_MSK)
  255. iwlagn_count_agg_tx_err_status(priv, status);
  256. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  257. AGG_TX_STATE_ABORT_MSK))
  258. continue;
  259. IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
  260. agg->frame_count, txq_id, idx);
  261. IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
  262. "try-count (0x%08x)\n",
  263. iwl_get_agg_tx_fail_reason(status),
  264. status & AGG_TX_STATUS_MSK,
  265. status & AGG_TX_TRY_MSK);
  266. hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
  267. if (!hdr) {
  268. IWL_ERR(priv,
  269. "BUG_ON idx doesn't point to valid skb"
  270. " idx=%d, txq_id=%d\n", idx, txq_id);
  271. return -1;
  272. }
  273. sc = le16_to_cpu(hdr->seq_ctrl);
  274. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  275. IWL_ERR(priv,
  276. "BUG_ON idx doesn't match seq control"
  277. " idx=%d, seq_idx=%d, seq=%d\n",
  278. idx, SEQ_TO_SN(sc),
  279. hdr->seq_ctrl);
  280. return -1;
  281. }
  282. IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
  283. i, idx, SEQ_TO_SN(sc));
  284. /*
  285. * sh -> how many frames ahead of the starting frame is
  286. * the current one?
  287. *
  288. * Note that all frames sent in the batch must be in a
  289. * 64-frame window, so this number should be in [0,63].
  290. * If outside of this window, then we've found a new
  291. * "first" frame in the batch and need to change start.
  292. */
  293. sh = idx - start;
  294. /*
  295. * If >= 64, out of window. start must be at the front
  296. * of the circular buffer, idx must be near the end of
  297. * the buffer, and idx is the new "first" frame. Shift
  298. * the indices around.
  299. */
  300. if (sh >= 64) {
  301. /* Shift bitmap by start - idx, wrapped */
  302. sh = 0x100 - idx + start;
  303. bitmap = bitmap << sh;
  304. /* Now idx is the new start so sh = 0 */
  305. sh = 0;
  306. start = idx;
  307. /*
  308. * If <= -64 then wraps the 256-pkt circular buffer
  309. * (e.g., start = 255 and idx = 0, sh should be 1)
  310. */
  311. } else if (sh <= -64) {
  312. sh = 0x100 - start + idx;
  313. /*
  314. * If < 0 but > -64, out of window. idx is before start
  315. * but not wrapped. Shift the indices around.
  316. */
  317. } else if (sh < 0) {
  318. /* Shift by how far start is ahead of idx */
  319. sh = start - idx;
  320. bitmap = bitmap << sh;
  321. /* Now idx is the new start so sh = 0 */
  322. start = idx;
  323. sh = 0;
  324. }
  325. /* Sequence number start + sh was sent in this batch */
  326. bitmap |= 1ULL << sh;
  327. IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
  328. start, (unsigned long long)bitmap);
  329. }
  330. /*
  331. * Store the bitmap and possibly the new start, if we wrapped
  332. * the buffer above
  333. */
  334. agg->bitmap = bitmap;
  335. agg->start_idx = start;
  336. IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
  337. agg->frame_count, agg->start_idx,
  338. (unsigned long long)agg->bitmap);
  339. if (bitmap)
  340. agg->wait_for_ba = 1;
  341. }
  342. return 0;
  343. }
  344. void iwl_check_abort_status(struct iwl_priv *priv,
  345. u8 frame_count, u32 status)
  346. {
  347. if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
  348. IWL_ERR(priv, "Tx flush command to flush out all frames\n");
  349. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  350. queue_work(priv->workqueue, &priv->tx_flush);
  351. }
  352. }
  353. static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
  354. struct iwl_rx_mem_buffer *rxb)
  355. {
  356. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  357. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  358. int txq_id = SEQ_TO_QUEUE(sequence);
  359. int index = SEQ_TO_INDEX(sequence);
  360. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  361. struct ieee80211_tx_info *info;
  362. struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  363. u32 status = le16_to_cpu(tx_resp->status.status);
  364. int tid;
  365. int sta_id;
  366. int freed;
  367. unsigned long flags;
  368. if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
  369. IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
  370. "is out of range [0-%d] %d %d\n", txq_id,
  371. index, txq->q.n_bd, txq->q.write_ptr,
  372. txq->q.read_ptr);
  373. return;
  374. }
  375. txq->time_stamp = jiffies;
  376. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
  377. memset(&info->status, 0, sizeof(info->status));
  378. tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
  379. IWLAGN_TX_RES_TID_POS;
  380. sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
  381. IWLAGN_TX_RES_RA_POS;
  382. spin_lock_irqsave(&priv->sta_lock, flags);
  383. if (txq->sched_retry) {
  384. const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
  385. struct iwl_ht_agg *agg;
  386. agg = &priv->stations[sta_id].tid[tid].agg;
  387. /*
  388. * If the BT kill count is non-zero, we'll get this
  389. * notification again.
  390. */
  391. if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
  392. priv->cfg->bt_params &&
  393. priv->cfg->bt_params->advanced_bt_coexist) {
  394. IWL_WARN(priv, "receive reply tx with bt_kill\n");
  395. }
  396. iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
  397. /* check if BAR is needed */
  398. if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
  399. info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  400. if (txq->q.read_ptr != (scd_ssn & 0xff)) {
  401. index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  402. IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
  403. "scd_ssn=%d idx=%d txq=%d swq=%d\n",
  404. scd_ssn , index, txq_id, txq->swq_id);
  405. freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
  406. iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
  407. if (priv->mac80211_registered &&
  408. (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
  409. (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
  410. iwl_wake_queue(priv, txq);
  411. }
  412. } else {
  413. iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
  414. freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
  415. iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
  416. if (priv->mac80211_registered &&
  417. (iwl_queue_space(&txq->q) > txq->q.low_mark))
  418. iwl_wake_queue(priv, txq);
  419. }
  420. iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
  421. iwl_check_abort_status(priv, tx_resp->frame_count, status);
  422. spin_unlock_irqrestore(&priv->sta_lock, flags);
  423. }
  424. void iwlagn_rx_handler_setup(struct iwl_priv *priv)
  425. {
  426. /* init calibration handlers */
  427. priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
  428. iwlagn_rx_calib_result;
  429. priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
  430. iwlagn_rx_calib_complete;
  431. priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
  432. }
  433. void iwlagn_setup_deferred_work(struct iwl_priv *priv)
  434. {
  435. /* in agn, the tx power calibration is done in uCode */
  436. priv->disable_tx_power_cal = 1;
  437. }
  438. int iwlagn_hw_valid_rtc_data_addr(u32 addr)
  439. {
  440. return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
  441. (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
  442. }
  443. int iwlagn_send_tx_power(struct iwl_priv *priv)
  444. {
  445. struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
  446. u8 tx_ant_cfg_cmd;
  447. if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
  448. "TX Power requested while scanning!\n"))
  449. return -EAGAIN;
  450. /* half dBm need to multiply */
  451. tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
  452. if (priv->tx_power_lmt_in_half_dbm &&
  453. priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
  454. /*
  455. * For the newer devices which using enhanced/extend tx power
  456. * table in EEPROM, the format is in half dBm. driver need to
  457. * convert to dBm format before report to mac80211.
  458. * By doing so, there is a possibility of 1/2 dBm resolution
  459. * lost. driver will perform "round-up" operation before
  460. * reporting, but it will cause 1/2 dBm tx power over the
  461. * regulatory limit. Perform the checking here, if the
  462. * "tx_power_user_lmt" is higher than EEPROM value (in
  463. * half-dBm format), lower the tx power based on EEPROM
  464. */
  465. tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
  466. }
  467. tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
  468. tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
  469. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  470. tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
  471. else
  472. tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
  473. return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
  474. &tx_power_cmd);
  475. }
  476. void iwlagn_temperature(struct iwl_priv *priv)
  477. {
  478. /* store temperature from statistics (in Celsius) */
  479. priv->temperature =
  480. le32_to_cpu(priv->_agn.statistics.general.common.temperature);
  481. iwl_tt_handler(priv);
  482. }
  483. u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
  484. {
  485. struct iwl_eeprom_calib_hdr {
  486. u8 version;
  487. u8 pa_type;
  488. u16 voltage;
  489. } *hdr;
  490. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
  491. EEPROM_CALIB_ALL);
  492. return hdr->version;
  493. }
  494. /*
  495. * EEPROM
  496. */
  497. static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
  498. {
  499. u16 offset = 0;
  500. if ((address & INDIRECT_ADDRESS) == 0)
  501. return address;
  502. switch (address & INDIRECT_TYPE_MSK) {
  503. case INDIRECT_HOST:
  504. offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
  505. break;
  506. case INDIRECT_GENERAL:
  507. offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
  508. break;
  509. case INDIRECT_REGULATORY:
  510. offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
  511. break;
  512. case INDIRECT_TXP_LIMIT:
  513. offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
  514. break;
  515. case INDIRECT_TXP_LIMIT_SIZE:
  516. offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
  517. break;
  518. case INDIRECT_CALIBRATION:
  519. offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
  520. break;
  521. case INDIRECT_PROCESS_ADJST:
  522. offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
  523. break;
  524. case INDIRECT_OTHERS:
  525. offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
  526. break;
  527. default:
  528. IWL_ERR(priv, "illegal indirect type: 0x%X\n",
  529. address & INDIRECT_TYPE_MSK);
  530. break;
  531. }
  532. /* translate the offset from words to byte */
  533. return (address & ADDRESS_MSK) + (offset << 1);
  534. }
  535. const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
  536. size_t offset)
  537. {
  538. u32 address = eeprom_indirect_address(priv, offset);
  539. BUG_ON(address >= priv->cfg->base_params->eeprom_size);
  540. return &priv->eeprom[address];
  541. }
  542. struct iwl_mod_params iwlagn_mod_params = {
  543. .amsdu_size_8K = 1,
  544. .restart_fw = 1,
  545. /* the rest are 0 by default */
  546. };
  547. void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  548. {
  549. unsigned long flags;
  550. int i;
  551. spin_lock_irqsave(&rxq->lock, flags);
  552. INIT_LIST_HEAD(&rxq->rx_free);
  553. INIT_LIST_HEAD(&rxq->rx_used);
  554. /* Fill the rx_used queue with _all_ of the Rx buffers */
  555. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  556. /* In the reset function, these buffers may have been allocated
  557. * to an SKB, so we need to unmap and free potential storage */
  558. if (rxq->pool[i].page != NULL) {
  559. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  560. PAGE_SIZE << priv->hw_params.rx_page_order,
  561. PCI_DMA_FROMDEVICE);
  562. __iwl_free_pages(priv, rxq->pool[i].page);
  563. rxq->pool[i].page = NULL;
  564. }
  565. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  566. }
  567. for (i = 0; i < RX_QUEUE_SIZE; i++)
  568. rxq->queue[i] = NULL;
  569. /* Set us so that we have processed and used all buffers, but have
  570. * not restocked the Rx queue with fresh buffers */
  571. rxq->read = rxq->write = 0;
  572. rxq->write_actual = 0;
  573. rxq->free_count = 0;
  574. spin_unlock_irqrestore(&rxq->lock, flags);
  575. }
  576. int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  577. {
  578. u32 rb_size;
  579. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  580. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  581. if (!priv->cfg->base_params->use_isr_legacy)
  582. rb_timeout = RX_RB_TIMEOUT;
  583. if (priv->cfg->mod_params->amsdu_size_8K)
  584. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  585. else
  586. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  587. /* Stop Rx DMA */
  588. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  589. /* Reset driver's Rx queue write index */
  590. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  591. /* Tell device where to find RBD circular buffer in DRAM */
  592. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  593. (u32)(rxq->bd_dma >> 8));
  594. /* Tell device where in DRAM to update its Rx status */
  595. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  596. rxq->rb_stts_dma >> 4);
  597. /* Enable Rx DMA
  598. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  599. * the credit mechanism in 5000 HW RX FIFO
  600. * Direct rx interrupts to hosts
  601. * Rx buffer size 4 or 8k
  602. * RB timeout 0x10
  603. * 256 RBDs
  604. */
  605. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  606. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  607. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  608. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  609. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  610. rb_size|
  611. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  612. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  613. /* Set interrupt coalescing timer to default (2048 usecs) */
  614. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
  615. return 0;
  616. }
  617. static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
  618. {
  619. /*
  620. * (for documentation purposes)
  621. * to set power to V_AUX, do:
  622. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  623. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  624. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  625. ~APMG_PS_CTRL_MSK_PWR_SRC);
  626. */
  627. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  628. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  629. ~APMG_PS_CTRL_MSK_PWR_SRC);
  630. }
  631. int iwlagn_hw_nic_init(struct iwl_priv *priv)
  632. {
  633. unsigned long flags;
  634. struct iwl_rx_queue *rxq = &priv->rxq;
  635. int ret;
  636. /* nic_init */
  637. spin_lock_irqsave(&priv->lock, flags);
  638. priv->cfg->ops->lib->apm_ops.init(priv);
  639. /* Set interrupt coalescing calibration timer to default (512 usecs) */
  640. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
  641. spin_unlock_irqrestore(&priv->lock, flags);
  642. iwlagn_set_pwr_vmain(priv);
  643. priv->cfg->ops->lib->apm_ops.config(priv);
  644. /* Allocate the RX queue, or reset if it is already allocated */
  645. if (!rxq->bd) {
  646. ret = iwl_rx_queue_alloc(priv);
  647. if (ret) {
  648. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  649. return -ENOMEM;
  650. }
  651. } else
  652. iwlagn_rx_queue_reset(priv, rxq);
  653. iwlagn_rx_replenish(priv);
  654. iwlagn_rx_init(priv, rxq);
  655. spin_lock_irqsave(&priv->lock, flags);
  656. rxq->need_update = 1;
  657. iwl_rx_queue_update_write_ptr(priv, rxq);
  658. spin_unlock_irqrestore(&priv->lock, flags);
  659. /* Allocate or reset and init all Tx and Command queues */
  660. if (!priv->txq) {
  661. ret = iwlagn_txq_ctx_alloc(priv);
  662. if (ret)
  663. return ret;
  664. } else
  665. iwlagn_txq_ctx_reset(priv);
  666. if (priv->cfg->base_params->shadow_reg_enable) {
  667. /* enable shadow regs in HW */
  668. iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
  669. 0x800FFFFF);
  670. }
  671. set_bit(STATUS_INIT, &priv->status);
  672. return 0;
  673. }
  674. /**
  675. * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  676. */
  677. static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
  678. dma_addr_t dma_addr)
  679. {
  680. return cpu_to_le32((u32)(dma_addr >> 8));
  681. }
  682. /**
  683. * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
  684. *
  685. * If there are slots in the RX queue that need to be restocked,
  686. * and we have free pre-allocated buffers, fill the ranks as much
  687. * as we can, pulling from rx_free.
  688. *
  689. * This moves the 'write' index forward to catch up with 'processed', and
  690. * also updates the memory address in the firmware to reference the new
  691. * target buffer.
  692. */
  693. void iwlagn_rx_queue_restock(struct iwl_priv *priv)
  694. {
  695. struct iwl_rx_queue *rxq = &priv->rxq;
  696. struct list_head *element;
  697. struct iwl_rx_mem_buffer *rxb;
  698. unsigned long flags;
  699. spin_lock_irqsave(&rxq->lock, flags);
  700. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  701. /* The overwritten rxb must be a used one */
  702. rxb = rxq->queue[rxq->write];
  703. BUG_ON(rxb && rxb->page);
  704. /* Get next free Rx buffer, remove from free list */
  705. element = rxq->rx_free.next;
  706. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  707. list_del(element);
  708. /* Point to Rx buffer via next RBD in circular buffer */
  709. rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
  710. rxb->page_dma);
  711. rxq->queue[rxq->write] = rxb;
  712. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  713. rxq->free_count--;
  714. }
  715. spin_unlock_irqrestore(&rxq->lock, flags);
  716. /* If the pre-allocated buffer pool is dropping low, schedule to
  717. * refill it */
  718. if (rxq->free_count <= RX_LOW_WATERMARK)
  719. queue_work(priv->workqueue, &priv->rx_replenish);
  720. /* If we've added more space for the firmware to place data, tell it.
  721. * Increment device's write pointer in multiples of 8. */
  722. if (rxq->write_actual != (rxq->write & ~0x7)) {
  723. spin_lock_irqsave(&rxq->lock, flags);
  724. rxq->need_update = 1;
  725. spin_unlock_irqrestore(&rxq->lock, flags);
  726. iwl_rx_queue_update_write_ptr(priv, rxq);
  727. }
  728. }
  729. /**
  730. * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
  731. *
  732. * When moving to rx_free an SKB is allocated for the slot.
  733. *
  734. * Also restock the Rx queue via iwl_rx_queue_restock.
  735. * This is called as a scheduled work item (except for during initialization)
  736. */
  737. void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  738. {
  739. struct iwl_rx_queue *rxq = &priv->rxq;
  740. struct list_head *element;
  741. struct iwl_rx_mem_buffer *rxb;
  742. struct page *page;
  743. unsigned long flags;
  744. gfp_t gfp_mask = priority;
  745. while (1) {
  746. spin_lock_irqsave(&rxq->lock, flags);
  747. if (list_empty(&rxq->rx_used)) {
  748. spin_unlock_irqrestore(&rxq->lock, flags);
  749. return;
  750. }
  751. spin_unlock_irqrestore(&rxq->lock, flags);
  752. if (rxq->free_count > RX_LOW_WATERMARK)
  753. gfp_mask |= __GFP_NOWARN;
  754. if (priv->hw_params.rx_page_order > 0)
  755. gfp_mask |= __GFP_COMP;
  756. /* Alloc a new receive buffer */
  757. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  758. if (!page) {
  759. if (net_ratelimit())
  760. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  761. "order: %d\n",
  762. priv->hw_params.rx_page_order);
  763. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  764. net_ratelimit())
  765. IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
  766. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  767. rxq->free_count);
  768. /* We don't reschedule replenish work here -- we will
  769. * call the restock method and if it still needs
  770. * more buffers it will schedule replenish */
  771. return;
  772. }
  773. spin_lock_irqsave(&rxq->lock, flags);
  774. if (list_empty(&rxq->rx_used)) {
  775. spin_unlock_irqrestore(&rxq->lock, flags);
  776. __free_pages(page, priv->hw_params.rx_page_order);
  777. return;
  778. }
  779. element = rxq->rx_used.next;
  780. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  781. list_del(element);
  782. spin_unlock_irqrestore(&rxq->lock, flags);
  783. BUG_ON(rxb->page);
  784. rxb->page = page;
  785. /* Get physical address of the RB */
  786. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  787. PAGE_SIZE << priv->hw_params.rx_page_order,
  788. PCI_DMA_FROMDEVICE);
  789. /* dma address must be no more than 36 bits */
  790. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  791. /* and also 256 byte aligned! */
  792. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  793. spin_lock_irqsave(&rxq->lock, flags);
  794. list_add_tail(&rxb->list, &rxq->rx_free);
  795. rxq->free_count++;
  796. priv->alloc_rxb_page++;
  797. spin_unlock_irqrestore(&rxq->lock, flags);
  798. }
  799. }
  800. void iwlagn_rx_replenish(struct iwl_priv *priv)
  801. {
  802. unsigned long flags;
  803. iwlagn_rx_allocate(priv, GFP_KERNEL);
  804. spin_lock_irqsave(&priv->lock, flags);
  805. iwlagn_rx_queue_restock(priv);
  806. spin_unlock_irqrestore(&priv->lock, flags);
  807. }
  808. void iwlagn_rx_replenish_now(struct iwl_priv *priv)
  809. {
  810. iwlagn_rx_allocate(priv, GFP_ATOMIC);
  811. iwlagn_rx_queue_restock(priv);
  812. }
  813. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  814. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  815. * This free routine walks the list of POOL entries and if SKB is set to
  816. * non NULL it is unmapped and freed
  817. */
  818. void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  819. {
  820. int i;
  821. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  822. if (rxq->pool[i].page != NULL) {
  823. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  824. PAGE_SIZE << priv->hw_params.rx_page_order,
  825. PCI_DMA_FROMDEVICE);
  826. __iwl_free_pages(priv, rxq->pool[i].page);
  827. rxq->pool[i].page = NULL;
  828. }
  829. }
  830. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  831. rxq->bd_dma);
  832. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  833. rxq->rb_stts, rxq->rb_stts_dma);
  834. rxq->bd = NULL;
  835. rxq->rb_stts = NULL;
  836. }
  837. int iwlagn_rxq_stop(struct iwl_priv *priv)
  838. {
  839. /* stop Rx DMA */
  840. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  841. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  842. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  843. return 0;
  844. }
  845. int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  846. {
  847. int idx = 0;
  848. int band_offset = 0;
  849. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  850. if (rate_n_flags & RATE_MCS_HT_MSK) {
  851. idx = (rate_n_flags & 0xff);
  852. return idx;
  853. /* Legacy rate format, search for match in table */
  854. } else {
  855. if (band == IEEE80211_BAND_5GHZ)
  856. band_offset = IWL_FIRST_OFDM_RATE;
  857. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  858. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  859. return idx - band_offset;
  860. }
  861. return -1;
  862. }
  863. /* Calc max signal level (dBm) among 3 possible receivers */
  864. static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
  865. struct iwl_rx_phy_res *rx_resp)
  866. {
  867. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  868. }
  869. static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  870. {
  871. u32 decrypt_out = 0;
  872. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  873. RX_RES_STATUS_STATION_FOUND)
  874. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  875. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  876. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  877. /* packet was not encrypted */
  878. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  879. RX_RES_STATUS_SEC_TYPE_NONE)
  880. return decrypt_out;
  881. /* packet was encrypted with unknown alg */
  882. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  883. RX_RES_STATUS_SEC_TYPE_ERR)
  884. return decrypt_out;
  885. /* decryption was not done in HW */
  886. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  887. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  888. return decrypt_out;
  889. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  890. case RX_RES_STATUS_SEC_TYPE_CCMP:
  891. /* alg is CCM: check MIC only */
  892. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  893. /* Bad MIC */
  894. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  895. else
  896. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  897. break;
  898. case RX_RES_STATUS_SEC_TYPE_TKIP:
  899. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  900. /* Bad TTAK */
  901. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  902. break;
  903. }
  904. /* fall through if TTAK OK */
  905. default:
  906. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  907. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  908. else
  909. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  910. break;
  911. }
  912. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  913. decrypt_in, decrypt_out);
  914. return decrypt_out;
  915. }
  916. static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
  917. struct ieee80211_hdr *hdr,
  918. u16 len,
  919. u32 ampdu_status,
  920. struct iwl_rx_mem_buffer *rxb,
  921. struct ieee80211_rx_status *stats)
  922. {
  923. struct sk_buff *skb;
  924. __le16 fc = hdr->frame_control;
  925. /* We only process data packets if the interface is open */
  926. if (unlikely(!priv->is_open)) {
  927. IWL_DEBUG_DROP_LIMIT(priv,
  928. "Dropping packet while interface is not open.\n");
  929. return;
  930. }
  931. /* In case of HW accelerated crypto and bad decryption, drop */
  932. if (!priv->cfg->mod_params->sw_crypto &&
  933. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  934. return;
  935. skb = dev_alloc_skb(128);
  936. if (!skb) {
  937. IWL_ERR(priv, "dev_alloc_skb failed\n");
  938. return;
  939. }
  940. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  941. iwl_update_stats(priv, false, fc, len);
  942. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  943. ieee80211_rx(priv->hw, skb);
  944. priv->alloc_rxb_page--;
  945. rxb->page = NULL;
  946. }
  947. /* Called for REPLY_RX (legacy ABG frames), or
  948. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  949. void iwlagn_rx_reply_rx(struct iwl_priv *priv,
  950. struct iwl_rx_mem_buffer *rxb)
  951. {
  952. struct ieee80211_hdr *header;
  953. struct ieee80211_rx_status rx_status;
  954. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  955. struct iwl_rx_phy_res *phy_res;
  956. __le32 rx_pkt_status;
  957. struct iwl_rx_mpdu_res_start *amsdu;
  958. u32 len;
  959. u32 ampdu_status;
  960. u32 rate_n_flags;
  961. /**
  962. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  963. * REPLY_RX: physical layer info is in this buffer
  964. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  965. * command and cached in priv->last_phy_res
  966. *
  967. * Here we set up local variables depending on which command is
  968. * received.
  969. */
  970. if (pkt->hdr.cmd == REPLY_RX) {
  971. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  972. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  973. + phy_res->cfg_phy_cnt);
  974. len = le16_to_cpu(phy_res->byte_count);
  975. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  976. phy_res->cfg_phy_cnt + len);
  977. ampdu_status = le32_to_cpu(rx_pkt_status);
  978. } else {
  979. if (!priv->_agn.last_phy_res_valid) {
  980. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  981. return;
  982. }
  983. phy_res = &priv->_agn.last_phy_res;
  984. amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
  985. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  986. len = le16_to_cpu(amsdu->byte_count);
  987. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  988. ampdu_status = iwlagn_translate_rx_status(priv,
  989. le32_to_cpu(rx_pkt_status));
  990. }
  991. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  992. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  993. phy_res->cfg_phy_cnt);
  994. return;
  995. }
  996. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  997. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  998. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  999. le32_to_cpu(rx_pkt_status));
  1000. return;
  1001. }
  1002. /* This will be used in several places later */
  1003. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  1004. /* rx_status carries information about the packet to mac80211 */
  1005. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  1006. rx_status.freq =
  1007. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
  1008. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  1009. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  1010. rx_status.rate_idx =
  1011. iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  1012. rx_status.flag = 0;
  1013. /* TSF isn't reliable. In order to allow smooth user experience,
  1014. * this W/A doesn't propagate it to the mac80211 */
  1015. /*rx_status.flag |= RX_FLAG_TSFT;*/
  1016. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  1017. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  1018. rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
  1019. iwl_dbg_log_rx_data_frame(priv, len, header);
  1020. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
  1021. rx_status.signal, (unsigned long long)rx_status.mactime);
  1022. /*
  1023. * "antenna number"
  1024. *
  1025. * It seems that the antenna field in the phy flags value
  1026. * is actually a bit field. This is undefined by radiotap,
  1027. * it wants an actual antenna number but I always get "7"
  1028. * for most legacy frames I receive indicating that the
  1029. * same frame was received on all three RX chains.
  1030. *
  1031. * I think this field should be removed in favor of a
  1032. * new 802.11n radiotap field "RX chains" that is defined
  1033. * as a bitmask.
  1034. */
  1035. rx_status.antenna =
  1036. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  1037. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  1038. /* set the preamble flag if appropriate */
  1039. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1040. rx_status.flag |= RX_FLAG_SHORTPRE;
  1041. /* Set up the HT phy flags */
  1042. if (rate_n_flags & RATE_MCS_HT_MSK)
  1043. rx_status.flag |= RX_FLAG_HT;
  1044. if (rate_n_flags & RATE_MCS_HT40_MSK)
  1045. rx_status.flag |= RX_FLAG_40MHZ;
  1046. if (rate_n_flags & RATE_MCS_SGI_MSK)
  1047. rx_status.flag |= RX_FLAG_SHORT_GI;
  1048. iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  1049. rxb, &rx_status);
  1050. }
  1051. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  1052. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  1053. void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
  1054. struct iwl_rx_mem_buffer *rxb)
  1055. {
  1056. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1057. priv->_agn.last_phy_res_valid = true;
  1058. memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
  1059. sizeof(struct iwl_rx_phy_res));
  1060. }
  1061. static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
  1062. struct ieee80211_vif *vif,
  1063. enum ieee80211_band band,
  1064. struct iwl_scan_channel *scan_ch)
  1065. {
  1066. const struct ieee80211_supported_band *sband;
  1067. u16 passive_dwell = 0;
  1068. u16 active_dwell = 0;
  1069. int added = 0;
  1070. u16 channel = 0;
  1071. sband = iwl_get_hw_mode(priv, band);
  1072. if (!sband) {
  1073. IWL_ERR(priv, "invalid band\n");
  1074. return added;
  1075. }
  1076. active_dwell = iwl_get_active_dwell_time(priv, band, 0);
  1077. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1078. if (passive_dwell <= active_dwell)
  1079. passive_dwell = active_dwell + 1;
  1080. channel = iwl_get_single_channel_number(priv, band);
  1081. if (channel) {
  1082. scan_ch->channel = cpu_to_le16(channel);
  1083. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  1084. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1085. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1086. /* Set txpower levels to defaults */
  1087. scan_ch->dsp_atten = 110;
  1088. if (band == IEEE80211_BAND_5GHZ)
  1089. scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1090. else
  1091. scan_ch->tx_gain = ((1 << 5) | (5 << 3));
  1092. added++;
  1093. } else
  1094. IWL_ERR(priv, "no valid channel found\n");
  1095. return added;
  1096. }
  1097. static int iwl_get_channels_for_scan(struct iwl_priv *priv,
  1098. struct ieee80211_vif *vif,
  1099. enum ieee80211_band band,
  1100. u8 is_active, u8 n_probes,
  1101. struct iwl_scan_channel *scan_ch)
  1102. {
  1103. struct ieee80211_channel *chan;
  1104. const struct ieee80211_supported_band *sband;
  1105. const struct iwl_channel_info *ch_info;
  1106. u16 passive_dwell = 0;
  1107. u16 active_dwell = 0;
  1108. int added, i;
  1109. u16 channel;
  1110. sband = iwl_get_hw_mode(priv, band);
  1111. if (!sband)
  1112. return 0;
  1113. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  1114. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1115. if (passive_dwell <= active_dwell)
  1116. passive_dwell = active_dwell + 1;
  1117. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1118. chan = priv->scan_request->channels[i];
  1119. if (chan->band != band)
  1120. continue;
  1121. channel = chan->hw_value;
  1122. scan_ch->channel = cpu_to_le16(channel);
  1123. ch_info = iwl_get_channel_info(priv, band, channel);
  1124. if (!is_channel_valid(ch_info)) {
  1125. IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
  1126. channel);
  1127. continue;
  1128. }
  1129. if (!is_active || is_channel_passive(ch_info) ||
  1130. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
  1131. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  1132. else
  1133. scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
  1134. if (n_probes)
  1135. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  1136. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1137. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1138. /* Set txpower levels to defaults */
  1139. scan_ch->dsp_atten = 110;
  1140. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1141. * power level:
  1142. * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1143. */
  1144. if (band == IEEE80211_BAND_5GHZ)
  1145. scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1146. else
  1147. scan_ch->tx_gain = ((1 << 5) | (5 << 3));
  1148. IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
  1149. channel, le32_to_cpu(scan_ch->type),
  1150. (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
  1151. "ACTIVE" : "PASSIVE",
  1152. (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
  1153. active_dwell : passive_dwell);
  1154. scan_ch++;
  1155. added++;
  1156. }
  1157. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1158. return added;
  1159. }
  1160. int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  1161. {
  1162. struct iwl_host_cmd cmd = {
  1163. .id = REPLY_SCAN_CMD,
  1164. .len = sizeof(struct iwl_scan_cmd),
  1165. .flags = CMD_SIZE_HUGE,
  1166. };
  1167. struct iwl_scan_cmd *scan;
  1168. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  1169. u32 rate_flags = 0;
  1170. u16 cmd_len;
  1171. u16 rx_chain = 0;
  1172. enum ieee80211_band band;
  1173. u8 n_probes = 0;
  1174. u8 rx_ant = priv->hw_params.valid_rx_ant;
  1175. u8 rate;
  1176. bool is_active = false;
  1177. int chan_mod;
  1178. u8 active_chains;
  1179. u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
  1180. int ret;
  1181. lockdep_assert_held(&priv->mutex);
  1182. if (vif)
  1183. ctx = iwl_rxon_ctx_from_vif(vif);
  1184. if (!priv->scan_cmd) {
  1185. priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
  1186. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  1187. if (!priv->scan_cmd) {
  1188. IWL_DEBUG_SCAN(priv,
  1189. "fail to allocate memory for scan\n");
  1190. return -ENOMEM;
  1191. }
  1192. }
  1193. scan = priv->scan_cmd;
  1194. memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
  1195. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  1196. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  1197. if (iwl_is_any_associated(priv)) {
  1198. u16 interval = 0;
  1199. u32 extra;
  1200. u32 suspend_time = 100;
  1201. u32 scan_suspend_time = 100;
  1202. unsigned long flags;
  1203. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  1204. spin_lock_irqsave(&priv->lock, flags);
  1205. if (priv->is_internal_short_scan)
  1206. interval = 0;
  1207. else
  1208. interval = vif->bss_conf.beacon_int;
  1209. spin_unlock_irqrestore(&priv->lock, flags);
  1210. scan->suspend_time = 0;
  1211. scan->max_out_time = cpu_to_le32(200 * 1024);
  1212. if (!interval)
  1213. interval = suspend_time;
  1214. extra = (suspend_time / interval) << 22;
  1215. scan_suspend_time = (extra |
  1216. ((suspend_time % interval) * 1024));
  1217. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  1218. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  1219. scan_suspend_time, interval);
  1220. }
  1221. if (priv->is_internal_short_scan) {
  1222. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  1223. } else if (priv->scan_request->n_ssids) {
  1224. int i, p = 0;
  1225. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  1226. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  1227. /* always does wildcard anyway */
  1228. if (!priv->scan_request->ssids[i].ssid_len)
  1229. continue;
  1230. scan->direct_scan[p].id = WLAN_EID_SSID;
  1231. scan->direct_scan[p].len =
  1232. priv->scan_request->ssids[i].ssid_len;
  1233. memcpy(scan->direct_scan[p].ssid,
  1234. priv->scan_request->ssids[i].ssid,
  1235. priv->scan_request->ssids[i].ssid_len);
  1236. n_probes++;
  1237. p++;
  1238. }
  1239. is_active = true;
  1240. } else
  1241. IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
  1242. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  1243. scan->tx_cmd.sta_id = ctx->bcast_sta_id;
  1244. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1245. switch (priv->scan_band) {
  1246. case IEEE80211_BAND_2GHZ:
  1247. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  1248. chan_mod = le32_to_cpu(
  1249. priv->contexts[IWL_RXON_CTX_BSS].active.flags &
  1250. RXON_FLG_CHANNEL_MODE_MSK)
  1251. >> RXON_FLG_CHANNEL_MODE_POS;
  1252. if (chan_mod == CHANNEL_MODE_PURE_40) {
  1253. rate = IWL_RATE_6M_PLCP;
  1254. } else {
  1255. rate = IWL_RATE_1M_PLCP;
  1256. rate_flags = RATE_MCS_CCK_MSK;
  1257. }
  1258. /*
  1259. * Internal scans are passive, so we can indiscriminately set
  1260. * the BT ignore flag on 2.4 GHz since it applies to TX only.
  1261. */
  1262. if (priv->cfg->bt_params &&
  1263. priv->cfg->bt_params->advanced_bt_coexist)
  1264. scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
  1265. break;
  1266. case IEEE80211_BAND_5GHZ:
  1267. rate = IWL_RATE_6M_PLCP;
  1268. break;
  1269. default:
  1270. IWL_WARN(priv, "Invalid scan band\n");
  1271. return -EIO;
  1272. }
  1273. /*
  1274. * If active scanning is requested but a certain channel is
  1275. * marked passive, we can do active scanning if we detect
  1276. * transmissions.
  1277. *
  1278. * There is an issue with some firmware versions that triggers
  1279. * a sysassert on a "good CRC threshold" of zero (== disabled),
  1280. * on a radar channel even though this means that we should NOT
  1281. * send probes.
  1282. *
  1283. * The "good CRC threshold" is the number of frames that we
  1284. * need to receive during our dwell time on a channel before
  1285. * sending out probes -- setting this to a huge value will
  1286. * mean we never reach it, but at the same time work around
  1287. * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
  1288. * here instead of IWL_GOOD_CRC_TH_DISABLED.
  1289. */
  1290. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  1291. IWL_GOOD_CRC_TH_NEVER;
  1292. band = priv->scan_band;
  1293. if (priv->cfg->scan_rx_antennas[band])
  1294. rx_ant = priv->cfg->scan_rx_antennas[band];
  1295. if (priv->cfg->scan_tx_antennas[band])
  1296. scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
  1297. if (priv->cfg->bt_params &&
  1298. priv->cfg->bt_params->advanced_bt_coexist &&
  1299. priv->bt_full_concurrent) {
  1300. /* operated as 1x1 in full concurrency mode */
  1301. scan_tx_antennas = first_antenna(
  1302. priv->cfg->scan_tx_antennas[band]);
  1303. }
  1304. priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
  1305. scan_tx_antennas);
  1306. rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
  1307. scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
  1308. /* In power save mode use one chain, otherwise use all chains */
  1309. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  1310. /* rx_ant has been set to all valid chains previously */
  1311. active_chains = rx_ant &
  1312. ((u8)(priv->chain_noise_data.active_chains));
  1313. if (!active_chains)
  1314. active_chains = rx_ant;
  1315. IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
  1316. priv->chain_noise_data.active_chains);
  1317. rx_ant = first_antenna(active_chains);
  1318. }
  1319. if (priv->cfg->bt_params &&
  1320. priv->cfg->bt_params->advanced_bt_coexist &&
  1321. priv->bt_full_concurrent) {
  1322. /* operated as 1x1 in full concurrency mode */
  1323. rx_ant = first_antenna(rx_ant);
  1324. }
  1325. /* MIMO is not used here, but value is required */
  1326. rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
  1327. rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  1328. rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
  1329. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  1330. scan->rx_chain = cpu_to_le16(rx_chain);
  1331. if (!priv->is_internal_short_scan) {
  1332. cmd_len = iwl_fill_probe_req(priv,
  1333. (struct ieee80211_mgmt *)scan->data,
  1334. vif->addr,
  1335. priv->scan_request->ie,
  1336. priv->scan_request->ie_len,
  1337. IWL_MAX_SCAN_SIZE - sizeof(*scan));
  1338. } else {
  1339. /* use bcast addr, will not be transmitted but must be valid */
  1340. cmd_len = iwl_fill_probe_req(priv,
  1341. (struct ieee80211_mgmt *)scan->data,
  1342. iwl_bcast_addr, NULL, 0,
  1343. IWL_MAX_SCAN_SIZE - sizeof(*scan));
  1344. }
  1345. scan->tx_cmd.len = cpu_to_le16(cmd_len);
  1346. scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
  1347. RXON_FILTER_BCON_AWARE_MSK);
  1348. if (priv->is_internal_short_scan) {
  1349. scan->channel_count =
  1350. iwl_get_single_channel_for_scan(priv, vif, band,
  1351. (void *)&scan->data[le16_to_cpu(
  1352. scan->tx_cmd.len)]);
  1353. } else {
  1354. scan->channel_count =
  1355. iwl_get_channels_for_scan(priv, vif, band,
  1356. is_active, n_probes,
  1357. (void *)&scan->data[le16_to_cpu(
  1358. scan->tx_cmd.len)]);
  1359. }
  1360. if (scan->channel_count == 0) {
  1361. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  1362. return -EIO;
  1363. }
  1364. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  1365. scan->channel_count * sizeof(struct iwl_scan_channel);
  1366. cmd.data = scan;
  1367. scan->len = cpu_to_le16(cmd.len);
  1368. /* set scan bit here for PAN params */
  1369. set_bit(STATUS_SCAN_HW, &priv->status);
  1370. if (priv->cfg->ops->hcmd->set_pan_params) {
  1371. ret = priv->cfg->ops->hcmd->set_pan_params(priv);
  1372. if (ret)
  1373. return ret;
  1374. }
  1375. ret = iwl_send_cmd_sync(priv, &cmd);
  1376. if (ret) {
  1377. clear_bit(STATUS_SCAN_HW, &priv->status);
  1378. if (priv->cfg->ops->hcmd->set_pan_params)
  1379. priv->cfg->ops->hcmd->set_pan_params(priv);
  1380. }
  1381. return ret;
  1382. }
  1383. int iwlagn_manage_ibss_station(struct iwl_priv *priv,
  1384. struct ieee80211_vif *vif, bool add)
  1385. {
  1386. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  1387. if (add)
  1388. return iwlagn_add_bssid_station(priv, vif_priv->ctx,
  1389. vif->bss_conf.bssid,
  1390. &vif_priv->ibss_bssid_sta_id);
  1391. return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
  1392. vif->bss_conf.bssid);
  1393. }
  1394. void iwl_free_tfds_in_queue(struct iwl_priv *priv,
  1395. int sta_id, int tid, int freed)
  1396. {
  1397. lockdep_assert_held(&priv->sta_lock);
  1398. if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
  1399. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  1400. else {
  1401. IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
  1402. priv->stations[sta_id].tid[tid].tfds_in_queue,
  1403. freed);
  1404. priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
  1405. }
  1406. }
  1407. #define IWL_FLUSH_WAIT_MS 2000
  1408. int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
  1409. {
  1410. struct iwl_tx_queue *txq;
  1411. struct iwl_queue *q;
  1412. int cnt;
  1413. unsigned long now = jiffies;
  1414. int ret = 0;
  1415. /* waiting for all the tx frames complete might take a while */
  1416. for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
  1417. if (cnt == priv->cmd_queue)
  1418. continue;
  1419. txq = &priv->txq[cnt];
  1420. q = &txq->q;
  1421. while (q->read_ptr != q->write_ptr && !time_after(jiffies,
  1422. now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
  1423. msleep(1);
  1424. if (q->read_ptr != q->write_ptr) {
  1425. IWL_ERR(priv, "fail to flush all tx fifo queues\n");
  1426. ret = -ETIMEDOUT;
  1427. break;
  1428. }
  1429. }
  1430. return ret;
  1431. }
  1432. #define IWL_TX_QUEUE_MSK 0xfffff
  1433. /**
  1434. * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
  1435. *
  1436. * pre-requirements:
  1437. * 1. acquire mutex before calling
  1438. * 2. make sure rf is on and not in exit state
  1439. */
  1440. int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
  1441. {
  1442. struct iwl_txfifo_flush_cmd flush_cmd;
  1443. struct iwl_host_cmd cmd = {
  1444. .id = REPLY_TXFIFO_FLUSH,
  1445. .len = sizeof(struct iwl_txfifo_flush_cmd),
  1446. .flags = CMD_SYNC,
  1447. .data = &flush_cmd,
  1448. };
  1449. might_sleep();
  1450. memset(&flush_cmd, 0, sizeof(flush_cmd));
  1451. flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
  1452. IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
  1453. if (priv->cfg->sku & IWL_SKU_N)
  1454. flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
  1455. IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
  1456. flush_cmd.fifo_control);
  1457. flush_cmd.flush_control = cpu_to_le16(flush_control);
  1458. return iwl_send_cmd(priv, &cmd);
  1459. }
  1460. void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
  1461. {
  1462. mutex_lock(&priv->mutex);
  1463. ieee80211_stop_queues(priv->hw);
  1464. if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
  1465. IWL_ERR(priv, "flush request fail\n");
  1466. goto done;
  1467. }
  1468. IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
  1469. iwlagn_wait_tx_queue_empty(priv);
  1470. done:
  1471. ieee80211_wake_queues(priv->hw);
  1472. mutex_unlock(&priv->mutex);
  1473. }
  1474. /*
  1475. * BT coex
  1476. */
  1477. /*
  1478. * Macros to access the lookup table.
  1479. *
  1480. * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
  1481. * wifi_prio, wifi_txrx and wifi_sh_ant_req.
  1482. *
  1483. * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
  1484. *
  1485. * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
  1486. * one after another in 32-bit registers, and "registers" 0 through 7 contain
  1487. * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
  1488. *
  1489. * These macros encode that format.
  1490. */
  1491. #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
  1492. wifi_txrx, wifi_sh_ant_req) \
  1493. (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
  1494. (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
  1495. #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
  1496. lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
  1497. #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1498. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1499. (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
  1500. bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
  1501. wifi_sh_ant_req))))
  1502. #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1503. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1504. LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
  1505. bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
  1506. wifi_sh_ant_req))
  1507. #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
  1508. wifi_req, wifi_prio, wifi_txrx, \
  1509. wifi_sh_ant_req) \
  1510. LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
  1511. bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
  1512. wifi_sh_ant_req))
  1513. #define LUT_WLAN_KILL_OP(lut, op, val) \
  1514. lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
  1515. #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1516. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1517. (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
  1518. wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
  1519. #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1520. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1521. LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
  1522. wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
  1523. #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1524. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1525. LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
  1526. wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
  1527. #define LUT_ANT_SWITCH_OP(lut, op, val) \
  1528. lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
  1529. #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1530. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1531. (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
  1532. wifi_req, wifi_prio, wifi_txrx, \
  1533. wifi_sh_ant_req))))
  1534. #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1535. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1536. LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
  1537. wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
  1538. #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
  1539. wifi_prio, wifi_txrx, wifi_sh_ant_req) \
  1540. LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
  1541. wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
  1542. static const __le32 iwlagn_def_3w_lookup[12] = {
  1543. cpu_to_le32(0xaaaaaaaa),
  1544. cpu_to_le32(0xaaaaaaaa),
  1545. cpu_to_le32(0xaeaaaaaa),
  1546. cpu_to_le32(0xaaaaaaaa),
  1547. cpu_to_le32(0xcc00ff28),
  1548. cpu_to_le32(0x0000aaaa),
  1549. cpu_to_le32(0xcc00aaaa),
  1550. cpu_to_le32(0x0000aaaa),
  1551. cpu_to_le32(0xc0004000),
  1552. cpu_to_le32(0x00004000),
  1553. cpu_to_le32(0xf0005000),
  1554. cpu_to_le32(0xf0005000),
  1555. };
  1556. static const __le32 iwlagn_concurrent_lookup[12] = {
  1557. cpu_to_le32(0xaaaaaaaa),
  1558. cpu_to_le32(0xaaaaaaaa),
  1559. cpu_to_le32(0xaaaaaaaa),
  1560. cpu_to_le32(0xaaaaaaaa),
  1561. cpu_to_le32(0xaaaaaaaa),
  1562. cpu_to_le32(0xaaaaaaaa),
  1563. cpu_to_le32(0xaaaaaaaa),
  1564. cpu_to_le32(0xaaaaaaaa),
  1565. cpu_to_le32(0x00000000),
  1566. cpu_to_le32(0x00000000),
  1567. cpu_to_le32(0x00000000),
  1568. cpu_to_le32(0x00000000),
  1569. };
  1570. void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
  1571. {
  1572. struct iwlagn_bt_cmd bt_cmd = {
  1573. .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
  1574. .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
  1575. .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
  1576. .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
  1577. };
  1578. BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
  1579. sizeof(bt_cmd.bt3_lookup_table));
  1580. if (priv->cfg->bt_params)
  1581. bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
  1582. else
  1583. bt_cmd.prio_boost = 0;
  1584. bt_cmd.kill_ack_mask = priv->kill_ack_mask;
  1585. bt_cmd.kill_cts_mask = priv->kill_cts_mask;
  1586. bt_cmd.valid = priv->bt_valid;
  1587. bt_cmd.tx_prio_boost = 0;
  1588. bt_cmd.rx_prio_boost = 0;
  1589. /*
  1590. * Configure BT coex mode to "no coexistence" when the
  1591. * user disabled BT coexistence, we have no interface
  1592. * (might be in monitor mode), or the interface is in
  1593. * IBSS mode (no proper uCode support for coex then).
  1594. */
  1595. if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
  1596. bt_cmd.flags = 0;
  1597. } else {
  1598. bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
  1599. IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
  1600. if (priv->cfg->bt_params &&
  1601. priv->cfg->bt_params->bt_sco_disable)
  1602. bt_cmd.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
  1603. if (priv->bt_ch_announce)
  1604. bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
  1605. IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
  1606. }
  1607. if (priv->bt_full_concurrent)
  1608. memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
  1609. sizeof(iwlagn_concurrent_lookup));
  1610. else
  1611. memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
  1612. sizeof(iwlagn_def_3w_lookup));
  1613. IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
  1614. bt_cmd.flags ? "active" : "disabled",
  1615. priv->bt_full_concurrent ?
  1616. "full concurrency" : "3-wire");
  1617. if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
  1618. IWL_ERR(priv, "failed to send BT Coex Config\n");
  1619. /*
  1620. * When we are doing a restart, need to also reconfigure BT
  1621. * SCO to the device. If not doing a restart, bt_sco_active
  1622. * will always be false, so there's no need to have an extra
  1623. * variable to check for it.
  1624. */
  1625. if (priv->bt_sco_active) {
  1626. struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
  1627. if (priv->bt_sco_active)
  1628. sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
  1629. if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
  1630. sizeof(sco_cmd), &sco_cmd))
  1631. IWL_ERR(priv, "failed to send BT SCO command\n");
  1632. }
  1633. }
  1634. static void iwlagn_bt_traffic_change_work(struct work_struct *work)
  1635. {
  1636. struct iwl_priv *priv =
  1637. container_of(work, struct iwl_priv, bt_traffic_change_work);
  1638. struct iwl_rxon_context *ctx;
  1639. int smps_request = -1;
  1640. /*
  1641. * Note: bt_traffic_load can be overridden by scan complete and
  1642. * coex profile notifications. Ignore that since only bad consequence
  1643. * can be not matching debug print with actual state.
  1644. */
  1645. IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
  1646. priv->bt_traffic_load);
  1647. switch (priv->bt_traffic_load) {
  1648. case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
  1649. if (priv->bt_status)
  1650. smps_request = IEEE80211_SMPS_DYNAMIC;
  1651. else
  1652. smps_request = IEEE80211_SMPS_AUTOMATIC;
  1653. break;
  1654. case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
  1655. smps_request = IEEE80211_SMPS_DYNAMIC;
  1656. break;
  1657. case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
  1658. case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
  1659. smps_request = IEEE80211_SMPS_STATIC;
  1660. break;
  1661. default:
  1662. IWL_ERR(priv, "Invalid BT traffic load: %d\n",
  1663. priv->bt_traffic_load);
  1664. break;
  1665. }
  1666. mutex_lock(&priv->mutex);
  1667. /*
  1668. * We can not send command to firmware while scanning. When the scan
  1669. * complete we will schedule this work again. We do check with mutex
  1670. * locked to prevent new scan request to arrive. We do not check
  1671. * STATUS_SCANNING to avoid race when queue_work two times from
  1672. * different notifications, but quit and not perform any work at all.
  1673. */
  1674. if (test_bit(STATUS_SCAN_HW, &priv->status))
  1675. goto out;
  1676. if (priv->cfg->ops->lib->update_chain_flags)
  1677. priv->cfg->ops->lib->update_chain_flags(priv);
  1678. if (smps_request != -1) {
  1679. for_each_context(priv, ctx) {
  1680. if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
  1681. ieee80211_request_smps(ctx->vif, smps_request);
  1682. }
  1683. }
  1684. out:
  1685. mutex_unlock(&priv->mutex);
  1686. }
  1687. static void iwlagn_print_uartmsg(struct iwl_priv *priv,
  1688. struct iwl_bt_uart_msg *uart_msg)
  1689. {
  1690. IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
  1691. "Update Req = 0x%X",
  1692. (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
  1693. BT_UART_MSG_FRAME1MSGTYPE_POS,
  1694. (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
  1695. BT_UART_MSG_FRAME1SSN_POS,
  1696. (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
  1697. BT_UART_MSG_FRAME1UPDATEREQ_POS);
  1698. IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
  1699. "Chl_SeqN = 0x%X, In band = 0x%X",
  1700. (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
  1701. BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
  1702. (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
  1703. BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
  1704. (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
  1705. BT_UART_MSG_FRAME2CHLSEQN_POS,
  1706. (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
  1707. BT_UART_MSG_FRAME2INBAND_POS);
  1708. IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
  1709. "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
  1710. (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
  1711. BT_UART_MSG_FRAME3SCOESCO_POS,
  1712. (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
  1713. BT_UART_MSG_FRAME3SNIFF_POS,
  1714. (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
  1715. BT_UART_MSG_FRAME3A2DP_POS,
  1716. (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
  1717. BT_UART_MSG_FRAME3ACL_POS,
  1718. (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
  1719. BT_UART_MSG_FRAME3MASTER_POS,
  1720. (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
  1721. BT_UART_MSG_FRAME3OBEX_POS);
  1722. IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
  1723. (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
  1724. BT_UART_MSG_FRAME4IDLEDURATION_POS);
  1725. IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
  1726. "eSCO Retransmissions = 0x%X",
  1727. (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
  1728. BT_UART_MSG_FRAME5TXACTIVITY_POS,
  1729. (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
  1730. BT_UART_MSG_FRAME5RXACTIVITY_POS,
  1731. (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
  1732. BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
  1733. IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
  1734. (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
  1735. BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
  1736. (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
  1737. BT_UART_MSG_FRAME6DISCOVERABLE_POS);
  1738. IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
  1739. "0x%X, Connectable = 0x%X",
  1740. (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
  1741. BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
  1742. (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
  1743. BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
  1744. (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
  1745. BT_UART_MSG_FRAME7CONNECTABLE_POS);
  1746. }
  1747. static void iwlagn_set_kill_msk(struct iwl_priv *priv,
  1748. struct iwl_bt_uart_msg *uart_msg)
  1749. {
  1750. u8 kill_msk;
  1751. static const __le32 bt_kill_ack_msg[2] = {
  1752. IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
  1753. IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
  1754. static const __le32 bt_kill_cts_msg[2] = {
  1755. IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
  1756. IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
  1757. kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
  1758. ? 1 : 0;
  1759. if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
  1760. priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
  1761. priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
  1762. priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
  1763. priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
  1764. priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
  1765. /* schedule to send runtime bt_config */
  1766. queue_work(priv->workqueue, &priv->bt_runtime_config);
  1767. }
  1768. }
  1769. void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
  1770. struct iwl_rx_mem_buffer *rxb)
  1771. {
  1772. unsigned long flags;
  1773. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1774. struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
  1775. struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
  1776. struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
  1777. IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
  1778. IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
  1779. IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
  1780. IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
  1781. coex->bt_ci_compliance);
  1782. iwlagn_print_uartmsg(priv, uart_msg);
  1783. priv->last_bt_traffic_load = priv->bt_traffic_load;
  1784. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  1785. if (priv->bt_status != coex->bt_status ||
  1786. priv->last_bt_traffic_load != coex->bt_traffic_load) {
  1787. if (coex->bt_status) {
  1788. /* BT on */
  1789. if (!priv->bt_ch_announce)
  1790. priv->bt_traffic_load =
  1791. IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
  1792. else
  1793. priv->bt_traffic_load =
  1794. coex->bt_traffic_load;
  1795. } else {
  1796. /* BT off */
  1797. priv->bt_traffic_load =
  1798. IWL_BT_COEX_TRAFFIC_LOAD_NONE;
  1799. }
  1800. priv->bt_status = coex->bt_status;
  1801. queue_work(priv->workqueue,
  1802. &priv->bt_traffic_change_work);
  1803. }
  1804. if (priv->bt_sco_active !=
  1805. (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
  1806. priv->bt_sco_active = uart_msg->frame3 &
  1807. BT_UART_MSG_FRAME3SCOESCO_MSK;
  1808. if (priv->bt_sco_active)
  1809. sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
  1810. iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
  1811. sizeof(sco_cmd), &sco_cmd, NULL);
  1812. }
  1813. }
  1814. iwlagn_set_kill_msk(priv, uart_msg);
  1815. /* FIXME: based on notification, adjust the prio_boost */
  1816. spin_lock_irqsave(&priv->lock, flags);
  1817. priv->bt_ci_compliance = coex->bt_ci_compliance;
  1818. spin_unlock_irqrestore(&priv->lock, flags);
  1819. }
  1820. void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
  1821. {
  1822. iwlagn_rx_handler_setup(priv);
  1823. priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
  1824. iwlagn_bt_coex_profile_notif;
  1825. }
  1826. void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
  1827. {
  1828. iwlagn_setup_deferred_work(priv);
  1829. INIT_WORK(&priv->bt_traffic_change_work,
  1830. iwlagn_bt_traffic_change_work);
  1831. }
  1832. void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
  1833. {
  1834. cancel_work_sync(&priv->bt_traffic_change_work);
  1835. }
  1836. static bool is_single_rx_stream(struct iwl_priv *priv)
  1837. {
  1838. return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
  1839. priv->current_ht_config.single_chain_sufficient;
  1840. }
  1841. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  1842. #define IWL_NUM_RX_CHAINS_SINGLE 2
  1843. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  1844. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  1845. /*
  1846. * Determine how many receiver/antenna chains to use.
  1847. *
  1848. * More provides better reception via diversity. Fewer saves power
  1849. * at the expense of throughput, but only when not in powersave to
  1850. * start with.
  1851. *
  1852. * MIMO (dual stream) requires at least 2, but works better with 3.
  1853. * This does not determine *which* chains to use, just how many.
  1854. */
  1855. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  1856. {
  1857. if (priv->cfg->bt_params &&
  1858. priv->cfg->bt_params->advanced_bt_coexist &&
  1859. (priv->bt_full_concurrent ||
  1860. priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
  1861. /*
  1862. * only use chain 'A' in bt high traffic load or
  1863. * full concurrency mode
  1864. */
  1865. return IWL_NUM_RX_CHAINS_SINGLE;
  1866. }
  1867. /* # of Rx chains to use when expecting MIMO. */
  1868. if (is_single_rx_stream(priv))
  1869. return IWL_NUM_RX_CHAINS_SINGLE;
  1870. else
  1871. return IWL_NUM_RX_CHAINS_MULTIPLE;
  1872. }
  1873. /*
  1874. * When we are in power saving mode, unless device support spatial
  1875. * multiplexing power save, use the active count for rx chain count.
  1876. */
  1877. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  1878. {
  1879. /* # Rx chains when idling, depending on SMPS mode */
  1880. switch (priv->current_ht_config.smps) {
  1881. case IEEE80211_SMPS_STATIC:
  1882. case IEEE80211_SMPS_DYNAMIC:
  1883. return IWL_NUM_IDLE_CHAINS_SINGLE;
  1884. case IEEE80211_SMPS_OFF:
  1885. return active_cnt;
  1886. default:
  1887. WARN(1, "invalid SMPS mode %d",
  1888. priv->current_ht_config.smps);
  1889. return active_cnt;
  1890. }
  1891. }
  1892. /* up to 4 chains */
  1893. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  1894. {
  1895. u8 res;
  1896. res = (chain_bitmap & BIT(0)) >> 0;
  1897. res += (chain_bitmap & BIT(1)) >> 1;
  1898. res += (chain_bitmap & BIT(2)) >> 2;
  1899. res += (chain_bitmap & BIT(3)) >> 3;
  1900. return res;
  1901. }
  1902. /**
  1903. * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  1904. *
  1905. * Selects how many and which Rx receivers/antennas/chains to use.
  1906. * This should not be used for scan command ... it puts data in wrong place.
  1907. */
  1908. void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
  1909. {
  1910. bool is_single = is_single_rx_stream(priv);
  1911. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  1912. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  1913. u32 active_chains;
  1914. u16 rx_chain;
  1915. /* Tell uCode which antennas are actually connected.
  1916. * Before first association, we assume all antennas are connected.
  1917. * Just after first association, iwl_chain_noise_calibration()
  1918. * checks which antennas actually *are* connected. */
  1919. if (priv->chain_noise_data.active_chains)
  1920. active_chains = priv->chain_noise_data.active_chains;
  1921. else
  1922. active_chains = priv->hw_params.valid_rx_ant;
  1923. if (priv->cfg->bt_params &&
  1924. priv->cfg->bt_params->advanced_bt_coexist &&
  1925. (priv->bt_full_concurrent ||
  1926. priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
  1927. /*
  1928. * only use chain 'A' in bt high traffic load or
  1929. * full concurrency mode
  1930. */
  1931. active_chains = first_antenna(active_chains);
  1932. }
  1933. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  1934. /* How many receivers should we use? */
  1935. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  1936. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  1937. /* correct rx chain count according hw settings
  1938. * and chain noise calibration
  1939. */
  1940. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  1941. if (valid_rx_cnt < active_rx_cnt)
  1942. active_rx_cnt = valid_rx_cnt;
  1943. if (valid_rx_cnt < idle_rx_cnt)
  1944. idle_rx_cnt = valid_rx_cnt;
  1945. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  1946. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  1947. ctx->staging.rx_chain = cpu_to_le16(rx_chain);
  1948. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  1949. ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  1950. else
  1951. ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  1952. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  1953. ctx->staging.rx_chain,
  1954. active_rx_cnt, idle_rx_cnt);
  1955. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  1956. active_rx_cnt < idle_rx_cnt);
  1957. }
  1958. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
  1959. {
  1960. int i;
  1961. u8 ind = ant;
  1962. if (priv->band == IEEE80211_BAND_2GHZ &&
  1963. priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
  1964. return 0;
  1965. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  1966. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  1967. if (valid & BIT(ind))
  1968. return ind;
  1969. }
  1970. return ant;
  1971. }
  1972. static const char *get_csr_string(int cmd)
  1973. {
  1974. switch (cmd) {
  1975. IWL_CMD(CSR_HW_IF_CONFIG_REG);
  1976. IWL_CMD(CSR_INT_COALESCING);
  1977. IWL_CMD(CSR_INT);
  1978. IWL_CMD(CSR_INT_MASK);
  1979. IWL_CMD(CSR_FH_INT_STATUS);
  1980. IWL_CMD(CSR_GPIO_IN);
  1981. IWL_CMD(CSR_RESET);
  1982. IWL_CMD(CSR_GP_CNTRL);
  1983. IWL_CMD(CSR_HW_REV);
  1984. IWL_CMD(CSR_EEPROM_REG);
  1985. IWL_CMD(CSR_EEPROM_GP);
  1986. IWL_CMD(CSR_OTP_GP_REG);
  1987. IWL_CMD(CSR_GIO_REG);
  1988. IWL_CMD(CSR_GP_UCODE_REG);
  1989. IWL_CMD(CSR_GP_DRIVER_REG);
  1990. IWL_CMD(CSR_UCODE_DRV_GP1);
  1991. IWL_CMD(CSR_UCODE_DRV_GP2);
  1992. IWL_CMD(CSR_LED_REG);
  1993. IWL_CMD(CSR_DRAM_INT_TBL_REG);
  1994. IWL_CMD(CSR_GIO_CHICKEN_BITS);
  1995. IWL_CMD(CSR_ANA_PLL_CFG);
  1996. IWL_CMD(CSR_HW_REV_WA_REG);
  1997. IWL_CMD(CSR_DBG_HPET_MEM_REG);
  1998. default:
  1999. return "UNKNOWN";
  2000. }
  2001. }
  2002. void iwl_dump_csr(struct iwl_priv *priv)
  2003. {
  2004. int i;
  2005. static const u32 csr_tbl[] = {
  2006. CSR_HW_IF_CONFIG_REG,
  2007. CSR_INT_COALESCING,
  2008. CSR_INT,
  2009. CSR_INT_MASK,
  2010. CSR_FH_INT_STATUS,
  2011. CSR_GPIO_IN,
  2012. CSR_RESET,
  2013. CSR_GP_CNTRL,
  2014. CSR_HW_REV,
  2015. CSR_EEPROM_REG,
  2016. CSR_EEPROM_GP,
  2017. CSR_OTP_GP_REG,
  2018. CSR_GIO_REG,
  2019. CSR_GP_UCODE_REG,
  2020. CSR_GP_DRIVER_REG,
  2021. CSR_UCODE_DRV_GP1,
  2022. CSR_UCODE_DRV_GP2,
  2023. CSR_LED_REG,
  2024. CSR_DRAM_INT_TBL_REG,
  2025. CSR_GIO_CHICKEN_BITS,
  2026. CSR_ANA_PLL_CFG,
  2027. CSR_HW_REV_WA_REG,
  2028. CSR_DBG_HPET_MEM_REG
  2029. };
  2030. IWL_ERR(priv, "CSR values:\n");
  2031. IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
  2032. "CSR_INT_PERIODIC_REG)\n");
  2033. for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
  2034. IWL_ERR(priv, " %25s: 0X%08x\n",
  2035. get_csr_string(csr_tbl[i]),
  2036. iwl_read32(priv, csr_tbl[i]));
  2037. }
  2038. }
  2039. static const char *get_fh_string(int cmd)
  2040. {
  2041. switch (cmd) {
  2042. IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
  2043. IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
  2044. IWL_CMD(FH_RSCSR_CHNL0_WPTR);
  2045. IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
  2046. IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
  2047. IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
  2048. IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
  2049. IWL_CMD(FH_TSSR_TX_STATUS_REG);
  2050. IWL_CMD(FH_TSSR_TX_ERROR_REG);
  2051. default:
  2052. return "UNKNOWN";
  2053. }
  2054. }
  2055. int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
  2056. {
  2057. int i;
  2058. #ifdef CONFIG_IWLWIFI_DEBUG
  2059. int pos = 0;
  2060. size_t bufsz = 0;
  2061. #endif
  2062. static const u32 fh_tbl[] = {
  2063. FH_RSCSR_CHNL0_STTS_WPTR_REG,
  2064. FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  2065. FH_RSCSR_CHNL0_WPTR,
  2066. FH_MEM_RCSR_CHNL0_CONFIG_REG,
  2067. FH_MEM_RSSR_SHARED_CTRL_REG,
  2068. FH_MEM_RSSR_RX_STATUS_REG,
  2069. FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
  2070. FH_TSSR_TX_STATUS_REG,
  2071. FH_TSSR_TX_ERROR_REG
  2072. };
  2073. #ifdef CONFIG_IWLWIFI_DEBUG
  2074. if (display) {
  2075. bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
  2076. *buf = kmalloc(bufsz, GFP_KERNEL);
  2077. if (!*buf)
  2078. return -ENOMEM;
  2079. pos += scnprintf(*buf + pos, bufsz - pos,
  2080. "FH register values:\n");
  2081. for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
  2082. pos += scnprintf(*buf + pos, bufsz - pos,
  2083. " %34s: 0X%08x\n",
  2084. get_fh_string(fh_tbl[i]),
  2085. iwl_read_direct32(priv, fh_tbl[i]));
  2086. }
  2087. return pos;
  2088. }
  2089. #endif
  2090. IWL_ERR(priv, "FH register values:\n");
  2091. for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
  2092. IWL_ERR(priv, " %34s: 0X%08x\n",
  2093. get_fh_string(fh_tbl[i]),
  2094. iwl_read_direct32(priv, fh_tbl[i]));
  2095. }
  2096. return 0;
  2097. }