nouveau_drv.c 11 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include "drmP.h"
  26. #include "drm.h"
  27. #include "drm_crtc_helper.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_hw.h"
  30. #include "nouveau_fb.h"
  31. #include "nouveau_fbcon.h"
  32. #include "nv50_display.h"
  33. #include "drm_pciids.h"
  34. MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
  35. int nouveau_ctxfw = 0;
  36. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  37. MODULE_PARM_DESC(noagp, "Disable AGP");
  38. int nouveau_noagp;
  39. module_param_named(noagp, nouveau_noagp, int, 0400);
  40. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  41. static int nouveau_modeset = -1; /* kms */
  42. module_param_named(modeset, nouveau_modeset, int, 0400);
  43. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  44. char *nouveau_vbios;
  45. module_param_named(vbios, nouveau_vbios, charp, 0400);
  46. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  47. int nouveau_vram_pushbuf;
  48. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  49. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  50. int nouveau_vram_notify;
  51. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  52. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  53. int nouveau_duallink = 1;
  54. module_param_named(duallink, nouveau_duallink, int, 0400);
  55. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  56. int nouveau_uscript_lvds = -1;
  57. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  58. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  59. int nouveau_uscript_tmds = -1;
  60. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  61. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  62. int nouveau_ignorelid = 0;
  63. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  64. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  65. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  66. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  67. "\t\tDefault: PAL\n"
  68. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  69. char *nouveau_tv_norm;
  70. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  71. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  72. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  73. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  74. "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
  75. int nouveau_reg_debug;
  76. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  77. int nouveau_fbpercrtc;
  78. #if 0
  79. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  80. #endif
  81. static struct pci_device_id pciidlist[] = {
  82. {
  83. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  84. .class = PCI_BASE_CLASS_DISPLAY << 16,
  85. .class_mask = 0xff << 16,
  86. },
  87. {
  88. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  89. .class = PCI_BASE_CLASS_DISPLAY << 16,
  90. .class_mask = 0xff << 16,
  91. },
  92. {}
  93. };
  94. MODULE_DEVICE_TABLE(pci, pciidlist);
  95. static struct drm_driver driver;
  96. static int __devinit
  97. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  98. {
  99. return drm_get_dev(pdev, ent, &driver);
  100. }
  101. static void
  102. nouveau_pci_remove(struct pci_dev *pdev)
  103. {
  104. struct drm_device *dev = pci_get_drvdata(pdev);
  105. drm_put_dev(dev);
  106. }
  107. static int
  108. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  109. {
  110. struct drm_device *dev = pci_get_drvdata(pdev);
  111. struct drm_nouveau_private *dev_priv = dev->dev_private;
  112. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  113. struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  114. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  115. struct nouveau_channel *chan;
  116. struct drm_crtc *crtc;
  117. uint32_t fbdev_flags;
  118. int ret, i;
  119. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  120. return -ENODEV;
  121. if (pm_state.event == PM_EVENT_PRETHAW)
  122. return 0;
  123. fbdev_flags = dev_priv->fbdev_info->flags;
  124. dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
  125. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  126. struct nouveau_framebuffer *nouveau_fb;
  127. nouveau_fb = nouveau_framebuffer(crtc->fb);
  128. if (!nouveau_fb || !nouveau_fb->nvbo)
  129. continue;
  130. nouveau_bo_unpin(nouveau_fb->nvbo);
  131. }
  132. NV_INFO(dev, "Evicting buffers...\n");
  133. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  134. NV_INFO(dev, "Idling channels...\n");
  135. for (i = 0; i < pfifo->channels; i++) {
  136. struct nouveau_fence *fence = NULL;
  137. chan = dev_priv->fifos[i];
  138. if (!chan || (dev_priv->card_type >= NV_50 &&
  139. chan == dev_priv->fifos[0]))
  140. continue;
  141. ret = nouveau_fence_new(chan, &fence, true);
  142. if (ret == 0) {
  143. ret = nouveau_fence_wait(fence, NULL, false, false);
  144. nouveau_fence_unref((void *)&fence);
  145. }
  146. if (ret) {
  147. NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
  148. chan->id);
  149. }
  150. }
  151. pgraph->fifo_access(dev, false);
  152. nouveau_wait_for_idle(dev);
  153. pfifo->reassign(dev, false);
  154. pfifo->disable(dev);
  155. pfifo->unload_context(dev);
  156. pgraph->unload_context(dev);
  157. NV_INFO(dev, "Suspending GPU objects...\n");
  158. ret = nouveau_gpuobj_suspend(dev);
  159. if (ret) {
  160. NV_ERROR(dev, "... failed: %d\n", ret);
  161. goto out_abort;
  162. }
  163. ret = pinstmem->suspend(dev);
  164. if (ret) {
  165. NV_ERROR(dev, "... failed: %d\n", ret);
  166. nouveau_gpuobj_suspend_cleanup(dev);
  167. goto out_abort;
  168. }
  169. NV_INFO(dev, "And we're gone!\n");
  170. pci_save_state(pdev);
  171. if (pm_state.event == PM_EVENT_SUSPEND) {
  172. pci_disable_device(pdev);
  173. pci_set_power_state(pdev, PCI_D3hot);
  174. }
  175. acquire_console_sem();
  176. fb_set_suspend(dev_priv->fbdev_info, 1);
  177. release_console_sem();
  178. dev_priv->fbdev_info->flags = fbdev_flags;
  179. return 0;
  180. out_abort:
  181. NV_INFO(dev, "Re-enabling acceleration..\n");
  182. pfifo->enable(dev);
  183. pfifo->reassign(dev, true);
  184. pgraph->fifo_access(dev, true);
  185. return ret;
  186. }
  187. static int
  188. nouveau_pci_resume(struct pci_dev *pdev)
  189. {
  190. struct drm_device *dev = pci_get_drvdata(pdev);
  191. struct drm_nouveau_private *dev_priv = dev->dev_private;
  192. struct nouveau_engine *engine = &dev_priv->engine;
  193. struct drm_crtc *crtc;
  194. uint32_t fbdev_flags;
  195. int ret, i;
  196. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  197. return -ENODEV;
  198. fbdev_flags = dev_priv->fbdev_info->flags;
  199. dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
  200. NV_INFO(dev, "We're back, enabling device...\n");
  201. pci_set_power_state(pdev, PCI_D0);
  202. pci_restore_state(pdev);
  203. if (pci_enable_device(pdev))
  204. return -1;
  205. pci_set_master(dev->pdev);
  206. NV_INFO(dev, "POSTing device...\n");
  207. ret = nouveau_run_vbios_init(dev);
  208. if (ret)
  209. return ret;
  210. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  211. ret = nouveau_mem_init_agp(dev);
  212. if (ret) {
  213. NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
  214. return ret;
  215. }
  216. }
  217. NV_INFO(dev, "Reinitialising engines...\n");
  218. engine->instmem.resume(dev);
  219. engine->mc.init(dev);
  220. engine->timer.init(dev);
  221. engine->fb.init(dev);
  222. engine->graph.init(dev);
  223. engine->fifo.init(dev);
  224. NV_INFO(dev, "Restoring GPU objects...\n");
  225. nouveau_gpuobj_resume(dev);
  226. nouveau_irq_postinstall(dev);
  227. /* Re-write SKIPS, they'll have been lost over the suspend */
  228. if (nouveau_vram_pushbuf) {
  229. struct nouveau_channel *chan;
  230. int j;
  231. for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  232. chan = dev_priv->fifos[i];
  233. if (!chan || !chan->pushbuf_bo)
  234. continue;
  235. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  236. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  237. }
  238. }
  239. NV_INFO(dev, "Restoring mode...\n");
  240. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  241. struct nouveau_framebuffer *nouveau_fb;
  242. nouveau_fb = nouveau_framebuffer(crtc->fb);
  243. if (!nouveau_fb || !nouveau_fb->nvbo)
  244. continue;
  245. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  246. }
  247. if (dev_priv->card_type < NV_50) {
  248. nv04_display_restore(dev);
  249. NVLockVgaCrtcs(dev, false);
  250. } else
  251. nv50_display_init(dev);
  252. /* Force CLUT to get re-loaded during modeset */
  253. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  254. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  255. nv_crtc->lut.depth = 0;
  256. }
  257. acquire_console_sem();
  258. fb_set_suspend(dev_priv->fbdev_info, 0);
  259. release_console_sem();
  260. nouveau_fbcon_zfill(dev);
  261. drm_helper_resume_force_mode(dev);
  262. dev_priv->fbdev_info->flags = fbdev_flags;
  263. return 0;
  264. }
  265. static struct drm_driver driver = {
  266. .driver_features =
  267. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  268. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  269. .load = nouveau_load,
  270. .firstopen = nouveau_firstopen,
  271. .lastclose = nouveau_lastclose,
  272. .unload = nouveau_unload,
  273. .preclose = nouveau_preclose,
  274. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  275. .debugfs_init = nouveau_debugfs_init,
  276. .debugfs_cleanup = nouveau_debugfs_takedown,
  277. #endif
  278. .irq_preinstall = nouveau_irq_preinstall,
  279. .irq_postinstall = nouveau_irq_postinstall,
  280. .irq_uninstall = nouveau_irq_uninstall,
  281. .irq_handler = nouveau_irq_handler,
  282. .reclaim_buffers = drm_core_reclaim_buffers,
  283. .get_map_ofs = drm_core_get_map_ofs,
  284. .get_reg_ofs = drm_core_get_reg_ofs,
  285. .ioctls = nouveau_ioctls,
  286. .fops = {
  287. .owner = THIS_MODULE,
  288. .open = drm_open,
  289. .release = drm_release,
  290. .unlocked_ioctl = drm_ioctl,
  291. .mmap = nouveau_ttm_mmap,
  292. .poll = drm_poll,
  293. .fasync = drm_fasync,
  294. #if defined(CONFIG_COMPAT)
  295. .compat_ioctl = nouveau_compat_ioctl,
  296. #endif
  297. },
  298. .pci_driver = {
  299. .name = DRIVER_NAME,
  300. .id_table = pciidlist,
  301. .probe = nouveau_pci_probe,
  302. .remove = nouveau_pci_remove,
  303. .suspend = nouveau_pci_suspend,
  304. .resume = nouveau_pci_resume
  305. },
  306. .gem_init_object = nouveau_gem_object_new,
  307. .gem_free_object = nouveau_gem_object_del,
  308. .name = DRIVER_NAME,
  309. .desc = DRIVER_DESC,
  310. #ifdef GIT_REVISION
  311. .date = GIT_REVISION,
  312. #else
  313. .date = DRIVER_DATE,
  314. #endif
  315. .major = DRIVER_MAJOR,
  316. .minor = DRIVER_MINOR,
  317. .patchlevel = DRIVER_PATCHLEVEL,
  318. };
  319. static int __init nouveau_init(void)
  320. {
  321. driver.num_ioctls = nouveau_max_ioctl;
  322. if (nouveau_modeset == -1) {
  323. #ifdef CONFIG_VGA_CONSOLE
  324. if (vgacon_text_force())
  325. nouveau_modeset = 0;
  326. else
  327. #endif
  328. nouveau_modeset = 1;
  329. }
  330. if (nouveau_modeset == 1)
  331. driver.driver_features |= DRIVER_MODESET;
  332. return drm_init(&driver);
  333. }
  334. static void __exit nouveau_exit(void)
  335. {
  336. drm_exit(&driver);
  337. }
  338. module_init(nouveau_init);
  339. module_exit(nouveau_exit);
  340. MODULE_AUTHOR(DRIVER_AUTHOR);
  341. MODULE_DESCRIPTION(DRIVER_DESC);
  342. MODULE_LICENSE("GPL and additional rights");