phy.c 90 KB

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  1. /*
  2. * PHY functions
  3. *
  4. * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
  5. * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
  6. * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
  7. * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
  8. *
  9. * Permission to use, copy, modify, and distribute this software for any
  10. * purpose with or without fee is hereby granted, provided that the above
  11. * copyright notice and this permission notice appear in all copies.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20. *
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/slab.h>
  24. #include <asm/unaligned.h>
  25. #include "ath5k.h"
  26. #include "reg.h"
  27. #include "base.h"
  28. #include "rfbuffer.h"
  29. #include "rfgain.h"
  30. /******************\
  31. * Helper functions *
  32. \******************/
  33. /*
  34. * Get the PHY Chip revision
  35. */
  36. u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
  37. {
  38. unsigned int i;
  39. u32 srev;
  40. u16 ret;
  41. /*
  42. * Set the radio chip access register
  43. */
  44. switch (chan) {
  45. case CHANNEL_2GHZ:
  46. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
  47. break;
  48. case CHANNEL_5GHZ:
  49. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  50. break;
  51. default:
  52. return 0;
  53. }
  54. mdelay(2);
  55. /* ...wait until PHY is ready and read the selected radio revision */
  56. ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
  57. for (i = 0; i < 8; i++)
  58. ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
  59. if (ah->ah_version == AR5K_AR5210) {
  60. srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
  61. ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
  62. } else {
  63. srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
  64. ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
  65. ((srev & 0x0f) << 4), 8);
  66. }
  67. /* Reset to the 5GHz mode */
  68. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  69. return ret;
  70. }
  71. /*
  72. * Check if a channel is supported
  73. */
  74. bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
  75. {
  76. /* Check if the channel is in our supported range */
  77. if (flags & CHANNEL_2GHZ) {
  78. if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
  79. (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
  80. return true;
  81. } else if (flags & CHANNEL_5GHZ)
  82. if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
  83. (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
  84. return true;
  85. return false;
  86. }
  87. bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
  88. struct ieee80211_channel *channel)
  89. {
  90. u8 refclk_freq;
  91. if ((ah->ah_radio == AR5K_RF5112) ||
  92. (ah->ah_radio == AR5K_RF5413) ||
  93. (ah->ah_radio == AR5K_RF2413) ||
  94. (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
  95. refclk_freq = 40;
  96. else
  97. refclk_freq = 32;
  98. if ((channel->center_freq % refclk_freq != 0) &&
  99. ((channel->center_freq % refclk_freq < 10) ||
  100. (channel->center_freq % refclk_freq > 22)))
  101. return true;
  102. else
  103. return false;
  104. }
  105. /*
  106. * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  107. */
  108. static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  109. const struct ath5k_rf_reg *rf_regs,
  110. u32 val, u8 reg_id, bool set)
  111. {
  112. const struct ath5k_rf_reg *rfreg = NULL;
  113. u8 offset, bank, num_bits, col, position;
  114. u16 entry;
  115. u32 mask, data, last_bit, bits_shifted, first_bit;
  116. u32 *rfb;
  117. s32 bits_left;
  118. int i;
  119. data = 0;
  120. rfb = ah->ah_rf_banks;
  121. for (i = 0; i < ah->ah_rf_regs_count; i++) {
  122. if (rf_regs[i].index == reg_id) {
  123. rfreg = &rf_regs[i];
  124. break;
  125. }
  126. }
  127. if (rfb == NULL || rfreg == NULL) {
  128. ATH5K_PRINTF("Rf register not found!\n");
  129. /* should not happen */
  130. return 0;
  131. }
  132. bank = rfreg->bank;
  133. num_bits = rfreg->field.len;
  134. first_bit = rfreg->field.pos;
  135. col = rfreg->field.col;
  136. /* first_bit is an offset from bank's
  137. * start. Since we have all banks on
  138. * the same array, we use this offset
  139. * to mark each bank's start */
  140. offset = ah->ah_offset[bank];
  141. /* Boundary check */
  142. if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
  143. ATH5K_PRINTF("invalid values at offset %u\n", offset);
  144. return 0;
  145. }
  146. entry = ((first_bit - 1) / 8) + offset;
  147. position = (first_bit - 1) % 8;
  148. if (set)
  149. data = ath5k_hw_bitswap(val, num_bits);
  150. for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
  151. position = 0, entry++) {
  152. last_bit = (position + bits_left > 8) ? 8 :
  153. position + bits_left;
  154. mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
  155. (col * 8);
  156. if (set) {
  157. rfb[entry] &= ~mask;
  158. rfb[entry] |= ((data << position) << (col * 8)) & mask;
  159. data >>= (8 - position);
  160. } else {
  161. data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
  162. << bits_shifted;
  163. bits_shifted += last_bit - position;
  164. }
  165. bits_left -= 8 - position;
  166. }
  167. data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
  168. return data;
  169. }
  170. /**
  171. * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
  172. *
  173. * @ah: the &struct ath5k_hw
  174. * @channel: the currently set channel upon reset
  175. *
  176. * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
  177. * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
  178. *
  179. * Since delta slope is floating point we split it on its exponent and
  180. * mantissa and provide these values on hw.
  181. *
  182. * For more infos i think this patent is related
  183. * http://www.freepatentsonline.com/7184495.html
  184. */
  185. static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
  186. struct ieee80211_channel *channel)
  187. {
  188. /* Get exponent and mantissa and set it */
  189. u32 coef_scaled, coef_exp, coef_man,
  190. ds_coef_exp, ds_coef_man, clock;
  191. BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
  192. !(channel->hw_value & CHANNEL_OFDM));
  193. /* Get coefficient
  194. * ALGO: coef = (5 * clock / carrier_freq) / 2
  195. * we scale coef by shifting clock value by 24 for
  196. * better precision since we use integers */
  197. switch (ah->ah_bwmode) {
  198. case AR5K_BWMODE_40MHZ:
  199. clock = 40 * 2;
  200. break;
  201. case AR5K_BWMODE_10MHZ:
  202. clock = 40 / 2;
  203. break;
  204. case AR5K_BWMODE_5MHZ:
  205. clock = 40 / 4;
  206. break;
  207. default:
  208. clock = 40;
  209. break;
  210. }
  211. coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
  212. /* Get exponent
  213. * ALGO: coef_exp = 14 - highest set bit position */
  214. coef_exp = ilog2(coef_scaled);
  215. /* Doesn't make sense if it's zero*/
  216. if (!coef_scaled || !coef_exp)
  217. return -EINVAL;
  218. /* Note: we've shifted coef_scaled by 24 */
  219. coef_exp = 14 - (coef_exp - 24);
  220. /* Get mantissa (significant digits)
  221. * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
  222. coef_man = coef_scaled +
  223. (1 << (24 - coef_exp - 1));
  224. /* Calculate delta slope coefficient exponent
  225. * and mantissa (remove scaling) and set them on hw */
  226. ds_coef_man = coef_man >> (24 - coef_exp);
  227. ds_coef_exp = coef_exp - 16;
  228. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
  229. AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
  230. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
  231. AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
  232. return 0;
  233. }
  234. int ath5k_hw_phy_disable(struct ath5k_hw *ah)
  235. {
  236. /*Just a try M.F.*/
  237. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  238. return 0;
  239. }
  240. /*
  241. * Wait for synth to settle
  242. */
  243. static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
  244. struct ieee80211_channel *channel)
  245. {
  246. /*
  247. * On 5211+ read activation -> rx delay
  248. * and use it (100ns steps).
  249. */
  250. if (ah->ah_version != AR5K_AR5210) {
  251. u32 delay;
  252. delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
  253. AR5K_PHY_RX_DELAY_M;
  254. delay = (channel->hw_value & CHANNEL_CCK) ?
  255. ((delay << 2) / 22) : (delay / 10);
  256. if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
  257. delay = delay << 1;
  258. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
  259. delay = delay << 2;
  260. /* XXX: /2 on turbo ? Let's be safe
  261. * for now */
  262. udelay(100 + delay);
  263. } else {
  264. mdelay(1);
  265. }
  266. }
  267. /**********************\
  268. * RF Gain optimization *
  269. \**********************/
  270. /*
  271. * This code is used to optimize RF gain on different environments
  272. * (temperature mostly) based on feedback from a power detector.
  273. *
  274. * It's only used on RF5111 and RF5112, later RF chips seem to have
  275. * auto adjustment on hw -notice they have a much smaller BANK 7 and
  276. * no gain optimization ladder-.
  277. *
  278. * For more infos check out this patent doc
  279. * http://www.freepatentsonline.com/7400691.html
  280. *
  281. * This paper describes power drops as seen on the receiver due to
  282. * probe packets
  283. * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
  284. * %20of%20Power%20Control.pdf
  285. *
  286. * And this is the MadWiFi bug entry related to the above
  287. * http://madwifi-project.org/ticket/1659
  288. * with various measurements and diagrams
  289. *
  290. * TODO: Deal with power drops due to probes by setting an appropriate
  291. * tx power on the probe packets ! Make this part of the calibration process.
  292. */
  293. /* Initialize ah_gain during attach */
  294. int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
  295. {
  296. /* Initialize the gain optimization values */
  297. switch (ah->ah_radio) {
  298. case AR5K_RF5111:
  299. ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
  300. ah->ah_gain.g_low = 20;
  301. ah->ah_gain.g_high = 35;
  302. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  303. break;
  304. case AR5K_RF5112:
  305. ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
  306. ah->ah_gain.g_low = 20;
  307. ah->ah_gain.g_high = 85;
  308. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  309. break;
  310. default:
  311. return -EINVAL;
  312. }
  313. return 0;
  314. }
  315. /* Schedule a gain probe check on the next transmitted packet.
  316. * That means our next packet is going to be sent with lower
  317. * tx power and a Peak to Average Power Detector (PAPD) will try
  318. * to measure the gain.
  319. *
  320. * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
  321. * just after we enable the probe so that we don't mess with
  322. * standard traffic ? Maybe it's time to use sw interrupts and
  323. * a probe tasklet !!!
  324. */
  325. static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
  326. {
  327. /* Skip if gain calibration is inactive or
  328. * we already handle a probe request */
  329. if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
  330. return;
  331. /* Send the packet with 2dB below max power as
  332. * patent doc suggest */
  333. ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
  334. AR5K_PHY_PAPD_PROBE_TXPOWER) |
  335. AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
  336. ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
  337. }
  338. /* Calculate gain_F measurement correction
  339. * based on the current step for RF5112 rev. 2 */
  340. static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
  341. {
  342. u32 mix, step;
  343. u32 *rf;
  344. const struct ath5k_gain_opt *go;
  345. const struct ath5k_gain_opt_step *g_step;
  346. const struct ath5k_rf_reg *rf_regs;
  347. /* Only RF5112 Rev. 2 supports it */
  348. if ((ah->ah_radio != AR5K_RF5112) ||
  349. (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
  350. return 0;
  351. go = &rfgain_opt_5112;
  352. rf_regs = rf_regs_5112a;
  353. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
  354. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  355. if (ah->ah_rf_banks == NULL)
  356. return 0;
  357. rf = ah->ah_rf_banks;
  358. ah->ah_gain.g_f_corr = 0;
  359. /* No VGA (Variable Gain Amplifier) override, skip */
  360. if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
  361. return 0;
  362. /* Mix gain stepping */
  363. step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
  364. /* Mix gain override */
  365. mix = g_step->gos_param[0];
  366. switch (mix) {
  367. case 3:
  368. ah->ah_gain.g_f_corr = step * 2;
  369. break;
  370. case 2:
  371. ah->ah_gain.g_f_corr = (step - 5) * 2;
  372. break;
  373. case 1:
  374. ah->ah_gain.g_f_corr = step;
  375. break;
  376. default:
  377. ah->ah_gain.g_f_corr = 0;
  378. break;
  379. }
  380. return ah->ah_gain.g_f_corr;
  381. }
  382. /* Check if current gain_F measurement is in the range of our
  383. * power detector windows. If we get a measurement outside range
  384. * we know it's not accurate (detectors can't measure anything outside
  385. * their detection window) so we must ignore it */
  386. static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
  387. {
  388. const struct ath5k_rf_reg *rf_regs;
  389. u32 step, mix_ovr, level[4];
  390. u32 *rf;
  391. if (ah->ah_rf_banks == NULL)
  392. return false;
  393. rf = ah->ah_rf_banks;
  394. if (ah->ah_radio == AR5K_RF5111) {
  395. rf_regs = rf_regs_5111;
  396. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
  397. step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
  398. false);
  399. level[0] = 0;
  400. level[1] = (step == 63) ? 50 : step + 4;
  401. level[2] = (step != 63) ? 64 : level[0];
  402. level[3] = level[2] + 50;
  403. ah->ah_gain.g_high = level[3] -
  404. (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
  405. ah->ah_gain.g_low = level[0] +
  406. (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
  407. } else {
  408. rf_regs = rf_regs_5112;
  409. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
  410. mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
  411. false);
  412. level[0] = level[2] = 0;
  413. if (mix_ovr == 1) {
  414. level[1] = level[3] = 83;
  415. } else {
  416. level[1] = level[3] = 107;
  417. ah->ah_gain.g_high = 55;
  418. }
  419. }
  420. return (ah->ah_gain.g_current >= level[0] &&
  421. ah->ah_gain.g_current <= level[1]) ||
  422. (ah->ah_gain.g_current >= level[2] &&
  423. ah->ah_gain.g_current <= level[3]);
  424. }
  425. /* Perform gain_F adjustment by choosing the right set
  426. * of parameters from RF gain optimization ladder */
  427. static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
  428. {
  429. const struct ath5k_gain_opt *go;
  430. const struct ath5k_gain_opt_step *g_step;
  431. int ret = 0;
  432. switch (ah->ah_radio) {
  433. case AR5K_RF5111:
  434. go = &rfgain_opt_5111;
  435. break;
  436. case AR5K_RF5112:
  437. go = &rfgain_opt_5112;
  438. break;
  439. default:
  440. return 0;
  441. }
  442. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  443. if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
  444. /* Reached maximum */
  445. if (ah->ah_gain.g_step_idx == 0)
  446. return -1;
  447. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  448. ah->ah_gain.g_target >= ah->ah_gain.g_high &&
  449. ah->ah_gain.g_step_idx > 0;
  450. g_step = &go->go_step[ah->ah_gain.g_step_idx])
  451. ah->ah_gain.g_target -= 2 *
  452. (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
  453. g_step->gos_gain);
  454. ret = 1;
  455. goto done;
  456. }
  457. if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
  458. /* Reached minimum */
  459. if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
  460. return -2;
  461. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  462. ah->ah_gain.g_target <= ah->ah_gain.g_low &&
  463. ah->ah_gain.g_step_idx < go->go_steps_count - 1;
  464. g_step = &go->go_step[ah->ah_gain.g_step_idx])
  465. ah->ah_gain.g_target -= 2 *
  466. (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
  467. g_step->gos_gain);
  468. ret = 2;
  469. goto done;
  470. }
  471. done:
  472. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  473. "ret %d, gain step %u, current gain %u, target gain %u\n",
  474. ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
  475. ah->ah_gain.g_target);
  476. return ret;
  477. }
  478. /* Main callback for thermal RF gain calibration engine
  479. * Check for a new gain reading and schedule an adjustment
  480. * if needed.
  481. *
  482. * TODO: Use sw interrupt to schedule reset if gain_F needs
  483. * adjustment */
  484. enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
  485. {
  486. u32 data, type;
  487. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  488. if (ah->ah_rf_banks == NULL ||
  489. ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
  490. return AR5K_RFGAIN_INACTIVE;
  491. /* No check requested, either engine is inactive
  492. * or an adjustment is already requested */
  493. if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
  494. goto done;
  495. /* Read the PAPD (Peak to Average Power Detector)
  496. * register */
  497. data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
  498. /* No probe is scheduled, read gain_F measurement */
  499. if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
  500. ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
  501. type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
  502. /* If tx packet is CCK correct the gain_F measurement
  503. * by cck ofdm gain delta */
  504. if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
  505. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
  506. ah->ah_gain.g_current +=
  507. ee->ee_cck_ofdm_gain_delta;
  508. else
  509. ah->ah_gain.g_current +=
  510. AR5K_GAIN_CCK_PROBE_CORR;
  511. }
  512. /* Further correct gain_F measurement for
  513. * RF5112A radios */
  514. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  515. ath5k_hw_rf_gainf_corr(ah);
  516. ah->ah_gain.g_current =
  517. ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
  518. (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
  519. 0;
  520. }
  521. /* Check if measurement is ok and if we need
  522. * to adjust gain, schedule a gain adjustment,
  523. * else switch back to the active state */
  524. if (ath5k_hw_rf_check_gainf_readback(ah) &&
  525. AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
  526. ath5k_hw_rf_gainf_adjust(ah)) {
  527. ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
  528. } else {
  529. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  530. }
  531. }
  532. done:
  533. return ah->ah_gain.g_state;
  534. }
  535. /* Write initial RF gain table to set the RF sensitivity
  536. * this one works on all RF chips and has nothing to do
  537. * with gain_F calibration */
  538. static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
  539. {
  540. const struct ath5k_ini_rfgain *ath5k_rfg;
  541. unsigned int i, size, index;
  542. switch (ah->ah_radio) {
  543. case AR5K_RF5111:
  544. ath5k_rfg = rfgain_5111;
  545. size = ARRAY_SIZE(rfgain_5111);
  546. break;
  547. case AR5K_RF5112:
  548. ath5k_rfg = rfgain_5112;
  549. size = ARRAY_SIZE(rfgain_5112);
  550. break;
  551. case AR5K_RF2413:
  552. ath5k_rfg = rfgain_2413;
  553. size = ARRAY_SIZE(rfgain_2413);
  554. break;
  555. case AR5K_RF2316:
  556. ath5k_rfg = rfgain_2316;
  557. size = ARRAY_SIZE(rfgain_2316);
  558. break;
  559. case AR5K_RF5413:
  560. ath5k_rfg = rfgain_5413;
  561. size = ARRAY_SIZE(rfgain_5413);
  562. break;
  563. case AR5K_RF2317:
  564. case AR5K_RF2425:
  565. ath5k_rfg = rfgain_2425;
  566. size = ARRAY_SIZE(rfgain_2425);
  567. break;
  568. default:
  569. return -EINVAL;
  570. }
  571. index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
  572. for (i = 0; i < size; i++) {
  573. AR5K_REG_WAIT(i);
  574. ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
  575. (u32)ath5k_rfg[i].rfg_register);
  576. }
  577. return 0;
  578. }
  579. /********************\
  580. * RF Registers setup *
  581. \********************/
  582. /*
  583. * Setup RF registers by writing RF buffer on hw
  584. */
  585. static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
  586. struct ieee80211_channel *channel, unsigned int mode)
  587. {
  588. const struct ath5k_rf_reg *rf_regs;
  589. const struct ath5k_ini_rfbuffer *ini_rfb;
  590. const struct ath5k_gain_opt *go = NULL;
  591. const struct ath5k_gain_opt_step *g_step;
  592. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  593. u8 ee_mode = 0;
  594. u32 *rfb;
  595. int i, obdb = -1, bank = -1;
  596. switch (ah->ah_radio) {
  597. case AR5K_RF5111:
  598. rf_regs = rf_regs_5111;
  599. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
  600. ini_rfb = rfb_5111;
  601. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
  602. go = &rfgain_opt_5111;
  603. break;
  604. case AR5K_RF5112:
  605. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  606. rf_regs = rf_regs_5112a;
  607. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
  608. ini_rfb = rfb_5112a;
  609. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
  610. } else {
  611. rf_regs = rf_regs_5112;
  612. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
  613. ini_rfb = rfb_5112;
  614. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
  615. }
  616. go = &rfgain_opt_5112;
  617. break;
  618. case AR5K_RF2413:
  619. rf_regs = rf_regs_2413;
  620. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
  621. ini_rfb = rfb_2413;
  622. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
  623. break;
  624. case AR5K_RF2316:
  625. rf_regs = rf_regs_2316;
  626. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
  627. ini_rfb = rfb_2316;
  628. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
  629. break;
  630. case AR5K_RF5413:
  631. rf_regs = rf_regs_5413;
  632. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
  633. ini_rfb = rfb_5413;
  634. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
  635. break;
  636. case AR5K_RF2317:
  637. rf_regs = rf_regs_2425;
  638. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
  639. ini_rfb = rfb_2317;
  640. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
  641. break;
  642. case AR5K_RF2425:
  643. rf_regs = rf_regs_2425;
  644. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
  645. if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
  646. ini_rfb = rfb_2425;
  647. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
  648. } else {
  649. ini_rfb = rfb_2417;
  650. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
  651. }
  652. break;
  653. default:
  654. return -EINVAL;
  655. }
  656. /* If it's the first time we set RF buffer, allocate
  657. * ah->ah_rf_banks based on ah->ah_rf_banks_size
  658. * we set above */
  659. if (ah->ah_rf_banks == NULL) {
  660. ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
  661. GFP_KERNEL);
  662. if (ah->ah_rf_banks == NULL) {
  663. ATH5K_ERR(ah, "out of memory\n");
  664. return -ENOMEM;
  665. }
  666. }
  667. /* Copy values to modify them */
  668. rfb = ah->ah_rf_banks;
  669. for (i = 0; i < ah->ah_rf_banks_size; i++) {
  670. if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
  671. ATH5K_ERR(ah, "invalid bank\n");
  672. return -EINVAL;
  673. }
  674. /* Bank changed, write down the offset */
  675. if (bank != ini_rfb[i].rfb_bank) {
  676. bank = ini_rfb[i].rfb_bank;
  677. ah->ah_offset[bank] = i;
  678. }
  679. rfb[i] = ini_rfb[i].rfb_mode_data[mode];
  680. }
  681. /* Set Output and Driver bias current (OB/DB) */
  682. if (channel->hw_value & CHANNEL_2GHZ) {
  683. if (channel->hw_value & CHANNEL_CCK)
  684. ee_mode = AR5K_EEPROM_MODE_11B;
  685. else
  686. ee_mode = AR5K_EEPROM_MODE_11G;
  687. /* For RF511X/RF211X combination we
  688. * use b_OB and b_DB parameters stored
  689. * in eeprom on ee->ee_ob[ee_mode][0]
  690. *
  691. * For all other chips we use OB/DB for 2GHz
  692. * stored in the b/g modal section just like
  693. * 802.11a on ee->ee_ob[ee_mode][1] */
  694. if ((ah->ah_radio == AR5K_RF5111) ||
  695. (ah->ah_radio == AR5K_RF5112))
  696. obdb = 0;
  697. else
  698. obdb = 1;
  699. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
  700. AR5K_RF_OB_2GHZ, true);
  701. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
  702. AR5K_RF_DB_2GHZ, true);
  703. /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
  704. } else if ((channel->hw_value & CHANNEL_5GHZ) ||
  705. (ah->ah_radio == AR5K_RF5111)) {
  706. /* For 11a, Turbo and XR we need to choose
  707. * OB/DB based on frequency range */
  708. ee_mode = AR5K_EEPROM_MODE_11A;
  709. obdb = channel->center_freq >= 5725 ? 3 :
  710. (channel->center_freq >= 5500 ? 2 :
  711. (channel->center_freq >= 5260 ? 1 :
  712. (channel->center_freq > 4000 ? 0 : -1)));
  713. if (obdb < 0)
  714. return -EINVAL;
  715. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
  716. AR5K_RF_OB_5GHZ, true);
  717. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
  718. AR5K_RF_DB_5GHZ, true);
  719. }
  720. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  721. /* Set turbo mode (N/A on RF5413) */
  722. if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
  723. (ah->ah_radio != AR5K_RF5413))
  724. ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
  725. /* Bank Modifications (chip-specific) */
  726. if (ah->ah_radio == AR5K_RF5111) {
  727. /* Set gain_F settings according to current step */
  728. if (channel->hw_value & CHANNEL_OFDM) {
  729. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
  730. AR5K_PHY_FRAME_CTL_TX_CLIP,
  731. g_step->gos_param[0]);
  732. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
  733. AR5K_RF_PWD_90, true);
  734. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
  735. AR5K_RF_PWD_84, true);
  736. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
  737. AR5K_RF_RFGAIN_SEL, true);
  738. /* We programmed gain_F parameters, switch back
  739. * to active state */
  740. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  741. }
  742. /* Bank 6/7 setup */
  743. ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
  744. AR5K_RF_PWD_XPD, true);
  745. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
  746. AR5K_RF_XPD_GAIN, true);
  747. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
  748. AR5K_RF_GAIN_I, true);
  749. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
  750. AR5K_RF_PLO_SEL, true);
  751. /* Tweak power detectors for half/quarter rate support */
  752. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
  753. ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
  754. u8 wait_i;
  755. ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
  756. AR5K_RF_WAIT_S, true);
  757. wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
  758. 0x1f : 0x10;
  759. ath5k_hw_rfb_op(ah, rf_regs, wait_i,
  760. AR5K_RF_WAIT_I, true);
  761. ath5k_hw_rfb_op(ah, rf_regs, 3,
  762. AR5K_RF_MAX_TIME, true);
  763. }
  764. }
  765. if (ah->ah_radio == AR5K_RF5112) {
  766. /* Set gain_F settings according to current step */
  767. if (channel->hw_value & CHANNEL_OFDM) {
  768. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
  769. AR5K_RF_MIXGAIN_OVR, true);
  770. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
  771. AR5K_RF_PWD_138, true);
  772. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
  773. AR5K_RF_PWD_137, true);
  774. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
  775. AR5K_RF_PWD_136, true);
  776. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
  777. AR5K_RF_PWD_132, true);
  778. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
  779. AR5K_RF_PWD_131, true);
  780. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
  781. AR5K_RF_PWD_130, true);
  782. /* We programmed gain_F parameters, switch back
  783. * to active state */
  784. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  785. }
  786. /* Bank 6/7 setup */
  787. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
  788. AR5K_RF_XPD_SEL, true);
  789. if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
  790. /* Rev. 1 supports only one xpd */
  791. ath5k_hw_rfb_op(ah, rf_regs,
  792. ee->ee_x_gain[ee_mode],
  793. AR5K_RF_XPD_GAIN, true);
  794. } else {
  795. u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
  796. if (ee->ee_pd_gains[ee_mode] > 1) {
  797. ath5k_hw_rfb_op(ah, rf_regs,
  798. pdg_curve_to_idx[0],
  799. AR5K_RF_PD_GAIN_LO, true);
  800. ath5k_hw_rfb_op(ah, rf_regs,
  801. pdg_curve_to_idx[1],
  802. AR5K_RF_PD_GAIN_HI, true);
  803. } else {
  804. ath5k_hw_rfb_op(ah, rf_regs,
  805. pdg_curve_to_idx[0],
  806. AR5K_RF_PD_GAIN_LO, true);
  807. ath5k_hw_rfb_op(ah, rf_regs,
  808. pdg_curve_to_idx[0],
  809. AR5K_RF_PD_GAIN_HI, true);
  810. }
  811. /* Lower synth voltage on Rev 2 */
  812. if (ah->ah_radio == AR5K_RF5112 &&
  813. (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {
  814. ath5k_hw_rfb_op(ah, rf_regs, 2,
  815. AR5K_RF_HIGH_VC_CP, true);
  816. ath5k_hw_rfb_op(ah, rf_regs, 2,
  817. AR5K_RF_MID_VC_CP, true);
  818. ath5k_hw_rfb_op(ah, rf_regs, 2,
  819. AR5K_RF_LOW_VC_CP, true);
  820. ath5k_hw_rfb_op(ah, rf_regs, 2,
  821. AR5K_RF_PUSH_UP, true);
  822. }
  823. /* Decrease power consumption on 5213+ BaseBand */
  824. if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
  825. ath5k_hw_rfb_op(ah, rf_regs, 1,
  826. AR5K_RF_PAD2GND, true);
  827. ath5k_hw_rfb_op(ah, rf_regs, 1,
  828. AR5K_RF_XB2_LVL, true);
  829. ath5k_hw_rfb_op(ah, rf_regs, 1,
  830. AR5K_RF_XB5_LVL, true);
  831. ath5k_hw_rfb_op(ah, rf_regs, 1,
  832. AR5K_RF_PWD_167, true);
  833. ath5k_hw_rfb_op(ah, rf_regs, 1,
  834. AR5K_RF_PWD_166, true);
  835. }
  836. }
  837. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
  838. AR5K_RF_GAIN_I, true);
  839. /* Tweak power detector for half/quarter rates */
  840. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
  841. ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
  842. u8 pd_delay;
  843. pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
  844. 0xf : 0x8;
  845. ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
  846. AR5K_RF_PD_PERIOD_A, true);
  847. ath5k_hw_rfb_op(ah, rf_regs, 0xf,
  848. AR5K_RF_PD_DELAY_A, true);
  849. }
  850. }
  851. if (ah->ah_radio == AR5K_RF5413 &&
  852. channel->hw_value & CHANNEL_2GHZ) {
  853. ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
  854. true);
  855. /* Set optimum value for early revisions (on pci-e chips) */
  856. if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
  857. ah->ah_mac_srev < AR5K_SREV_AR5413)
  858. ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
  859. AR5K_RF_PWD_ICLOBUF_2G, true);
  860. }
  861. /* Write RF banks on hw */
  862. for (i = 0; i < ah->ah_rf_banks_size; i++) {
  863. AR5K_REG_WAIT(i);
  864. ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
  865. }
  866. return 0;
  867. }
  868. /**************************\
  869. PHY/RF channel functions
  870. \**************************/
  871. /*
  872. * Conversion needed for RF5110
  873. */
  874. static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
  875. {
  876. u32 athchan;
  877. /*
  878. * Convert IEEE channel/MHz to an internal channel value used
  879. * by the AR5210 chipset. This has not been verified with
  880. * newer chipsets like the AR5212A who have a completely
  881. * different RF/PHY part.
  882. */
  883. athchan = (ath5k_hw_bitswap(
  884. (ieee80211_frequency_to_channel(
  885. channel->center_freq) - 24) / 2, 5)
  886. << 1) | (1 << 6) | 0x1;
  887. return athchan;
  888. }
  889. /*
  890. * Set channel on RF5110
  891. */
  892. static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
  893. struct ieee80211_channel *channel)
  894. {
  895. u32 data;
  896. /*
  897. * Set the channel and wait
  898. */
  899. data = ath5k_hw_rf5110_chan2athchan(channel);
  900. ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
  901. ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
  902. mdelay(1);
  903. return 0;
  904. }
  905. /*
  906. * Conversion needed for 5111
  907. */
  908. static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
  909. struct ath5k_athchan_2ghz *athchan)
  910. {
  911. int channel;
  912. /* Cast this value to catch negative channel numbers (>= -19) */
  913. channel = (int)ieee;
  914. /*
  915. * Map 2GHz IEEE channel to 5GHz Atheros channel
  916. */
  917. if (channel <= 13) {
  918. athchan->a2_athchan = 115 + channel;
  919. athchan->a2_flags = 0x46;
  920. } else if (channel == 14) {
  921. athchan->a2_athchan = 124;
  922. athchan->a2_flags = 0x44;
  923. } else if (channel >= 15 && channel <= 26) {
  924. athchan->a2_athchan = ((channel - 14) * 4) + 132;
  925. athchan->a2_flags = 0x46;
  926. } else
  927. return -EINVAL;
  928. return 0;
  929. }
  930. /*
  931. * Set channel on 5111
  932. */
  933. static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
  934. struct ieee80211_channel *channel)
  935. {
  936. struct ath5k_athchan_2ghz ath5k_channel_2ghz;
  937. unsigned int ath5k_channel =
  938. ieee80211_frequency_to_channel(channel->center_freq);
  939. u32 data0, data1, clock;
  940. int ret;
  941. /*
  942. * Set the channel on the RF5111 radio
  943. */
  944. data0 = data1 = 0;
  945. if (channel->hw_value & CHANNEL_2GHZ) {
  946. /* Map 2GHz channel to 5GHz Atheros channel ID */
  947. ret = ath5k_hw_rf5111_chan2athchan(
  948. ieee80211_frequency_to_channel(channel->center_freq),
  949. &ath5k_channel_2ghz);
  950. if (ret)
  951. return ret;
  952. ath5k_channel = ath5k_channel_2ghz.a2_athchan;
  953. data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
  954. << 5) | (1 << 4);
  955. }
  956. if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
  957. clock = 1;
  958. data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
  959. (clock << 1) | (1 << 10) | 1;
  960. } else {
  961. clock = 0;
  962. data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
  963. << 2) | (clock << 1) | (1 << 10) | 1;
  964. }
  965. ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
  966. AR5K_RF_BUFFER);
  967. ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
  968. AR5K_RF_BUFFER_CONTROL_3);
  969. return 0;
  970. }
  971. /*
  972. * Set channel on 5112 and newer
  973. */
  974. static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
  975. struct ieee80211_channel *channel)
  976. {
  977. u32 data, data0, data1, data2;
  978. u16 c;
  979. data = data0 = data1 = data2 = 0;
  980. c = channel->center_freq;
  981. if (c < 4800) {
  982. if (!((c - 2224) % 5)) {
  983. data0 = ((2 * (c - 704)) - 3040) / 10;
  984. data1 = 1;
  985. } else if (!((c - 2192) % 5)) {
  986. data0 = ((2 * (c - 672)) - 3040) / 10;
  987. data1 = 0;
  988. } else
  989. return -EINVAL;
  990. data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
  991. } else if ((c % 5) != 2 || c > 5435) {
  992. if (!(c % 20) && c >= 5120) {
  993. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  994. data2 = ath5k_hw_bitswap(3, 2);
  995. } else if (!(c % 10)) {
  996. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  997. data2 = ath5k_hw_bitswap(2, 2);
  998. } else if (!(c % 5)) {
  999. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  1000. data2 = ath5k_hw_bitswap(1, 2);
  1001. } else
  1002. return -EINVAL;
  1003. } else {
  1004. data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
  1005. data2 = ath5k_hw_bitswap(0, 2);
  1006. }
  1007. data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
  1008. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  1009. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  1010. return 0;
  1011. }
  1012. /*
  1013. * Set the channel on the RF2425
  1014. */
  1015. static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
  1016. struct ieee80211_channel *channel)
  1017. {
  1018. u32 data, data0, data2;
  1019. u16 c;
  1020. data = data0 = data2 = 0;
  1021. c = channel->center_freq;
  1022. if (c < 4800) {
  1023. data0 = ath5k_hw_bitswap((c - 2272), 8);
  1024. data2 = 0;
  1025. /* ? 5GHz ? */
  1026. } else if ((c % 5) != 2 || c > 5435) {
  1027. if (!(c % 20) && c < 5120)
  1028. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  1029. else if (!(c % 10))
  1030. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  1031. else if (!(c % 5))
  1032. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  1033. else
  1034. return -EINVAL;
  1035. data2 = ath5k_hw_bitswap(1, 2);
  1036. } else {
  1037. data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
  1038. data2 = ath5k_hw_bitswap(0, 2);
  1039. }
  1040. data = (data0 << 4) | data2 << 2 | 0x1001;
  1041. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  1042. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  1043. return 0;
  1044. }
  1045. /*
  1046. * Set a channel on the radio chip
  1047. */
  1048. static int ath5k_hw_channel(struct ath5k_hw *ah,
  1049. struct ieee80211_channel *channel)
  1050. {
  1051. int ret;
  1052. /*
  1053. * Check bounds supported by the PHY (we don't care about regulatory
  1054. * restrictions at this point). Note: hw_value already has the band
  1055. * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
  1056. * of the band by that */
  1057. if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
  1058. ATH5K_ERR(ah,
  1059. "channel frequency (%u MHz) out of supported "
  1060. "band range\n",
  1061. channel->center_freq);
  1062. return -EINVAL;
  1063. }
  1064. /*
  1065. * Set the channel and wait
  1066. */
  1067. switch (ah->ah_radio) {
  1068. case AR5K_RF5110:
  1069. ret = ath5k_hw_rf5110_channel(ah, channel);
  1070. break;
  1071. case AR5K_RF5111:
  1072. ret = ath5k_hw_rf5111_channel(ah, channel);
  1073. break;
  1074. case AR5K_RF2317:
  1075. case AR5K_RF2425:
  1076. ret = ath5k_hw_rf2425_channel(ah, channel);
  1077. break;
  1078. default:
  1079. ret = ath5k_hw_rf5112_channel(ah, channel);
  1080. break;
  1081. }
  1082. if (ret)
  1083. return ret;
  1084. /* Set JAPAN setting for channel 14 */
  1085. if (channel->center_freq == 2484) {
  1086. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
  1087. AR5K_PHY_CCKTXCTL_JAPAN);
  1088. } else {
  1089. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
  1090. AR5K_PHY_CCKTXCTL_WORLD);
  1091. }
  1092. ah->ah_current_channel = channel;
  1093. return 0;
  1094. }
  1095. /*****************\
  1096. PHY calibration
  1097. \*****************/
  1098. static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
  1099. {
  1100. s32 val;
  1101. val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
  1102. return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
  1103. }
  1104. void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
  1105. {
  1106. int i;
  1107. ah->ah_nfcal_hist.index = 0;
  1108. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
  1109. ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
  1110. }
  1111. static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
  1112. {
  1113. struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
  1114. hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
  1115. hist->nfval[hist->index] = noise_floor;
  1116. }
  1117. static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
  1118. {
  1119. s16 sort[ATH5K_NF_CAL_HIST_MAX];
  1120. s16 tmp;
  1121. int i, j;
  1122. memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
  1123. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
  1124. for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
  1125. if (sort[j] > sort[j - 1]) {
  1126. tmp = sort[j];
  1127. sort[j] = sort[j - 1];
  1128. sort[j - 1] = tmp;
  1129. }
  1130. }
  1131. }
  1132. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
  1133. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1134. "cal %d:%d\n", i, sort[i]);
  1135. }
  1136. return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
  1137. }
  1138. /*
  1139. * When we tell the hardware to perform a noise floor calibration
  1140. * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
  1141. * sample-and-hold the minimum noise level seen at the antennas.
  1142. * This value is then stored in a ring buffer of recently measured
  1143. * noise floor values so we have a moving window of the last few
  1144. * samples.
  1145. *
  1146. * The median of the values in the history is then loaded into the
  1147. * hardware for its own use for RSSI and CCA measurements.
  1148. */
  1149. void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
  1150. {
  1151. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1152. u32 val;
  1153. s16 nf, threshold;
  1154. u8 ee_mode;
  1155. /* keep last value if calibration hasn't completed */
  1156. if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
  1157. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1158. "NF did not complete in calibration window\n");
  1159. return;
  1160. }
  1161. ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
  1162. /* completed NF calibration, test threshold */
  1163. nf = ath5k_hw_read_measured_noise_floor(ah);
  1164. threshold = ee->ee_noise_floor_thr[ee_mode];
  1165. if (nf > threshold) {
  1166. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1167. "noise floor failure detected; "
  1168. "read %d, threshold %d\n",
  1169. nf, threshold);
  1170. nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
  1171. }
  1172. ath5k_hw_update_nfcal_hist(ah, nf);
  1173. nf = ath5k_hw_get_median_noise_floor(ah);
  1174. /* load noise floor (in .5 dBm) so the hardware will use it */
  1175. val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
  1176. val |= (nf * 2) & AR5K_PHY_NF_M;
  1177. ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
  1178. AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
  1179. ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
  1180. ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
  1181. 0, false);
  1182. /*
  1183. * Load a high max CCA Power value (-50 dBm in .5 dBm units)
  1184. * so that we're not capped by the median we just loaded.
  1185. * This will be used as the initial value for the next noise
  1186. * floor calibration.
  1187. */
  1188. val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
  1189. ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
  1190. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1191. AR5K_PHY_AGCCTL_NF_EN |
  1192. AR5K_PHY_AGCCTL_NF_NOUPDATE |
  1193. AR5K_PHY_AGCCTL_NF);
  1194. ah->ah_noise_floor = nf;
  1195. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1196. "noise floor calibrated: %d\n", nf);
  1197. }
  1198. /*
  1199. * Perform a PHY calibration on RF5110
  1200. * -Fix BPSK/QAM Constellation (I/Q correction)
  1201. */
  1202. static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
  1203. struct ieee80211_channel *channel)
  1204. {
  1205. u32 phy_sig, phy_agc, phy_sat, beacon;
  1206. int ret;
  1207. /*
  1208. * Disable beacons and RX/TX queues, wait
  1209. */
  1210. AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1211. AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
  1212. beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
  1213. ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
  1214. mdelay(2);
  1215. /*
  1216. * Set the channel (with AGC turned off)
  1217. */
  1218. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1219. udelay(10);
  1220. ret = ath5k_hw_channel(ah, channel);
  1221. /*
  1222. * Activate PHY and wait
  1223. */
  1224. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  1225. mdelay(1);
  1226. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1227. if (ret)
  1228. return ret;
  1229. /*
  1230. * Calibrate the radio chip
  1231. */
  1232. /* Remember normal state */
  1233. phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
  1234. phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
  1235. phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
  1236. /* Update radio registers */
  1237. ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
  1238. AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
  1239. ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
  1240. AR5K_PHY_AGCCOARSE_LO)) |
  1241. AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
  1242. AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
  1243. ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
  1244. AR5K_PHY_ADCSAT_THR)) |
  1245. AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
  1246. AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
  1247. udelay(20);
  1248. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1249. udelay(10);
  1250. ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
  1251. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1252. mdelay(1);
  1253. /*
  1254. * Enable calibration and wait until completion
  1255. */
  1256. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
  1257. ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  1258. AR5K_PHY_AGCCTL_CAL, 0, false);
  1259. /* Reset to normal state */
  1260. ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
  1261. ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
  1262. ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
  1263. if (ret) {
  1264. ATH5K_ERR(ah, "calibration timeout (%uMHz)\n",
  1265. channel->center_freq);
  1266. return ret;
  1267. }
  1268. /*
  1269. * Re-enable RX/TX and beacons
  1270. */
  1271. AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1272. AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
  1273. ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
  1274. return 0;
  1275. }
  1276. /*
  1277. * Perform I/Q calibration on RF5111/5112 and newer chips
  1278. */
  1279. static int
  1280. ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
  1281. {
  1282. u32 i_pwr, q_pwr;
  1283. s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
  1284. int i;
  1285. if (!ah->ah_calibration ||
  1286. ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
  1287. return 0;
  1288. /* Calibration has finished, get the results and re-run */
  1289. /* work around empty results which can apparently happen on 5212 */
  1290. for (i = 0; i <= 10; i++) {
  1291. iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
  1292. i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
  1293. q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
  1294. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
  1295. "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
  1296. if (i_pwr && q_pwr)
  1297. break;
  1298. }
  1299. i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
  1300. if (ah->ah_version == AR5K_AR5211)
  1301. q_coffd = q_pwr >> 6;
  1302. else
  1303. q_coffd = q_pwr >> 7;
  1304. /* protect against divide by 0 and loss of sign bits */
  1305. if (i_coffd == 0 || q_coffd < 2)
  1306. return 0;
  1307. i_coff = (-iq_corr) / i_coffd;
  1308. i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
  1309. if (ah->ah_version == AR5K_AR5211)
  1310. q_coff = (i_pwr / q_coffd) - 64;
  1311. else
  1312. q_coff = (i_pwr / q_coffd) - 128;
  1313. q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
  1314. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
  1315. "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
  1316. i_coff, q_coff, i_coffd, q_coffd);
  1317. /* Commit new I/Q values (set enable bit last to match HAL sources) */
  1318. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
  1319. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
  1320. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
  1321. /* Re-enable calibration -if we don't we'll commit
  1322. * the same values again and again */
  1323. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
  1324. AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
  1325. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
  1326. return 0;
  1327. }
  1328. /*
  1329. * Perform a PHY calibration
  1330. */
  1331. int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
  1332. struct ieee80211_channel *channel)
  1333. {
  1334. int ret;
  1335. if (ah->ah_radio == AR5K_RF5110)
  1336. return ath5k_hw_rf5110_calibrate(ah, channel);
  1337. ret = ath5k_hw_rf511x_iq_calibrate(ah);
  1338. if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
  1339. (channel->hw_value & CHANNEL_OFDM))
  1340. ath5k_hw_request_rfgain_probe(ah);
  1341. return ret;
  1342. }
  1343. /***************************\
  1344. * Spur mitigation functions *
  1345. \***************************/
  1346. static void
  1347. ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
  1348. struct ieee80211_channel *channel)
  1349. {
  1350. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1351. u32 mag_mask[4] = {0, 0, 0, 0};
  1352. u32 pilot_mask[2] = {0, 0};
  1353. /* Note: fbin values are scaled up by 2 */
  1354. u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
  1355. s32 spur_delta_phase, spur_freq_sigma_delta;
  1356. s32 spur_offset, num_symbols_x16;
  1357. u8 num_symbol_offsets, i, freq_band;
  1358. /* Convert current frequency to fbin value (the same way channels
  1359. * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
  1360. * up by 2 so we can compare it later */
  1361. if (channel->hw_value & CHANNEL_2GHZ) {
  1362. chan_fbin = (channel->center_freq - 2300) * 10;
  1363. freq_band = AR5K_EEPROM_BAND_2GHZ;
  1364. } else {
  1365. chan_fbin = (channel->center_freq - 4900) * 10;
  1366. freq_band = AR5K_EEPROM_BAND_5GHZ;
  1367. }
  1368. /* Check if any spur_chan_fbin from EEPROM is
  1369. * within our current channel's spur detection range */
  1370. spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
  1371. spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
  1372. /* XXX: Half/Quarter channels ?*/
  1373. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  1374. spur_detection_window *= 2;
  1375. for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
  1376. spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
  1377. /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
  1378. * so it's zero if we got nothing from EEPROM */
  1379. if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
  1380. spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
  1381. break;
  1382. }
  1383. if ((chan_fbin - spur_detection_window <=
  1384. (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
  1385. (chan_fbin + spur_detection_window >=
  1386. (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
  1387. spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
  1388. break;
  1389. }
  1390. }
  1391. /* We need to enable spur filter for this channel */
  1392. if (spur_chan_fbin) {
  1393. spur_offset = spur_chan_fbin - chan_fbin;
  1394. /*
  1395. * Calculate deltas:
  1396. * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
  1397. * spur_delta_phase -> spur_offset / chip_freq << 11
  1398. * Note: Both values have 100Hz resolution
  1399. */
  1400. switch (ah->ah_bwmode) {
  1401. case AR5K_BWMODE_40MHZ:
  1402. /* Both sample_freq and chip_freq are 80MHz */
  1403. spur_delta_phase = (spur_offset << 16) / 25;
  1404. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1405. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
  1406. break;
  1407. case AR5K_BWMODE_10MHZ:
  1408. /* Both sample_freq and chip_freq are 20MHz (?) */
  1409. spur_delta_phase = (spur_offset << 18) / 25;
  1410. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1411. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
  1412. case AR5K_BWMODE_5MHZ:
  1413. /* Both sample_freq and chip_freq are 10MHz (?) */
  1414. spur_delta_phase = (spur_offset << 19) / 25;
  1415. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1416. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
  1417. default:
  1418. if (channel->hw_value == CHANNEL_A) {
  1419. /* Both sample_freq and chip_freq are 40MHz */
  1420. spur_delta_phase = (spur_offset << 17) / 25;
  1421. spur_freq_sigma_delta =
  1422. (spur_delta_phase >> 10);
  1423. symbol_width =
  1424. AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
  1425. } else {
  1426. /* sample_freq -> 40MHz chip_freq -> 44MHz
  1427. * (for b compatibility) */
  1428. spur_delta_phase = (spur_offset << 17) / 25;
  1429. spur_freq_sigma_delta =
  1430. (spur_offset << 8) / 55;
  1431. symbol_width =
  1432. AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
  1433. }
  1434. break;
  1435. }
  1436. /* Calculate pilot and magnitude masks */
  1437. /* Scale up spur_offset by 1000 to switch to 100HZ resolution
  1438. * and divide by symbol_width to find how many symbols we have
  1439. * Note: number of symbols is scaled up by 16 */
  1440. num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
  1441. /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
  1442. if (!(num_symbols_x16 & 0xF))
  1443. /* _X_ */
  1444. num_symbol_offsets = 3;
  1445. else
  1446. /* _xx_ */
  1447. num_symbol_offsets = 4;
  1448. for (i = 0; i < num_symbol_offsets; i++) {
  1449. /* Calculate pilot mask */
  1450. s32 curr_sym_off =
  1451. (num_symbols_x16 / 16) + i + 25;
  1452. /* Pilot magnitude mask seems to be a way to
  1453. * declare the boundaries for our detection
  1454. * window or something, it's 2 for the middle
  1455. * value(s) where the symbol is expected to be
  1456. * and 1 on the boundary values */
  1457. u8 plt_mag_map =
  1458. (i == 0 || i == (num_symbol_offsets - 1))
  1459. ? 1 : 2;
  1460. if (curr_sym_off >= 0 && curr_sym_off <= 32) {
  1461. if (curr_sym_off <= 25)
  1462. pilot_mask[0] |= 1 << curr_sym_off;
  1463. else if (curr_sym_off >= 27)
  1464. pilot_mask[0] |= 1 << (curr_sym_off - 1);
  1465. } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
  1466. pilot_mask[1] |= 1 << (curr_sym_off - 33);
  1467. /* Calculate magnitude mask (for viterbi decoder) */
  1468. if (curr_sym_off >= -1 && curr_sym_off <= 14)
  1469. mag_mask[0] |=
  1470. plt_mag_map << (curr_sym_off + 1) * 2;
  1471. else if (curr_sym_off >= 15 && curr_sym_off <= 30)
  1472. mag_mask[1] |=
  1473. plt_mag_map << (curr_sym_off - 15) * 2;
  1474. else if (curr_sym_off >= 31 && curr_sym_off <= 46)
  1475. mag_mask[2] |=
  1476. plt_mag_map << (curr_sym_off - 31) * 2;
  1477. else if (curr_sym_off >= 47 && curr_sym_off <= 53)
  1478. mag_mask[3] |=
  1479. plt_mag_map << (curr_sym_off - 47) * 2;
  1480. }
  1481. /* Write settings on hw to enable spur filter */
  1482. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1483. AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
  1484. /* XXX: Self correlator also ? */
  1485. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
  1486. AR5K_PHY_IQ_PILOT_MASK_EN |
  1487. AR5K_PHY_IQ_CHAN_MASK_EN |
  1488. AR5K_PHY_IQ_SPUR_FILT_EN);
  1489. /* Set delta phase and freq sigma delta */
  1490. ath5k_hw_reg_write(ah,
  1491. AR5K_REG_SM(spur_delta_phase,
  1492. AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
  1493. AR5K_REG_SM(spur_freq_sigma_delta,
  1494. AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
  1495. AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
  1496. AR5K_PHY_TIMING_11);
  1497. /* Write pilot masks */
  1498. ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
  1499. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
  1500. AR5K_PHY_TIMING_8_PILOT_MASK_2,
  1501. pilot_mask[1]);
  1502. ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
  1503. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
  1504. AR5K_PHY_TIMING_10_PILOT_MASK_2,
  1505. pilot_mask[1]);
  1506. /* Write magnitude masks */
  1507. ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
  1508. ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
  1509. ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
  1510. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1511. AR5K_PHY_BIN_MASK_CTL_MASK_4,
  1512. mag_mask[3]);
  1513. ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
  1514. ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
  1515. ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
  1516. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
  1517. AR5K_PHY_BIN_MASK2_4_MASK_4,
  1518. mag_mask[3]);
  1519. } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
  1520. AR5K_PHY_IQ_SPUR_FILT_EN) {
  1521. /* Clean up spur mitigation settings and disable filter */
  1522. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1523. AR5K_PHY_BIN_MASK_CTL_RATE, 0);
  1524. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
  1525. AR5K_PHY_IQ_PILOT_MASK_EN |
  1526. AR5K_PHY_IQ_CHAN_MASK_EN |
  1527. AR5K_PHY_IQ_SPUR_FILT_EN);
  1528. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
  1529. /* Clear pilot masks */
  1530. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
  1531. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
  1532. AR5K_PHY_TIMING_8_PILOT_MASK_2,
  1533. 0);
  1534. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
  1535. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
  1536. AR5K_PHY_TIMING_10_PILOT_MASK_2,
  1537. 0);
  1538. /* Clear magnitude masks */
  1539. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
  1540. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
  1541. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
  1542. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1543. AR5K_PHY_BIN_MASK_CTL_MASK_4,
  1544. 0);
  1545. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
  1546. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
  1547. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
  1548. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
  1549. AR5K_PHY_BIN_MASK2_4_MASK_4,
  1550. 0);
  1551. }
  1552. }
  1553. /*****************\
  1554. * Antenna control *
  1555. \*****************/
  1556. static void /*TODO:Boundary check*/
  1557. ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
  1558. {
  1559. if (ah->ah_version != AR5K_AR5210)
  1560. ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
  1561. }
  1562. /*
  1563. * Enable/disable fast rx antenna diversity
  1564. */
  1565. static void
  1566. ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
  1567. {
  1568. switch (ee_mode) {
  1569. case AR5K_EEPROM_MODE_11G:
  1570. /* XXX: This is set to
  1571. * disabled on initvals !!! */
  1572. case AR5K_EEPROM_MODE_11A:
  1573. if (enable)
  1574. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1575. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1576. else
  1577. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1578. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1579. break;
  1580. case AR5K_EEPROM_MODE_11B:
  1581. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1582. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1583. break;
  1584. default:
  1585. return;
  1586. }
  1587. if (enable) {
  1588. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
  1589. AR5K_PHY_RESTART_DIV_GC, 4);
  1590. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
  1591. AR5K_PHY_FAST_ANT_DIV_EN);
  1592. } else {
  1593. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
  1594. AR5K_PHY_RESTART_DIV_GC, 0);
  1595. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
  1596. AR5K_PHY_FAST_ANT_DIV_EN);
  1597. }
  1598. }
  1599. void
  1600. ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
  1601. {
  1602. u8 ant0, ant1;
  1603. /*
  1604. * In case a fixed antenna was set as default
  1605. * use the same switch table twice.
  1606. */
  1607. if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
  1608. ant0 = ant1 = AR5K_ANT_SWTABLE_A;
  1609. else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
  1610. ant0 = ant1 = AR5K_ANT_SWTABLE_B;
  1611. else {
  1612. ant0 = AR5K_ANT_SWTABLE_A;
  1613. ant1 = AR5K_ANT_SWTABLE_B;
  1614. }
  1615. /* Set antenna idle switch table */
  1616. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
  1617. AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
  1618. (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
  1619. AR5K_PHY_ANT_CTL_TXRX_EN));
  1620. /* Set antenna switch tables */
  1621. ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
  1622. AR5K_PHY_ANT_SWITCH_TABLE_0);
  1623. ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
  1624. AR5K_PHY_ANT_SWITCH_TABLE_1);
  1625. }
  1626. /*
  1627. * Set antenna operating mode
  1628. */
  1629. void
  1630. ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
  1631. {
  1632. struct ieee80211_channel *channel = ah->ah_current_channel;
  1633. bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
  1634. bool use_def_for_sg;
  1635. int ee_mode;
  1636. u8 def_ant, tx_ant;
  1637. u32 sta_id1 = 0;
  1638. /* if channel is not initialized yet we can't set the antennas
  1639. * so just store the mode. it will be set on the next reset */
  1640. if (channel == NULL) {
  1641. ah->ah_ant_mode = ant_mode;
  1642. return;
  1643. }
  1644. def_ant = ah->ah_def_ant;
  1645. ee_mode = ath5k_eeprom_mode_from_channel(channel);
  1646. if (ee_mode < 0) {
  1647. ATH5K_ERR(ah,
  1648. "invalid channel: %d\n", channel->center_freq);
  1649. return;
  1650. }
  1651. switch (ant_mode) {
  1652. case AR5K_ANTMODE_DEFAULT:
  1653. tx_ant = 0;
  1654. use_def_for_tx = false;
  1655. update_def_on_tx = false;
  1656. use_def_for_rts = false;
  1657. use_def_for_sg = false;
  1658. fast_div = true;
  1659. break;
  1660. case AR5K_ANTMODE_FIXED_A:
  1661. def_ant = 1;
  1662. tx_ant = 1;
  1663. use_def_for_tx = true;
  1664. update_def_on_tx = false;
  1665. use_def_for_rts = true;
  1666. use_def_for_sg = true;
  1667. fast_div = false;
  1668. break;
  1669. case AR5K_ANTMODE_FIXED_B:
  1670. def_ant = 2;
  1671. tx_ant = 2;
  1672. use_def_for_tx = true;
  1673. update_def_on_tx = false;
  1674. use_def_for_rts = true;
  1675. use_def_for_sg = true;
  1676. fast_div = false;
  1677. break;
  1678. case AR5K_ANTMODE_SINGLE_AP:
  1679. def_ant = 1; /* updated on tx */
  1680. tx_ant = 0;
  1681. use_def_for_tx = true;
  1682. update_def_on_tx = true;
  1683. use_def_for_rts = true;
  1684. use_def_for_sg = true;
  1685. fast_div = true;
  1686. break;
  1687. case AR5K_ANTMODE_SECTOR_AP:
  1688. tx_ant = 1; /* variable */
  1689. use_def_for_tx = false;
  1690. update_def_on_tx = false;
  1691. use_def_for_rts = true;
  1692. use_def_for_sg = false;
  1693. fast_div = false;
  1694. break;
  1695. case AR5K_ANTMODE_SECTOR_STA:
  1696. tx_ant = 1; /* variable */
  1697. use_def_for_tx = true;
  1698. update_def_on_tx = false;
  1699. use_def_for_rts = true;
  1700. use_def_for_sg = false;
  1701. fast_div = true;
  1702. break;
  1703. case AR5K_ANTMODE_DEBUG:
  1704. def_ant = 1;
  1705. tx_ant = 2;
  1706. use_def_for_tx = false;
  1707. update_def_on_tx = false;
  1708. use_def_for_rts = false;
  1709. use_def_for_sg = false;
  1710. fast_div = false;
  1711. break;
  1712. default:
  1713. return;
  1714. }
  1715. ah->ah_tx_ant = tx_ant;
  1716. ah->ah_ant_mode = ant_mode;
  1717. ah->ah_def_ant = def_ant;
  1718. sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
  1719. sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
  1720. sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
  1721. sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
  1722. AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
  1723. if (sta_id1)
  1724. AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
  1725. ath5k_hw_set_antenna_switch(ah, ee_mode);
  1726. /* Note: set diversity before default antenna
  1727. * because it won't work correctly */
  1728. ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
  1729. ath5k_hw_set_def_antenna(ah, def_ant);
  1730. }
  1731. /****************\
  1732. * TX power setup *
  1733. \****************/
  1734. /*
  1735. * Helper functions
  1736. */
  1737. /*
  1738. * Do linear interpolation between two given (x, y) points
  1739. */
  1740. static s16
  1741. ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
  1742. s16 y_left, s16 y_right)
  1743. {
  1744. s16 ratio, result;
  1745. /* Avoid divide by zero and skip interpolation
  1746. * if we have the same point */
  1747. if ((x_left == x_right) || (y_left == y_right))
  1748. return y_left;
  1749. /*
  1750. * Since we use ints and not fps, we need to scale up in
  1751. * order to get a sane ratio value (or else we 'll eg. get
  1752. * always 1 instead of 1.25, 1.75 etc). We scale up by 100
  1753. * to have some accuracy both for 0.5 and 0.25 steps.
  1754. */
  1755. ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
  1756. /* Now scale down to be in range */
  1757. result = y_left + (ratio * (target - x_left) / 100);
  1758. return result;
  1759. }
  1760. /*
  1761. * Find vertical boundary (min pwr) for the linear PCDAC curve.
  1762. *
  1763. * Since we have the top of the curve and we draw the line below
  1764. * until we reach 1 (1 pcdac step) we need to know which point
  1765. * (x value) that is so that we don't go below y axis and have negative
  1766. * pcdac values when creating the curve, or fill the table with zeroes.
  1767. */
  1768. static s16
  1769. ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
  1770. const s16 *pwrL, const s16 *pwrR)
  1771. {
  1772. s8 tmp;
  1773. s16 min_pwrL, min_pwrR;
  1774. s16 pwr_i;
  1775. /* Some vendors write the same pcdac value twice !!! */
  1776. if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
  1777. return max(pwrL[0], pwrR[0]);
  1778. if (pwrL[0] == pwrL[1])
  1779. min_pwrL = pwrL[0];
  1780. else {
  1781. pwr_i = pwrL[0];
  1782. do {
  1783. pwr_i--;
  1784. tmp = (s8) ath5k_get_interpolated_value(pwr_i,
  1785. pwrL[0], pwrL[1],
  1786. stepL[0], stepL[1]);
  1787. } while (tmp > 1);
  1788. min_pwrL = pwr_i;
  1789. }
  1790. if (pwrR[0] == pwrR[1])
  1791. min_pwrR = pwrR[0];
  1792. else {
  1793. pwr_i = pwrR[0];
  1794. do {
  1795. pwr_i--;
  1796. tmp = (s8) ath5k_get_interpolated_value(pwr_i,
  1797. pwrR[0], pwrR[1],
  1798. stepR[0], stepR[1]);
  1799. } while (tmp > 1);
  1800. min_pwrR = pwr_i;
  1801. }
  1802. /* Keep the right boundary so that it works for both curves */
  1803. return max(min_pwrL, min_pwrR);
  1804. }
  1805. /*
  1806. * Interpolate (pwr,vpd) points to create a Power to PDADC or a
  1807. * Power to PCDAC curve.
  1808. *
  1809. * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
  1810. * steps (offsets) on y axis. Power can go up to 31.5dB and max
  1811. * PCDAC/PDADC step for each curve is 64 but we can write more than
  1812. * one curves on hw so we can go up to 128 (which is the max step we
  1813. * can write on the final table).
  1814. *
  1815. * We write y values (PCDAC/PDADC steps) on hw.
  1816. */
  1817. static void
  1818. ath5k_create_power_curve(s16 pmin, s16 pmax,
  1819. const s16 *pwr, const u8 *vpd,
  1820. u8 num_points,
  1821. u8 *vpd_table, u8 type)
  1822. {
  1823. u8 idx[2] = { 0, 1 };
  1824. s16 pwr_i = 2 * pmin;
  1825. int i;
  1826. if (num_points < 2)
  1827. return;
  1828. /* We want the whole line, so adjust boundaries
  1829. * to cover the entire power range. Note that
  1830. * power values are already 0.25dB so no need
  1831. * to multiply pwr_i by 2 */
  1832. if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
  1833. pwr_i = pmin;
  1834. pmin = 0;
  1835. pmax = 63;
  1836. }
  1837. /* Find surrounding turning points (TPs)
  1838. * and interpolate between them */
  1839. for (i = 0; (i <= (u16) (pmax - pmin)) &&
  1840. (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
  1841. /* We passed the right TP, move to the next set of TPs
  1842. * if we pass the last TP, extrapolate above using the last
  1843. * two TPs for ratio */
  1844. if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
  1845. idx[0]++;
  1846. idx[1]++;
  1847. }
  1848. vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
  1849. pwr[idx[0]], pwr[idx[1]],
  1850. vpd[idx[0]], vpd[idx[1]]);
  1851. /* Increase by 0.5dB
  1852. * (0.25 dB units) */
  1853. pwr_i += 2;
  1854. }
  1855. }
  1856. /*
  1857. * Get the surrounding per-channel power calibration piers
  1858. * for a given frequency so that we can interpolate between
  1859. * them and come up with an appropriate dataset for our current
  1860. * channel.
  1861. */
  1862. static void
  1863. ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
  1864. struct ieee80211_channel *channel,
  1865. struct ath5k_chan_pcal_info **pcinfo_l,
  1866. struct ath5k_chan_pcal_info **pcinfo_r)
  1867. {
  1868. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1869. struct ath5k_chan_pcal_info *pcinfo;
  1870. u8 idx_l, idx_r;
  1871. u8 mode, max, i;
  1872. u32 target = channel->center_freq;
  1873. idx_l = 0;
  1874. idx_r = 0;
  1875. if (!(channel->hw_value & CHANNEL_OFDM)) {
  1876. pcinfo = ee->ee_pwr_cal_b;
  1877. mode = AR5K_EEPROM_MODE_11B;
  1878. } else if (channel->hw_value & CHANNEL_2GHZ) {
  1879. pcinfo = ee->ee_pwr_cal_g;
  1880. mode = AR5K_EEPROM_MODE_11G;
  1881. } else {
  1882. pcinfo = ee->ee_pwr_cal_a;
  1883. mode = AR5K_EEPROM_MODE_11A;
  1884. }
  1885. max = ee->ee_n_piers[mode] - 1;
  1886. /* Frequency is below our calibrated
  1887. * range. Use the lowest power curve
  1888. * we have */
  1889. if (target < pcinfo[0].freq) {
  1890. idx_l = idx_r = 0;
  1891. goto done;
  1892. }
  1893. /* Frequency is above our calibrated
  1894. * range. Use the highest power curve
  1895. * we have */
  1896. if (target > pcinfo[max].freq) {
  1897. idx_l = idx_r = max;
  1898. goto done;
  1899. }
  1900. /* Frequency is inside our calibrated
  1901. * channel range. Pick the surrounding
  1902. * calibration piers so that we can
  1903. * interpolate */
  1904. for (i = 0; i <= max; i++) {
  1905. /* Frequency matches one of our calibration
  1906. * piers, no need to interpolate, just use
  1907. * that calibration pier */
  1908. if (pcinfo[i].freq == target) {
  1909. idx_l = idx_r = i;
  1910. goto done;
  1911. }
  1912. /* We found a calibration pier that's above
  1913. * frequency, use this pier and the previous
  1914. * one to interpolate */
  1915. if (target < pcinfo[i].freq) {
  1916. idx_r = i;
  1917. idx_l = idx_r - 1;
  1918. goto done;
  1919. }
  1920. }
  1921. done:
  1922. *pcinfo_l = &pcinfo[idx_l];
  1923. *pcinfo_r = &pcinfo[idx_r];
  1924. }
  1925. /*
  1926. * Get the surrounding per-rate power calibration data
  1927. * for a given frequency and interpolate between power
  1928. * values to set max target power supported by hw for
  1929. * each rate.
  1930. */
  1931. static void
  1932. ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
  1933. struct ieee80211_channel *channel,
  1934. struct ath5k_rate_pcal_info *rates)
  1935. {
  1936. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1937. struct ath5k_rate_pcal_info *rpinfo;
  1938. u8 idx_l, idx_r;
  1939. u8 mode, max, i;
  1940. u32 target = channel->center_freq;
  1941. idx_l = 0;
  1942. idx_r = 0;
  1943. if (!(channel->hw_value & CHANNEL_OFDM)) {
  1944. rpinfo = ee->ee_rate_tpwr_b;
  1945. mode = AR5K_EEPROM_MODE_11B;
  1946. } else if (channel->hw_value & CHANNEL_2GHZ) {
  1947. rpinfo = ee->ee_rate_tpwr_g;
  1948. mode = AR5K_EEPROM_MODE_11G;
  1949. } else {
  1950. rpinfo = ee->ee_rate_tpwr_a;
  1951. mode = AR5K_EEPROM_MODE_11A;
  1952. }
  1953. max = ee->ee_rate_target_pwr_num[mode] - 1;
  1954. /* Get the surrounding calibration
  1955. * piers - same as above */
  1956. if (target < rpinfo[0].freq) {
  1957. idx_l = idx_r = 0;
  1958. goto done;
  1959. }
  1960. if (target > rpinfo[max].freq) {
  1961. idx_l = idx_r = max;
  1962. goto done;
  1963. }
  1964. for (i = 0; i <= max; i++) {
  1965. if (rpinfo[i].freq == target) {
  1966. idx_l = idx_r = i;
  1967. goto done;
  1968. }
  1969. if (target < rpinfo[i].freq) {
  1970. idx_r = i;
  1971. idx_l = idx_r - 1;
  1972. goto done;
  1973. }
  1974. }
  1975. done:
  1976. /* Now interpolate power value, based on the frequency */
  1977. rates->freq = target;
  1978. rates->target_power_6to24 =
  1979. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1980. rpinfo[idx_r].freq,
  1981. rpinfo[idx_l].target_power_6to24,
  1982. rpinfo[idx_r].target_power_6to24);
  1983. rates->target_power_36 =
  1984. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1985. rpinfo[idx_r].freq,
  1986. rpinfo[idx_l].target_power_36,
  1987. rpinfo[idx_r].target_power_36);
  1988. rates->target_power_48 =
  1989. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1990. rpinfo[idx_r].freq,
  1991. rpinfo[idx_l].target_power_48,
  1992. rpinfo[idx_r].target_power_48);
  1993. rates->target_power_54 =
  1994. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1995. rpinfo[idx_r].freq,
  1996. rpinfo[idx_l].target_power_54,
  1997. rpinfo[idx_r].target_power_54);
  1998. }
  1999. /*
  2000. * Get the max edge power for this channel if
  2001. * we have such data from EEPROM's Conformance Test
  2002. * Limits (CTL), and limit max power if needed.
  2003. */
  2004. static void
  2005. ath5k_get_max_ctl_power(struct ath5k_hw *ah,
  2006. struct ieee80211_channel *channel)
  2007. {
  2008. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  2009. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2010. struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
  2011. u8 *ctl_val = ee->ee_ctl;
  2012. s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
  2013. s16 edge_pwr = 0;
  2014. u8 rep_idx;
  2015. u8 i, ctl_mode;
  2016. u8 ctl_idx = 0xFF;
  2017. u32 target = channel->center_freq;
  2018. ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
  2019. switch (channel->hw_value & CHANNEL_MODES) {
  2020. case CHANNEL_A:
  2021. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  2022. ctl_mode |= AR5K_CTL_TURBO;
  2023. else
  2024. ctl_mode |= AR5K_CTL_11A;
  2025. break;
  2026. case CHANNEL_G:
  2027. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  2028. ctl_mode |= AR5K_CTL_TURBOG;
  2029. else
  2030. ctl_mode |= AR5K_CTL_11G;
  2031. break;
  2032. case CHANNEL_B:
  2033. ctl_mode |= AR5K_CTL_11B;
  2034. break;
  2035. default:
  2036. return;
  2037. }
  2038. for (i = 0; i < ee->ee_ctls; i++) {
  2039. if (ctl_val[i] == ctl_mode) {
  2040. ctl_idx = i;
  2041. break;
  2042. }
  2043. }
  2044. /* If we have a CTL dataset available grab it and find the
  2045. * edge power for our frequency */
  2046. if (ctl_idx == 0xFF)
  2047. return;
  2048. /* Edge powers are sorted by frequency from lower
  2049. * to higher. Each CTL corresponds to 8 edge power
  2050. * measurements. */
  2051. rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
  2052. /* Don't do boundaries check because we
  2053. * might have more that one bands defined
  2054. * for this mode */
  2055. /* Get the edge power that's closer to our
  2056. * frequency */
  2057. for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
  2058. rep_idx += i;
  2059. if (target <= rep[rep_idx].freq)
  2060. edge_pwr = (s16) rep[rep_idx].edge;
  2061. }
  2062. if (edge_pwr)
  2063. ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
  2064. }
  2065. /*
  2066. * Power to PCDAC table functions
  2067. */
  2068. /*
  2069. * Fill Power to PCDAC table on RF5111
  2070. *
  2071. * No further processing is needed for RF5111, the only thing we have to
  2072. * do is fill the values below and above calibration range since eeprom data
  2073. * may not cover the entire PCDAC table.
  2074. */
  2075. static void
  2076. ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
  2077. s16 *table_max)
  2078. {
  2079. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2080. u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
  2081. u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
  2082. s16 min_pwr, max_pwr;
  2083. /* Get table boundaries */
  2084. min_pwr = table_min[0];
  2085. pcdac_0 = pcdac_tmp[0];
  2086. max_pwr = table_max[0];
  2087. pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
  2088. /* Extrapolate below minimum using pcdac_0 */
  2089. pcdac_i = 0;
  2090. for (i = 0; i < min_pwr; i++)
  2091. pcdac_out[pcdac_i++] = pcdac_0;
  2092. /* Copy values from pcdac_tmp */
  2093. pwr_idx = min_pwr;
  2094. for (i = 0; pwr_idx <= max_pwr &&
  2095. pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
  2096. pcdac_out[pcdac_i++] = pcdac_tmp[i];
  2097. pwr_idx++;
  2098. }
  2099. /* Extrapolate above maximum */
  2100. while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
  2101. pcdac_out[pcdac_i++] = pcdac_n;
  2102. }
  2103. /*
  2104. * Combine available XPD Curves and fill Linear Power to PCDAC table
  2105. * on RF5112
  2106. *
  2107. * RFX112 can have up to 2 curves (one for low txpower range and one for
  2108. * higher txpower range). We need to put them both on pcdac_out and place
  2109. * them in the correct location. In case we only have one curve available
  2110. * just fit it on pcdac_out (it's supposed to cover the entire range of
  2111. * available pwr levels since it's always the higher power curve). Extrapolate
  2112. * below and above final table if needed.
  2113. */
  2114. static void
  2115. ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
  2116. s16 *table_max, u8 pdcurves)
  2117. {
  2118. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2119. u8 *pcdac_low_pwr;
  2120. u8 *pcdac_high_pwr;
  2121. u8 *pcdac_tmp;
  2122. u8 pwr;
  2123. s16 max_pwr_idx;
  2124. s16 min_pwr_idx;
  2125. s16 mid_pwr_idx = 0;
  2126. /* Edge flag turns on the 7nth bit on the PCDAC
  2127. * to declare the higher power curve (force values
  2128. * to be greater than 64). If we only have one curve
  2129. * we don't need to set this, if we have 2 curves and
  2130. * fill the table backwards this can also be used to
  2131. * switch from higher power curve to lower power curve */
  2132. u8 edge_flag;
  2133. int i;
  2134. /* When we have only one curve available
  2135. * that's the higher power curve. If we have
  2136. * two curves the first is the high power curve
  2137. * and the next is the low power curve. */
  2138. if (pdcurves > 1) {
  2139. pcdac_low_pwr = ah->ah_txpower.tmpL[1];
  2140. pcdac_high_pwr = ah->ah_txpower.tmpL[0];
  2141. mid_pwr_idx = table_max[1] - table_min[1] - 1;
  2142. max_pwr_idx = (table_max[0] - table_min[0]) / 2;
  2143. /* If table size goes beyond 31.5dB, keep the
  2144. * upper 31.5dB range when setting tx power.
  2145. * Note: 126 = 31.5 dB in quarter dB steps */
  2146. if (table_max[0] - table_min[1] > 126)
  2147. min_pwr_idx = table_max[0] - 126;
  2148. else
  2149. min_pwr_idx = table_min[1];
  2150. /* Since we fill table backwards
  2151. * start from high power curve */
  2152. pcdac_tmp = pcdac_high_pwr;
  2153. edge_flag = 0x40;
  2154. } else {
  2155. pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
  2156. pcdac_high_pwr = ah->ah_txpower.tmpL[0];
  2157. min_pwr_idx = table_min[0];
  2158. max_pwr_idx = (table_max[0] - table_min[0]) / 2;
  2159. pcdac_tmp = pcdac_high_pwr;
  2160. edge_flag = 0;
  2161. }
  2162. /* This is used when setting tx power*/
  2163. ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
  2164. /* Fill Power to PCDAC table backwards */
  2165. pwr = max_pwr_idx;
  2166. for (i = 63; i >= 0; i--) {
  2167. /* Entering lower power range, reset
  2168. * edge flag and set pcdac_tmp to lower
  2169. * power curve.*/
  2170. if (edge_flag == 0x40 &&
  2171. (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
  2172. edge_flag = 0x00;
  2173. pcdac_tmp = pcdac_low_pwr;
  2174. pwr = mid_pwr_idx / 2;
  2175. }
  2176. /* Don't go below 1, extrapolate below if we have
  2177. * already switched to the lower power curve -or
  2178. * we only have one curve and edge_flag is zero
  2179. * anyway */
  2180. if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
  2181. while (i >= 0) {
  2182. pcdac_out[i] = pcdac_out[i + 1];
  2183. i--;
  2184. }
  2185. break;
  2186. }
  2187. pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
  2188. /* Extrapolate above if pcdac is greater than
  2189. * 126 -this can happen because we OR pcdac_out
  2190. * value with edge_flag on high power curve */
  2191. if (pcdac_out[i] > 126)
  2192. pcdac_out[i] = 126;
  2193. /* Decrease by a 0.5dB step */
  2194. pwr--;
  2195. }
  2196. }
  2197. /* Write PCDAC values on hw */
  2198. static void
  2199. ath5k_write_pcdac_table(struct ath5k_hw *ah)
  2200. {
  2201. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2202. int i;
  2203. /*
  2204. * Write TX power values
  2205. */
  2206. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2207. ath5k_hw_reg_write(ah,
  2208. (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
  2209. (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
  2210. AR5K_PHY_PCDAC_TXPOWER(i));
  2211. }
  2212. }
  2213. /*
  2214. * Power to PDADC table functions
  2215. */
  2216. /*
  2217. * Set the gain boundaries and create final Power to PDADC table
  2218. *
  2219. * We can have up to 4 pd curves, we need to do a similar process
  2220. * as we do for RF5112. This time we don't have an edge_flag but we
  2221. * set the gain boundaries on a separate register.
  2222. */
  2223. static void
  2224. ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
  2225. s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
  2226. {
  2227. u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
  2228. u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
  2229. u8 *pdadc_tmp;
  2230. s16 pdadc_0;
  2231. u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
  2232. u8 pd_gain_overlap;
  2233. /* Note: Register value is initialized on initvals
  2234. * there is no feedback from hw.
  2235. * XXX: What about pd_gain_overlap from EEPROM ? */
  2236. pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
  2237. AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
  2238. /* Create final PDADC table */
  2239. for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
  2240. pdadc_tmp = ah->ah_txpower.tmpL[pdg];
  2241. if (pdg == pdcurves - 1)
  2242. /* 2 dB boundary stretch for last
  2243. * (higher power) curve */
  2244. gain_boundaries[pdg] = pwr_max[pdg] + 4;
  2245. else
  2246. /* Set gain boundary in the middle
  2247. * between this curve and the next one */
  2248. gain_boundaries[pdg] =
  2249. (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
  2250. /* Sanity check in case our 2 db stretch got out of
  2251. * range. */
  2252. if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
  2253. gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
  2254. /* For the first curve (lower power)
  2255. * start from 0 dB */
  2256. if (pdg == 0)
  2257. pdadc_0 = 0;
  2258. else
  2259. /* For the other curves use the gain overlap */
  2260. pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
  2261. pd_gain_overlap;
  2262. /* Force each power step to be at least 0.5 dB */
  2263. if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
  2264. pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
  2265. else
  2266. pwr_step = 1;
  2267. /* If pdadc_0 is negative, we need to extrapolate
  2268. * below this pdgain by a number of pwr_steps */
  2269. while ((pdadc_0 < 0) && (pdadc_i < 128)) {
  2270. s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
  2271. pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
  2272. pdadc_0++;
  2273. }
  2274. /* Set last pwr level, using gain boundaries */
  2275. pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
  2276. /* Limit it to be inside pwr range */
  2277. table_size = pwr_max[pdg] - pwr_min[pdg];
  2278. max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
  2279. /* Fill pdadc_out table */
  2280. while (pdadc_0 < max_idx && pdadc_i < 128)
  2281. pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
  2282. /* Need to extrapolate above this pdgain? */
  2283. if (pdadc_n <= max_idx)
  2284. continue;
  2285. /* Force each power step to be at least 0.5 dB */
  2286. if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
  2287. pwr_step = pdadc_tmp[table_size - 1] -
  2288. pdadc_tmp[table_size - 2];
  2289. else
  2290. pwr_step = 1;
  2291. /* Extrapolate above */
  2292. while ((pdadc_0 < (s16) pdadc_n) &&
  2293. (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
  2294. s16 tmp = pdadc_tmp[table_size - 1] +
  2295. (pdadc_0 - max_idx) * pwr_step;
  2296. pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
  2297. pdadc_0++;
  2298. }
  2299. }
  2300. while (pdg < AR5K_EEPROM_N_PD_GAINS) {
  2301. gain_boundaries[pdg] = gain_boundaries[pdg - 1];
  2302. pdg++;
  2303. }
  2304. while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
  2305. pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
  2306. pdadc_i++;
  2307. }
  2308. /* Set gain boundaries */
  2309. ath5k_hw_reg_write(ah,
  2310. AR5K_REG_SM(pd_gain_overlap,
  2311. AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
  2312. AR5K_REG_SM(gain_boundaries[0],
  2313. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
  2314. AR5K_REG_SM(gain_boundaries[1],
  2315. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
  2316. AR5K_REG_SM(gain_boundaries[2],
  2317. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
  2318. AR5K_REG_SM(gain_boundaries[3],
  2319. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
  2320. AR5K_PHY_TPC_RG5);
  2321. /* Used for setting rate power table */
  2322. ah->ah_txpower.txp_min_idx = pwr_min[0];
  2323. }
  2324. /* Write PDADC values on hw */
  2325. static void
  2326. ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
  2327. {
  2328. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2329. u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
  2330. u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
  2331. u8 pdcurves = ee->ee_pd_gains[ee_mode];
  2332. u32 reg;
  2333. u8 i;
  2334. /* Select the right pdgain curves */
  2335. /* Clear current settings */
  2336. reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
  2337. reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
  2338. AR5K_PHY_TPC_RG1_PDGAIN_2 |
  2339. AR5K_PHY_TPC_RG1_PDGAIN_3 |
  2340. AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
  2341. /*
  2342. * Use pd_gains curve from eeprom
  2343. *
  2344. * This overrides the default setting from initvals
  2345. * in case some vendors (e.g. Zcomax) don't use the default
  2346. * curves. If we don't honor their settings we 'll get a
  2347. * 5dB (1 * gain overlap ?) drop.
  2348. */
  2349. reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
  2350. switch (pdcurves) {
  2351. case 3:
  2352. reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
  2353. /* Fall through */
  2354. case 2:
  2355. reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
  2356. /* Fall through */
  2357. case 1:
  2358. reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
  2359. break;
  2360. }
  2361. ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
  2362. /*
  2363. * Write TX power values
  2364. */
  2365. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2366. u32 val = get_unaligned_le32(&pdadc_out[4 * i]);
  2367. ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i));
  2368. }
  2369. }
  2370. /*
  2371. * Common code for PCDAC/PDADC tables
  2372. */
  2373. /*
  2374. * This is the main function that uses all of the above
  2375. * to set PCDAC/PDADC table on hw for the current channel.
  2376. * This table is used for tx power calibration on the baseband,
  2377. * without it we get weird tx power levels and in some cases
  2378. * distorted spectral mask
  2379. */
  2380. static int
  2381. ath5k_setup_channel_powertable(struct ath5k_hw *ah,
  2382. struct ieee80211_channel *channel,
  2383. u8 ee_mode, u8 type)
  2384. {
  2385. struct ath5k_pdgain_info *pdg_L, *pdg_R;
  2386. struct ath5k_chan_pcal_info *pcinfo_L;
  2387. struct ath5k_chan_pcal_info *pcinfo_R;
  2388. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2389. u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
  2390. s16 table_min[AR5K_EEPROM_N_PD_GAINS];
  2391. s16 table_max[AR5K_EEPROM_N_PD_GAINS];
  2392. u8 *tmpL;
  2393. u8 *tmpR;
  2394. u32 target = channel->center_freq;
  2395. int pdg, i;
  2396. /* Get surrounding freq piers for this channel */
  2397. ath5k_get_chan_pcal_surrounding_piers(ah, channel,
  2398. &pcinfo_L,
  2399. &pcinfo_R);
  2400. /* Loop over pd gain curves on
  2401. * surrounding freq piers by index */
  2402. for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
  2403. /* Fill curves in reverse order
  2404. * from lower power (max gain)
  2405. * to higher power. Use curve -> idx
  2406. * backmapping we did on eeprom init */
  2407. u8 idx = pdg_curve_to_idx[pdg];
  2408. /* Grab the needed curves by index */
  2409. pdg_L = &pcinfo_L->pd_curves[idx];
  2410. pdg_R = &pcinfo_R->pd_curves[idx];
  2411. /* Initialize the temp tables */
  2412. tmpL = ah->ah_txpower.tmpL[pdg];
  2413. tmpR = ah->ah_txpower.tmpR[pdg];
  2414. /* Set curve's x boundaries and create
  2415. * curves so that they cover the same
  2416. * range (if we don't do that one table
  2417. * will have values on some range and the
  2418. * other one won't have any so interpolation
  2419. * will fail) */
  2420. table_min[pdg] = min(pdg_L->pd_pwr[0],
  2421. pdg_R->pd_pwr[0]) / 2;
  2422. table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
  2423. pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
  2424. /* Now create the curves on surrounding channels
  2425. * and interpolate if needed to get the final
  2426. * curve for this gain on this channel */
  2427. switch (type) {
  2428. case AR5K_PWRTABLE_LINEAR_PCDAC:
  2429. /* Override min/max so that we don't loose
  2430. * accuracy (don't divide by 2) */
  2431. table_min[pdg] = min(pdg_L->pd_pwr[0],
  2432. pdg_R->pd_pwr[0]);
  2433. table_max[pdg] =
  2434. max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
  2435. pdg_R->pd_pwr[pdg_R->pd_points - 1]);
  2436. /* Override minimum so that we don't get
  2437. * out of bounds while extrapolating
  2438. * below. Don't do this when we have 2
  2439. * curves and we are on the high power curve
  2440. * because table_min is ok in this case */
  2441. if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
  2442. table_min[pdg] =
  2443. ath5k_get_linear_pcdac_min(pdg_L->pd_step,
  2444. pdg_R->pd_step,
  2445. pdg_L->pd_pwr,
  2446. pdg_R->pd_pwr);
  2447. /* Don't go too low because we will
  2448. * miss the upper part of the curve.
  2449. * Note: 126 = 31.5dB (max power supported)
  2450. * in 0.25dB units */
  2451. if (table_max[pdg] - table_min[pdg] > 126)
  2452. table_min[pdg] = table_max[pdg] - 126;
  2453. }
  2454. /* Fall through */
  2455. case AR5K_PWRTABLE_PWR_TO_PCDAC:
  2456. case AR5K_PWRTABLE_PWR_TO_PDADC:
  2457. ath5k_create_power_curve(table_min[pdg],
  2458. table_max[pdg],
  2459. pdg_L->pd_pwr,
  2460. pdg_L->pd_step,
  2461. pdg_L->pd_points, tmpL, type);
  2462. /* We are in a calibration
  2463. * pier, no need to interpolate
  2464. * between freq piers */
  2465. if (pcinfo_L == pcinfo_R)
  2466. continue;
  2467. ath5k_create_power_curve(table_min[pdg],
  2468. table_max[pdg],
  2469. pdg_R->pd_pwr,
  2470. pdg_R->pd_step,
  2471. pdg_R->pd_points, tmpR, type);
  2472. break;
  2473. default:
  2474. return -EINVAL;
  2475. }
  2476. /* Interpolate between curves
  2477. * of surrounding freq piers to
  2478. * get the final curve for this
  2479. * pd gain. Re-use tmpL for interpolation
  2480. * output */
  2481. for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
  2482. (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
  2483. tmpL[i] = (u8) ath5k_get_interpolated_value(target,
  2484. (s16) pcinfo_L->freq,
  2485. (s16) pcinfo_R->freq,
  2486. (s16) tmpL[i],
  2487. (s16) tmpR[i]);
  2488. }
  2489. }
  2490. /* Now we have a set of curves for this
  2491. * channel on tmpL (x range is table_max - table_min
  2492. * and y values are tmpL[pdg][]) sorted in the same
  2493. * order as EEPROM (because we've used the backmapping).
  2494. * So for RF5112 it's from higher power to lower power
  2495. * and for RF2413 it's from lower power to higher power.
  2496. * For RF5111 we only have one curve. */
  2497. /* Fill min and max power levels for this
  2498. * channel by interpolating the values on
  2499. * surrounding channels to complete the dataset */
  2500. ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
  2501. (s16) pcinfo_L->freq,
  2502. (s16) pcinfo_R->freq,
  2503. pcinfo_L->min_pwr, pcinfo_R->min_pwr);
  2504. ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
  2505. (s16) pcinfo_L->freq,
  2506. (s16) pcinfo_R->freq,
  2507. pcinfo_L->max_pwr, pcinfo_R->max_pwr);
  2508. /* Fill PCDAC/PDADC table */
  2509. switch (type) {
  2510. case AR5K_PWRTABLE_LINEAR_PCDAC:
  2511. /* For RF5112 we can have one or two curves
  2512. * and each curve covers a certain power lvl
  2513. * range so we need to do some more processing */
  2514. ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
  2515. ee->ee_pd_gains[ee_mode]);
  2516. /* Set txp.offset so that we can
  2517. * match max power value with max
  2518. * table index */
  2519. ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
  2520. break;
  2521. case AR5K_PWRTABLE_PWR_TO_PCDAC:
  2522. /* We are done for RF5111 since it has only
  2523. * one curve, just fit the curve on the table */
  2524. ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
  2525. /* No rate powertable adjustment for RF5111 */
  2526. ah->ah_txpower.txp_min_idx = 0;
  2527. ah->ah_txpower.txp_offset = 0;
  2528. break;
  2529. case AR5K_PWRTABLE_PWR_TO_PDADC:
  2530. /* Set PDADC boundaries and fill
  2531. * final PDADC table */
  2532. ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
  2533. ee->ee_pd_gains[ee_mode]);
  2534. /* Set txp.offset, note that table_min
  2535. * can be negative */
  2536. ah->ah_txpower.txp_offset = table_min[0];
  2537. break;
  2538. default:
  2539. return -EINVAL;
  2540. }
  2541. ah->ah_txpower.txp_setup = true;
  2542. return 0;
  2543. }
  2544. /* Write power table for current channel to hw */
  2545. static void
  2546. ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
  2547. {
  2548. if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
  2549. ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
  2550. else
  2551. ath5k_write_pcdac_table(ah);
  2552. }
  2553. /*
  2554. * Per-rate tx power setting
  2555. *
  2556. * This is the code that sets the desired tx power (below
  2557. * maximum) on hw for each rate (we also have TPC that sets
  2558. * power per packet). We do that by providing an index on the
  2559. * PCDAC/PDADC table we set up.
  2560. */
  2561. /*
  2562. * Set rate power table
  2563. *
  2564. * For now we only limit txpower based on maximum tx power
  2565. * supported by hw (what's inside rate_info). We need to limit
  2566. * this even more, based on regulatory domain etc.
  2567. *
  2568. * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
  2569. * and is indexed as follows:
  2570. * rates[0] - rates[7] -> OFDM rates
  2571. * rates[8] - rates[14] -> CCK rates
  2572. * rates[15] -> XR rates (they all have the same power)
  2573. */
  2574. static void
  2575. ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
  2576. struct ath5k_rate_pcal_info *rate_info,
  2577. u8 ee_mode)
  2578. {
  2579. unsigned int i;
  2580. u16 *rates;
  2581. /* max_pwr is power level we got from driver/user in 0.5dB
  2582. * units, switch to 0.25dB units so we can compare */
  2583. max_pwr *= 2;
  2584. max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
  2585. /* apply rate limits */
  2586. rates = ah->ah_txpower.txp_rates_power_table;
  2587. /* OFDM rates 6 to 24Mb/s */
  2588. for (i = 0; i < 5; i++)
  2589. rates[i] = min(max_pwr, rate_info->target_power_6to24);
  2590. /* Rest OFDM rates */
  2591. rates[5] = min(rates[0], rate_info->target_power_36);
  2592. rates[6] = min(rates[0], rate_info->target_power_48);
  2593. rates[7] = min(rates[0], rate_info->target_power_54);
  2594. /* CCK rates */
  2595. /* 1L */
  2596. rates[8] = min(rates[0], rate_info->target_power_6to24);
  2597. /* 2L */
  2598. rates[9] = min(rates[0], rate_info->target_power_36);
  2599. /* 2S */
  2600. rates[10] = min(rates[0], rate_info->target_power_36);
  2601. /* 5L */
  2602. rates[11] = min(rates[0], rate_info->target_power_48);
  2603. /* 5S */
  2604. rates[12] = min(rates[0], rate_info->target_power_48);
  2605. /* 11L */
  2606. rates[13] = min(rates[0], rate_info->target_power_54);
  2607. /* 11S */
  2608. rates[14] = min(rates[0], rate_info->target_power_54);
  2609. /* XR rates */
  2610. rates[15] = min(rates[0], rate_info->target_power_6to24);
  2611. /* CCK rates have different peak to average ratio
  2612. * so we have to tweak their power so that gainf
  2613. * correction works ok. For this we use OFDM to
  2614. * CCK delta from eeprom */
  2615. if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
  2616. (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
  2617. for (i = 8; i <= 15; i++)
  2618. rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
  2619. /* Now that we have all rates setup use table offset to
  2620. * match the power range set by user with the power indices
  2621. * on PCDAC/PDADC table */
  2622. for (i = 0; i < 16; i++) {
  2623. rates[i] += ah->ah_txpower.txp_offset;
  2624. /* Don't get out of bounds */
  2625. if (rates[i] > 63)
  2626. rates[i] = 63;
  2627. }
  2628. /* Min/max in 0.25dB units */
  2629. ah->ah_txpower.txp_min_pwr = 2 * rates[7];
  2630. ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
  2631. ah->ah_txpower.txp_ofdm = rates[7];
  2632. }
  2633. /*
  2634. * Set transmission power
  2635. */
  2636. static int
  2637. ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  2638. u8 txpower)
  2639. {
  2640. struct ath5k_rate_pcal_info rate_info;
  2641. struct ieee80211_channel *curr_channel = ah->ah_current_channel;
  2642. int ee_mode;
  2643. u8 type;
  2644. int ret;
  2645. if (txpower > AR5K_TUNE_MAX_TXPOWER) {
  2646. ATH5K_ERR(ah, "invalid tx power: %u\n", txpower);
  2647. return -EINVAL;
  2648. }
  2649. ee_mode = ath5k_eeprom_mode_from_channel(channel);
  2650. if (ee_mode < 0) {
  2651. ATH5K_ERR(ah,
  2652. "invalid channel: %d\n", channel->center_freq);
  2653. return -EINVAL;
  2654. }
  2655. /* Initialize TX power table */
  2656. switch (ah->ah_radio) {
  2657. case AR5K_RF5110:
  2658. /* TODO */
  2659. return 0;
  2660. case AR5K_RF5111:
  2661. type = AR5K_PWRTABLE_PWR_TO_PCDAC;
  2662. break;
  2663. case AR5K_RF5112:
  2664. type = AR5K_PWRTABLE_LINEAR_PCDAC;
  2665. break;
  2666. case AR5K_RF2413:
  2667. case AR5K_RF5413:
  2668. case AR5K_RF2316:
  2669. case AR5K_RF2317:
  2670. case AR5K_RF2425:
  2671. type = AR5K_PWRTABLE_PWR_TO_PDADC;
  2672. break;
  2673. default:
  2674. return -EINVAL;
  2675. }
  2676. /*
  2677. * If we don't change channel/mode skip tx powertable calculation
  2678. * and use the cached one.
  2679. */
  2680. if (!ah->ah_txpower.txp_setup ||
  2681. (channel->hw_value != curr_channel->hw_value) ||
  2682. (channel->center_freq != curr_channel->center_freq)) {
  2683. /* Reset TX power values */
  2684. memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
  2685. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  2686. /* Calculate the powertable */
  2687. ret = ath5k_setup_channel_powertable(ah, channel,
  2688. ee_mode, type);
  2689. if (ret)
  2690. return ret;
  2691. }
  2692. /* Write table on hw */
  2693. ath5k_write_channel_powertable(ah, ee_mode, type);
  2694. /* Limit max power if we have a CTL available */
  2695. ath5k_get_max_ctl_power(ah, channel);
  2696. /* FIXME: Antenna reduction stuff */
  2697. /* FIXME: Limit power on turbo modes */
  2698. /* FIXME: TPC scale reduction */
  2699. /* Get surrounding channels for per-rate power table
  2700. * calibration */
  2701. ath5k_get_rate_pcal_data(ah, channel, &rate_info);
  2702. /* Setup rate power table */
  2703. ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
  2704. /* Write rate power table on hw */
  2705. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
  2706. AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
  2707. AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
  2708. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
  2709. AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
  2710. AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
  2711. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
  2712. AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
  2713. AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
  2714. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
  2715. AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
  2716. AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
  2717. /* FIXME: TPC support */
  2718. if (ah->ah_txpower.txp_tpc) {
  2719. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
  2720. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  2721. ath5k_hw_reg_write(ah,
  2722. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
  2723. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
  2724. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
  2725. AR5K_TPC);
  2726. } else {
  2727. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
  2728. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  2729. }
  2730. return 0;
  2731. }
  2732. int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
  2733. {
  2734. ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
  2735. "changing txpower to %d\n", txpower);
  2736. return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
  2737. }
  2738. /*************\
  2739. Init function
  2740. \*************/
  2741. int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  2742. u8 mode, bool fast)
  2743. {
  2744. struct ieee80211_channel *curr_channel;
  2745. int ret, i;
  2746. u32 phy_tst1;
  2747. ret = 0;
  2748. /*
  2749. * Sanity check for fast flag
  2750. * Don't try fast channel change when changing modulation
  2751. * mode/band. We check for chip compatibility on
  2752. * ath5k_hw_reset.
  2753. */
  2754. curr_channel = ah->ah_current_channel;
  2755. if (fast && (channel->hw_value != curr_channel->hw_value))
  2756. return -EINVAL;
  2757. /*
  2758. * On fast channel change we only set the synth parameters
  2759. * while PHY is running, enable calibration and skip the rest.
  2760. */
  2761. if (fast) {
  2762. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
  2763. AR5K_PHY_RFBUS_REQ_REQUEST);
  2764. for (i = 0; i < 100; i++) {
  2765. if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
  2766. break;
  2767. udelay(5);
  2768. }
  2769. /* Failed */
  2770. if (i >= 100)
  2771. return -EIO;
  2772. /* Set channel and wait for synth */
  2773. ret = ath5k_hw_channel(ah, channel);
  2774. if (ret)
  2775. return ret;
  2776. ath5k_hw_wait_for_synth(ah, channel);
  2777. }
  2778. /*
  2779. * Set TX power
  2780. *
  2781. * Note: We need to do that before we set
  2782. * RF buffer settings on 5211/5212+ so that we
  2783. * properly set curve indices.
  2784. */
  2785. ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
  2786. ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
  2787. if (ret)
  2788. return ret;
  2789. /* Write OFDM timings on 5212*/
  2790. if (ah->ah_version == AR5K_AR5212 &&
  2791. channel->hw_value & CHANNEL_OFDM) {
  2792. ret = ath5k_hw_write_ofdm_timings(ah, channel);
  2793. if (ret)
  2794. return ret;
  2795. /* Spur info is available only from EEPROM versions
  2796. * greater than 5.3, but the EEPROM routines will use
  2797. * static values for older versions */
  2798. if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
  2799. ath5k_hw_set_spur_mitigation_filter(ah,
  2800. channel);
  2801. }
  2802. /* If we used fast channel switching
  2803. * we are done, release RF bus and
  2804. * fire up NF calibration.
  2805. *
  2806. * Note: Only NF calibration due to
  2807. * channel change, not AGC calibration
  2808. * since AGC is still running !
  2809. */
  2810. if (fast) {
  2811. /*
  2812. * Release RF Bus grant
  2813. */
  2814. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
  2815. AR5K_PHY_RFBUS_REQ_REQUEST);
  2816. /*
  2817. * Start NF calibration
  2818. */
  2819. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  2820. AR5K_PHY_AGCCTL_NF);
  2821. return ret;
  2822. }
  2823. /*
  2824. * For 5210 we do all initialization using
  2825. * initvals, so we don't have to modify
  2826. * any settings (5210 also only supports
  2827. * a/aturbo modes)
  2828. */
  2829. if (ah->ah_version != AR5K_AR5210) {
  2830. /*
  2831. * Write initial RF gain settings
  2832. * This should work for both 5111/5112
  2833. */
  2834. ret = ath5k_hw_rfgain_init(ah, channel->band);
  2835. if (ret)
  2836. return ret;
  2837. mdelay(1);
  2838. /*
  2839. * Write RF buffer
  2840. */
  2841. ret = ath5k_hw_rfregs_init(ah, channel, mode);
  2842. if (ret)
  2843. return ret;
  2844. /*Enable/disable 802.11b mode on 5111
  2845. (enable 2111 frequency converter + CCK)*/
  2846. if (ah->ah_radio == AR5K_RF5111) {
  2847. if (mode == AR5K_MODE_11B)
  2848. AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
  2849. AR5K_TXCFG_B_MODE);
  2850. else
  2851. AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
  2852. AR5K_TXCFG_B_MODE);
  2853. }
  2854. } else if (ah->ah_version == AR5K_AR5210) {
  2855. mdelay(1);
  2856. /* Disable phy and wait */
  2857. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  2858. mdelay(1);
  2859. }
  2860. /* Set channel on PHY */
  2861. ret = ath5k_hw_channel(ah, channel);
  2862. if (ret)
  2863. return ret;
  2864. /*
  2865. * Enable the PHY and wait until completion
  2866. * This includes BaseBand and Synthesizer
  2867. * activation.
  2868. */
  2869. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  2870. ath5k_hw_wait_for_synth(ah, channel);
  2871. /*
  2872. * Perform ADC test to see if baseband is ready
  2873. * Set tx hold and check adc test register
  2874. */
  2875. phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
  2876. ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
  2877. for (i = 0; i <= 20; i++) {
  2878. if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
  2879. break;
  2880. udelay(200);
  2881. }
  2882. ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
  2883. /*
  2884. * Start automatic gain control calibration
  2885. *
  2886. * During AGC calibration RX path is re-routed to
  2887. * a power detector so we don't receive anything.
  2888. *
  2889. * This method is used to calibrate some static offsets
  2890. * used together with on-the fly I/Q calibration (the
  2891. * one performed via ath5k_hw_phy_calibrate), which doesn't
  2892. * interrupt rx path.
  2893. *
  2894. * While rx path is re-routed to the power detector we also
  2895. * start a noise floor calibration to measure the
  2896. * card's noise floor (the noise we measure when we are not
  2897. * transmitting or receiving anything).
  2898. *
  2899. * If we are in a noisy environment, AGC calibration may time
  2900. * out and/or noise floor calibration might timeout.
  2901. */
  2902. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  2903. AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
  2904. /* At the same time start I/Q calibration for QAM constellation
  2905. * -no need for CCK- */
  2906. ah->ah_calibration = false;
  2907. if (!(mode == AR5K_MODE_11B)) {
  2908. ah->ah_calibration = true;
  2909. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
  2910. AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
  2911. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
  2912. AR5K_PHY_IQ_RUN);
  2913. }
  2914. /* Wait for gain calibration to finish (we check for I/Q calibration
  2915. * during ath5k_phy_calibrate) */
  2916. if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  2917. AR5K_PHY_AGCCTL_CAL, 0, false)) {
  2918. ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n",
  2919. channel->center_freq);
  2920. }
  2921. /* Restore antenna mode */
  2922. ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
  2923. return ret;
  2924. }