board-bockw.c 6.7 KB

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  1. /*
  2. * Bock-W board support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/mfd/tmio.h>
  21. #include <linux/mmc/host.h>
  22. #include <linux/mtd/partitions.h>
  23. #include <linux/pinctrl/machine.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/regulator/fixed.h>
  26. #include <linux/regulator/machine.h>
  27. #include <linux/smsc911x.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/spi/flash.h>
  30. #include <mach/common.h>
  31. #include <mach/irqs.h>
  32. #include <mach/r8a7778.h>
  33. #include <asm/mach/arch.h>
  34. /*
  35. * CN9(Upper side) SCIF/RCAN selection
  36. *
  37. * 1,4 3,6
  38. * SW40 SCIF RCAN
  39. * SW41 SCIF RCAN
  40. */
  41. /*
  42. * MMC (CN26) pin
  43. *
  44. * SW6 (D2) 3 pin
  45. * SW7 (D5) ON
  46. * SW8 (D3) 3 pin
  47. * SW10 (D4) 1 pin
  48. * SW12 (CLK) 1 pin
  49. * SW13 (D6) 3 pin
  50. * SW14 (CMD) ON
  51. * SW15 (D6) 1 pin
  52. * SW16 (D0) ON
  53. * SW17 (D1) ON
  54. * SW18 (D7) 3 pin
  55. * SW19 (MMC) 1 pin
  56. */
  57. /* Dummy supplies, where voltage doesn't matter */
  58. static struct regulator_consumer_supply dummy_supplies[] = {
  59. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  60. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  61. };
  62. static struct smsc911x_platform_config smsc911x_data = {
  63. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  64. .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
  65. .flags = SMSC911X_USE_32BIT,
  66. .phy_interface = PHY_INTERFACE_MODE_MII,
  67. };
  68. static struct resource smsc911x_resources[] = {
  69. DEFINE_RES_MEM(0x18300000, 0x1000),
  70. DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  71. };
  72. /* USB */
  73. static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
  74. /* SDHI */
  75. static struct sh_mobile_sdhi_info sdhi0_info = {
  76. .tmio_caps = MMC_CAP_SD_HIGHSPEED,
  77. .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  78. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  79. };
  80. static struct sh_eth_plat_data ether_platform_data __initdata = {
  81. .phy = 0x01,
  82. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  83. .phy_interface = PHY_INTERFACE_MODE_RMII,
  84. /*
  85. * Although the LINK signal is available on the board, it's connected to
  86. * the link/activity LED output of the PHY, thus the link disappears and
  87. * reappears after each packet. We'd be better off ignoring such signal
  88. * and getting the link state from the PHY indirectly.
  89. */
  90. .no_ether_link = 1,
  91. };
  92. /* I2C */
  93. static struct i2c_board_info i2c0_devices[] = {
  94. {
  95. I2C_BOARD_INFO("rx8581", 0x51),
  96. },
  97. };
  98. /* HSPI*/
  99. static struct mtd_partition m25p80_spi_flash_partitions[] = {
  100. {
  101. .name = "data(spi)",
  102. .size = 0x0100000,
  103. .offset = 0,
  104. },
  105. };
  106. static struct flash_platform_data spi_flash_data = {
  107. .name = "m25p80",
  108. .type = "s25fl008k",
  109. .parts = m25p80_spi_flash_partitions,
  110. .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions),
  111. };
  112. static struct spi_board_info spi_board_info[] __initdata = {
  113. {
  114. .modalias = "m25p80",
  115. .max_speed_hz = 104000000,
  116. .chip_select = 0,
  117. .bus_num = 0,
  118. .mode = SPI_MODE_0,
  119. .platform_data = &spi_flash_data,
  120. },
  121. };
  122. /* MMC */
  123. static struct sh_mmcif_plat_data sh_mmcif_plat = {
  124. .sup_pclk = 0,
  125. .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  126. .caps = MMC_CAP_4_BIT_DATA |
  127. MMC_CAP_8_BIT_DATA |
  128. MMC_CAP_NEEDS_POLL,
  129. };
  130. static const struct pinctrl_map bockw_pinctrl_map[] = {
  131. /* Ether */
  132. PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
  133. "ether_rmii", "ether"),
  134. /* HSPI0 */
  135. PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
  136. "hspi0_a", "hspi0"),
  137. /* MMC */
  138. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  139. "mmc_data8", "mmc"),
  140. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  141. "mmc_ctrl", "mmc"),
  142. /* SCIF0 */
  143. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  144. "scif0_data_a", "scif0"),
  145. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  146. "scif0_ctrl", "scif0"),
  147. /* USB */
  148. PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
  149. "usb0", "usb0"),
  150. PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
  151. "usb1", "usb1"),
  152. /* SDHI0 */
  153. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  154. "sdhi0_data4", "sdhi0"),
  155. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  156. "sdhi0_ctrl", "sdhi0"),
  157. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  158. "sdhi0_cd", "sdhi0"),
  159. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  160. "sdhi0_wp", "sdhi0"),
  161. };
  162. #define FPGA 0x18200000
  163. #define IRQ0MR 0x30
  164. #define PFC 0xfffc0000
  165. #define PUPR4 0x110
  166. static void __init bockw_init(void)
  167. {
  168. void __iomem *base;
  169. r8a7778_clock_init();
  170. r8a7778_init_irq_extpin(1);
  171. r8a7778_add_standard_devices();
  172. r8a7778_add_usb_phy_device(&usb_phy_platform_data);
  173. r8a7778_add_ether_device(&ether_platform_data);
  174. r8a7778_add_i2c_device(0);
  175. r8a7778_add_hspi_device(0);
  176. r8a7778_add_mmc_device(&sh_mmcif_plat);
  177. i2c_register_board_info(0, i2c0_devices,
  178. ARRAY_SIZE(i2c0_devices));
  179. spi_register_board_info(spi_board_info,
  180. ARRAY_SIZE(spi_board_info));
  181. pinctrl_register_mappings(bockw_pinctrl_map,
  182. ARRAY_SIZE(bockw_pinctrl_map));
  183. r8a7778_pinmux_init();
  184. /* for SMSC */
  185. base = ioremap_nocache(FPGA, SZ_1M);
  186. if (base) {
  187. /*
  188. * CAUTION
  189. *
  190. * IRQ0/1 is cascaded interrupt from FPGA.
  191. * it should be cared in the future
  192. * Now, it is assuming IRQ0 was used only from SMSC.
  193. */
  194. u16 val = ioread16(base + IRQ0MR);
  195. val &= ~(1 << 4); /* enable SMSC911x */
  196. iowrite16(val, base + IRQ0MR);
  197. iounmap(base);
  198. regulator_register_fixed(0, dummy_supplies,
  199. ARRAY_SIZE(dummy_supplies));
  200. platform_device_register_resndata(
  201. &platform_bus, "smsc911x", -1,
  202. smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
  203. &smsc911x_data, sizeof(smsc911x_data));
  204. }
  205. /* for SDHI */
  206. base = ioremap_nocache(PFC, 0x200);
  207. if (base) {
  208. /*
  209. * FIXME
  210. *
  211. * SDHI CD/WP pin needs pull-up
  212. */
  213. iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
  214. iounmap(base);
  215. r8a7778_sdhi_init(0, &sdhi0_info);
  216. }
  217. }
  218. static const char *bockw_boards_compat_dt[] __initdata = {
  219. "renesas,bockw",
  220. NULL,
  221. };
  222. DT_MACHINE_START(BOCKW_DT, "bockw")
  223. .init_early = r8a7778_init_delay,
  224. .init_irq = r8a7778_init_irq_dt,
  225. .init_machine = bockw_init,
  226. .init_time = shmobile_timer_init,
  227. .dt_compat = bockw_boards_compat_dt,
  228. .init_late = r8a7778_init_late,
  229. MACHINE_END