dev.c 5.1 KB

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  1. /*
  2. * Tegra host1x driver
  3. *
  4. * Copyright (c) 2010-2013, NVIDIA Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/list.h>
  20. #include <linux/slab.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/io.h>
  25. #define CREATE_TRACE_POINTS
  26. #include <trace/events/host1x.h>
  27. #include "bus.h"
  28. #include "dev.h"
  29. #include "intr.h"
  30. #include "channel.h"
  31. #include "debug.h"
  32. #include "hw/host1x01.h"
  33. #include "hw/host1x02.h"
  34. void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  35. {
  36. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  37. writel(v, sync_regs + r);
  38. }
  39. u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  40. {
  41. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  42. return readl(sync_regs + r);
  43. }
  44. void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  45. {
  46. writel(v, ch->regs + r);
  47. }
  48. u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  49. {
  50. return readl(ch->regs + r);
  51. }
  52. static const struct host1x_info host1x01_info = {
  53. .nb_channels = 8,
  54. .nb_pts = 32,
  55. .nb_mlocks = 16,
  56. .nb_bases = 8,
  57. .init = host1x01_init,
  58. .sync_offset = 0x3000,
  59. };
  60. static const struct host1x_info host1x02_info = {
  61. .nb_channels = 9,
  62. .nb_pts = 32,
  63. .nb_mlocks = 16,
  64. .nb_bases = 12,
  65. .init = host1x02_init,
  66. .sync_offset = 0x3000,
  67. };
  68. static struct of_device_id host1x_of_match[] = {
  69. { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
  70. { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
  71. { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
  72. { },
  73. };
  74. MODULE_DEVICE_TABLE(of, host1x_of_match);
  75. static int host1x_probe(struct platform_device *pdev)
  76. {
  77. const struct of_device_id *id;
  78. struct host1x *host;
  79. struct resource *regs;
  80. int syncpt_irq;
  81. int err;
  82. id = of_match_device(host1x_of_match, &pdev->dev);
  83. if (!id)
  84. return -EINVAL;
  85. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. if (!regs) {
  87. dev_err(&pdev->dev, "failed to get registers\n");
  88. return -ENXIO;
  89. }
  90. syncpt_irq = platform_get_irq(pdev, 0);
  91. if (syncpt_irq < 0) {
  92. dev_err(&pdev->dev, "failed to get IRQ\n");
  93. return -ENXIO;
  94. }
  95. host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
  96. if (!host)
  97. return -ENOMEM;
  98. mutex_init(&host->devices_lock);
  99. INIT_LIST_HEAD(&host->devices);
  100. INIT_LIST_HEAD(&host->list);
  101. host->dev = &pdev->dev;
  102. host->info = id->data;
  103. /* set common host1x device data */
  104. platform_set_drvdata(pdev, host);
  105. host->regs = devm_ioremap_resource(&pdev->dev, regs);
  106. if (IS_ERR(host->regs))
  107. return PTR_ERR(host->regs);
  108. if (host->info->init) {
  109. err = host->info->init(host);
  110. if (err)
  111. return err;
  112. }
  113. host->clk = devm_clk_get(&pdev->dev, NULL);
  114. if (IS_ERR(host->clk)) {
  115. dev_err(&pdev->dev, "failed to get clock\n");
  116. err = PTR_ERR(host->clk);
  117. return err;
  118. }
  119. err = host1x_channel_list_init(host);
  120. if (err) {
  121. dev_err(&pdev->dev, "failed to initialize channel list\n");
  122. return err;
  123. }
  124. err = clk_prepare_enable(host->clk);
  125. if (err < 0) {
  126. dev_err(&pdev->dev, "failed to enable clock\n");
  127. return err;
  128. }
  129. err = host1x_syncpt_init(host);
  130. if (err) {
  131. dev_err(&pdev->dev, "failed to initialize syncpts\n");
  132. goto fail_unprepare_disable;
  133. }
  134. err = host1x_intr_init(host, syncpt_irq);
  135. if (err) {
  136. dev_err(&pdev->dev, "failed to initialize interrupts\n");
  137. goto fail_deinit_syncpt;
  138. }
  139. host1x_debug_init(host);
  140. err = host1x_register(host);
  141. if (err < 0)
  142. goto fail_deinit_intr;
  143. return 0;
  144. fail_deinit_intr:
  145. host1x_intr_deinit(host);
  146. fail_deinit_syncpt:
  147. host1x_syncpt_deinit(host);
  148. fail_unprepare_disable:
  149. clk_disable_unprepare(host->clk);
  150. return err;
  151. }
  152. static int host1x_remove(struct platform_device *pdev)
  153. {
  154. struct host1x *host = platform_get_drvdata(pdev);
  155. host1x_unregister(host);
  156. host1x_intr_deinit(host);
  157. host1x_syncpt_deinit(host);
  158. clk_disable_unprepare(host->clk);
  159. return 0;
  160. }
  161. static struct platform_driver tegra_host1x_driver = {
  162. .driver = {
  163. .name = "tegra-host1x",
  164. .of_match_table = host1x_of_match,
  165. },
  166. .probe = host1x_probe,
  167. .remove = host1x_remove,
  168. };
  169. static int __init tegra_host1x_init(void)
  170. {
  171. int err;
  172. err = host1x_bus_init();
  173. if (err < 0)
  174. return err;
  175. err = platform_driver_register(&tegra_host1x_driver);
  176. if (err < 0) {
  177. host1x_bus_exit();
  178. return err;
  179. }
  180. return 0;
  181. }
  182. module_init(tegra_host1x_init);
  183. static void __exit tegra_host1x_exit(void)
  184. {
  185. platform_driver_unregister(&tegra_host1x_driver);
  186. host1x_bus_exit();
  187. }
  188. module_exit(tegra_host1x_exit);
  189. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  190. MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
  191. MODULE_DESCRIPTION("Host1x driver for Tegra products");
  192. MODULE_LICENSE("GPL");