mdp4_crtc.c 20 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "mdp4_kms.h"
  18. #include <drm/drm_mode.h>
  19. #include "drm_crtc.h"
  20. #include "drm_crtc_helper.h"
  21. #include "drm_flip_work.h"
  22. struct mdp4_crtc {
  23. struct drm_crtc base;
  24. char name[8];
  25. struct drm_plane *plane;
  26. struct drm_plane *planes[8];
  27. int id;
  28. int ovlp;
  29. enum mdp4_dma dma;
  30. bool enabled;
  31. /* which mixer/encoder we route output to: */
  32. int mixer;
  33. struct {
  34. spinlock_t lock;
  35. bool stale;
  36. uint32_t width, height;
  37. /* next cursor to scan-out: */
  38. uint32_t next_iova;
  39. struct drm_gem_object *next_bo;
  40. /* current cursor being scanned out: */
  41. struct drm_gem_object *scanout_bo;
  42. } cursor;
  43. /* if there is a pending flip, these will be non-null: */
  44. struct drm_pending_vblank_event *event;
  45. struct msm_fence_cb pageflip_cb;
  46. #define PENDING_CURSOR 0x1
  47. #define PENDING_FLIP 0x2
  48. atomic_t pending;
  49. /* the fb that we currently hold a scanout ref to: */
  50. struct drm_framebuffer *fb;
  51. /* for unref'ing framebuffers after scanout completes: */
  52. struct drm_flip_work unref_fb_work;
  53. /* for unref'ing cursor bo's after scanout completes: */
  54. struct drm_flip_work unref_cursor_work;
  55. struct mdp4_irq vblank;
  56. struct mdp4_irq err;
  57. };
  58. #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
  59. static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
  60. {
  61. struct msm_drm_private *priv = crtc->dev->dev_private;
  62. return to_mdp4_kms(priv->kms);
  63. }
  64. static void update_fb(struct drm_crtc *crtc, bool async,
  65. struct drm_framebuffer *new_fb)
  66. {
  67. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  68. struct drm_framebuffer *old_fb = mdp4_crtc->fb;
  69. if (old_fb)
  70. drm_flip_work_queue(&mdp4_crtc->unref_fb_work, old_fb);
  71. /* grab reference to incoming scanout fb: */
  72. drm_framebuffer_reference(new_fb);
  73. mdp4_crtc->base.fb = new_fb;
  74. mdp4_crtc->fb = new_fb;
  75. if (!async) {
  76. /* enable vblank to pick up the old_fb */
  77. mdp4_irq_register(get_kms(crtc), &mdp4_crtc->vblank);
  78. }
  79. }
  80. /* if file!=NULL, this is preclose potential cancel-flip path */
  81. static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
  82. {
  83. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  84. struct drm_device *dev = crtc->dev;
  85. struct drm_pending_vblank_event *event;
  86. unsigned long flags;
  87. spin_lock_irqsave(&dev->event_lock, flags);
  88. event = mdp4_crtc->event;
  89. if (event) {
  90. /* if regular vblank case (!file) or if cancel-flip from
  91. * preclose on file that requested flip, then send the
  92. * event:
  93. */
  94. if (!file || (event->base.file_priv == file)) {
  95. mdp4_crtc->event = NULL;
  96. drm_send_vblank_event(dev, mdp4_crtc->id, event);
  97. }
  98. }
  99. spin_unlock_irqrestore(&dev->event_lock, flags);
  100. }
  101. static void crtc_flush(struct drm_crtc *crtc)
  102. {
  103. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  104. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  105. uint32_t i, flush = 0;
  106. for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
  107. struct drm_plane *plane = mdp4_crtc->planes[i];
  108. if (plane) {
  109. enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
  110. flush |= pipe2flush(pipe_id);
  111. }
  112. }
  113. flush |= ovlp2flush(mdp4_crtc->ovlp);
  114. DBG("%s: flush=%08x", mdp4_crtc->name, flush);
  115. mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
  116. }
  117. static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  118. {
  119. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  120. atomic_or(pending, &mdp4_crtc->pending);
  121. mdp4_irq_register(get_kms(crtc), &mdp4_crtc->vblank);
  122. }
  123. static void pageflip_cb(struct msm_fence_cb *cb)
  124. {
  125. struct mdp4_crtc *mdp4_crtc =
  126. container_of(cb, struct mdp4_crtc, pageflip_cb);
  127. struct drm_crtc *crtc = &mdp4_crtc->base;
  128. struct drm_framebuffer *fb = crtc->fb;
  129. if (!fb)
  130. return;
  131. mdp4_plane_set_scanout(mdp4_crtc->plane, fb);
  132. crtc_flush(crtc);
  133. /* enable vblank to complete flip: */
  134. request_pending(crtc, PENDING_FLIP);
  135. }
  136. static void unref_fb_worker(struct drm_flip_work *work, void *val)
  137. {
  138. struct mdp4_crtc *mdp4_crtc =
  139. container_of(work, struct mdp4_crtc, unref_fb_work);
  140. struct drm_device *dev = mdp4_crtc->base.dev;
  141. mutex_lock(&dev->mode_config.mutex);
  142. drm_framebuffer_unreference(val);
  143. mutex_unlock(&dev->mode_config.mutex);
  144. }
  145. static void unref_cursor_worker(struct drm_flip_work *work, void *val)
  146. {
  147. struct mdp4_crtc *mdp4_crtc =
  148. container_of(work, struct mdp4_crtc, unref_cursor_work);
  149. struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
  150. msm_gem_put_iova(val, mdp4_kms->id);
  151. drm_gem_object_unreference_unlocked(val);
  152. }
  153. static void mdp4_crtc_destroy(struct drm_crtc *crtc)
  154. {
  155. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  156. mdp4_crtc->plane->funcs->destroy(mdp4_crtc->plane);
  157. drm_crtc_cleanup(crtc);
  158. drm_flip_work_cleanup(&mdp4_crtc->unref_fb_work);
  159. drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
  160. kfree(mdp4_crtc);
  161. }
  162. static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
  163. {
  164. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  165. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  166. bool enabled = (mode == DRM_MODE_DPMS_ON);
  167. DBG("%s: mode=%d", mdp4_crtc->name, mode);
  168. if (enabled != mdp4_crtc->enabled) {
  169. if (enabled) {
  170. mdp4_enable(mdp4_kms);
  171. mdp4_irq_register(mdp4_kms, &mdp4_crtc->err);
  172. } else {
  173. mdp4_irq_unregister(mdp4_kms, &mdp4_crtc->err);
  174. mdp4_disable(mdp4_kms);
  175. }
  176. mdp4_crtc->enabled = enabled;
  177. }
  178. }
  179. static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
  180. const struct drm_display_mode *mode,
  181. struct drm_display_mode *adjusted_mode)
  182. {
  183. return true;
  184. }
  185. static void blend_setup(struct drm_crtc *crtc)
  186. {
  187. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  188. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  189. int i, ovlp = mdp4_crtc->ovlp;
  190. uint32_t mixer_cfg = 0;
  191. static const enum mdp4_mixer_stage_id stages[] = {
  192. STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
  193. };
  194. /* statically (for now) map planes to mixer stage (z-order): */
  195. static const int idxs[] = {
  196. [VG1] = 1,
  197. [VG2] = 2,
  198. [RGB1] = 0,
  199. [RGB2] = 0,
  200. [RGB3] = 0,
  201. [VG3] = 3,
  202. [VG4] = 4,
  203. };
  204. bool alpha[4]= { false, false, false, false };
  205. mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
  206. mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
  207. mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
  208. mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
  209. /* TODO single register for all CRTCs, so this won't work properly
  210. * when multiple CRTCs are active..
  211. */
  212. for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
  213. struct drm_plane *plane = mdp4_crtc->planes[i];
  214. if (plane) {
  215. enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
  216. int idx = idxs[pipe_id];
  217. if (idx > 0) {
  218. const struct mdp4_format *format =
  219. to_mdp4_format(msm_framebuffer_format(plane->fb));
  220. alpha[idx-1] = format->alpha_enable;
  221. }
  222. mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, stages[idx]);
  223. }
  224. }
  225. /* this shouldn't happen.. and seems to cause underflow: */
  226. WARN_ON(!mixer_cfg);
  227. for (i = 0; i < 4; i++) {
  228. uint32_t op;
  229. if (alpha[i]) {
  230. op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
  231. MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
  232. MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
  233. } else {
  234. op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
  235. MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
  236. }
  237. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
  238. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
  239. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
  240. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
  241. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
  242. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
  243. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
  244. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
  245. }
  246. mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
  247. }
  248. static int mdp4_crtc_mode_set(struct drm_crtc *crtc,
  249. struct drm_display_mode *mode,
  250. struct drm_display_mode *adjusted_mode,
  251. int x, int y,
  252. struct drm_framebuffer *old_fb)
  253. {
  254. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  255. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  256. enum mdp4_dma dma = mdp4_crtc->dma;
  257. int ret, ovlp = mdp4_crtc->ovlp;
  258. mode = adjusted_mode;
  259. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  260. mdp4_crtc->name, mode->base.id, mode->name,
  261. mode->vrefresh, mode->clock,
  262. mode->hdisplay, mode->hsync_start,
  263. mode->hsync_end, mode->htotal,
  264. mode->vdisplay, mode->vsync_start,
  265. mode->vsync_end, mode->vtotal,
  266. mode->type, mode->flags);
  267. mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
  268. MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
  269. MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
  270. /* take data from pipe: */
  271. mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
  272. mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma),
  273. crtc->fb->pitches[0]);
  274. mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
  275. MDP4_DMA_DST_SIZE_WIDTH(0) |
  276. MDP4_DMA_DST_SIZE_HEIGHT(0));
  277. mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
  278. mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
  279. MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
  280. MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
  281. mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp),
  282. crtc->fb->pitches[0]);
  283. mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
  284. update_fb(crtc, false, crtc->fb);
  285. ret = mdp4_plane_mode_set(mdp4_crtc->plane, crtc, crtc->fb,
  286. 0, 0, mode->hdisplay, mode->vdisplay,
  287. x << 16, y << 16,
  288. mode->hdisplay << 16, mode->vdisplay << 16);
  289. if (ret) {
  290. dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n",
  291. mdp4_crtc->name, ret);
  292. return ret;
  293. }
  294. if (dma == DMA_E) {
  295. mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
  296. mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
  297. mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
  298. }
  299. return 0;
  300. }
  301. static void mdp4_crtc_prepare(struct drm_crtc *crtc)
  302. {
  303. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  304. DBG("%s", mdp4_crtc->name);
  305. /* make sure we hold a ref to mdp clks while setting up mode: */
  306. mdp4_enable(get_kms(crtc));
  307. mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  308. }
  309. static void mdp4_crtc_commit(struct drm_crtc *crtc)
  310. {
  311. mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  312. crtc_flush(crtc);
  313. /* drop the ref to mdp clk's that we got in prepare: */
  314. mdp4_disable(get_kms(crtc));
  315. }
  316. static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  317. struct drm_framebuffer *old_fb)
  318. {
  319. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  320. struct drm_plane *plane = mdp4_crtc->plane;
  321. struct drm_display_mode *mode = &crtc->mode;
  322. update_fb(crtc, false, crtc->fb);
  323. return mdp4_plane_mode_set(plane, crtc, crtc->fb,
  324. 0, 0, mode->hdisplay, mode->vdisplay,
  325. x << 16, y << 16,
  326. mode->hdisplay << 16, mode->vdisplay << 16);
  327. }
  328. static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
  329. {
  330. }
  331. static int mdp4_crtc_page_flip(struct drm_crtc *crtc,
  332. struct drm_framebuffer *new_fb,
  333. struct drm_pending_vblank_event *event,
  334. uint32_t page_flip_flags)
  335. {
  336. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  337. struct drm_device *dev = crtc->dev;
  338. struct drm_gem_object *obj;
  339. unsigned long flags;
  340. if (mdp4_crtc->event) {
  341. dev_err(dev->dev, "already pending flip!\n");
  342. return -EBUSY;
  343. }
  344. obj = msm_framebuffer_bo(new_fb, 0);
  345. spin_lock_irqsave(&dev->event_lock, flags);
  346. mdp4_crtc->event = event;
  347. spin_unlock_irqrestore(&dev->event_lock, flags);
  348. update_fb(crtc, true, new_fb);
  349. return msm_gem_queue_inactive_cb(obj, &mdp4_crtc->pageflip_cb);
  350. }
  351. static int mdp4_crtc_set_property(struct drm_crtc *crtc,
  352. struct drm_property *property, uint64_t val)
  353. {
  354. // XXX
  355. return -EINVAL;
  356. }
  357. #define CURSOR_WIDTH 64
  358. #define CURSOR_HEIGHT 64
  359. /* called from IRQ to update cursor related registers (if needed). The
  360. * cursor registers, other than x/y position, appear not to be double
  361. * buffered, and changing them other than from vblank seems to trigger
  362. * underflow.
  363. */
  364. static void update_cursor(struct drm_crtc *crtc)
  365. {
  366. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  367. enum mdp4_dma dma = mdp4_crtc->dma;
  368. unsigned long flags;
  369. spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
  370. if (mdp4_crtc->cursor.stale) {
  371. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  372. struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
  373. struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
  374. uint32_t iova = mdp4_crtc->cursor.next_iova;
  375. if (next_bo) {
  376. /* take a obj ref + iova ref when we start scanning out: */
  377. drm_gem_object_reference(next_bo);
  378. msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
  379. /* enable cursor: */
  380. mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
  381. MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
  382. MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
  383. mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
  384. mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
  385. MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
  386. MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
  387. } else {
  388. /* disable cursor: */
  389. mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), 0);
  390. mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
  391. MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB));
  392. }
  393. /* and drop the iova ref + obj rev when done scanning out: */
  394. if (prev_bo)
  395. drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
  396. mdp4_crtc->cursor.scanout_bo = next_bo;
  397. mdp4_crtc->cursor.stale = false;
  398. }
  399. spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
  400. }
  401. static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
  402. struct drm_file *file_priv, uint32_t handle,
  403. uint32_t width, uint32_t height)
  404. {
  405. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  406. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  407. struct drm_device *dev = crtc->dev;
  408. struct drm_gem_object *cursor_bo, *old_bo;
  409. unsigned long flags;
  410. uint32_t iova;
  411. int ret;
  412. if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
  413. dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
  414. return -EINVAL;
  415. }
  416. if (handle) {
  417. cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
  418. if (!cursor_bo)
  419. return -ENOENT;
  420. } else {
  421. cursor_bo = NULL;
  422. }
  423. if (cursor_bo) {
  424. ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
  425. if (ret)
  426. goto fail;
  427. } else {
  428. iova = 0;
  429. }
  430. spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
  431. old_bo = mdp4_crtc->cursor.next_bo;
  432. mdp4_crtc->cursor.next_bo = cursor_bo;
  433. mdp4_crtc->cursor.next_iova = iova;
  434. mdp4_crtc->cursor.width = width;
  435. mdp4_crtc->cursor.height = height;
  436. mdp4_crtc->cursor.stale = true;
  437. spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
  438. if (old_bo) {
  439. /* drop our previous reference: */
  440. msm_gem_put_iova(old_bo, mdp4_kms->id);
  441. drm_gem_object_unreference_unlocked(old_bo);
  442. }
  443. request_pending(crtc, PENDING_CURSOR);
  444. return 0;
  445. fail:
  446. drm_gem_object_unreference_unlocked(cursor_bo);
  447. return ret;
  448. }
  449. static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  450. {
  451. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  452. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  453. enum mdp4_dma dma = mdp4_crtc->dma;
  454. mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
  455. MDP4_DMA_CURSOR_POS_X(x) |
  456. MDP4_DMA_CURSOR_POS_Y(y));
  457. return 0;
  458. }
  459. static const struct drm_crtc_funcs mdp4_crtc_funcs = {
  460. .set_config = drm_crtc_helper_set_config,
  461. .destroy = mdp4_crtc_destroy,
  462. .page_flip = mdp4_crtc_page_flip,
  463. .set_property = mdp4_crtc_set_property,
  464. .cursor_set = mdp4_crtc_cursor_set,
  465. .cursor_move = mdp4_crtc_cursor_move,
  466. };
  467. static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
  468. .dpms = mdp4_crtc_dpms,
  469. .mode_fixup = mdp4_crtc_mode_fixup,
  470. .mode_set = mdp4_crtc_mode_set,
  471. .prepare = mdp4_crtc_prepare,
  472. .commit = mdp4_crtc_commit,
  473. .mode_set_base = mdp4_crtc_mode_set_base,
  474. .load_lut = mdp4_crtc_load_lut,
  475. };
  476. static void mdp4_crtc_vblank_irq(struct mdp4_irq *irq, uint32_t irqstatus)
  477. {
  478. struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
  479. struct drm_crtc *crtc = &mdp4_crtc->base;
  480. struct msm_drm_private *priv = crtc->dev->dev_private;
  481. unsigned pending;
  482. mdp4_irq_unregister(get_kms(crtc), &mdp4_crtc->vblank);
  483. pending = atomic_xchg(&mdp4_crtc->pending, 0);
  484. if (pending & PENDING_FLIP) {
  485. complete_flip(crtc, NULL);
  486. drm_flip_work_commit(&mdp4_crtc->unref_fb_work, priv->wq);
  487. }
  488. if (pending & PENDING_CURSOR) {
  489. update_cursor(crtc);
  490. drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
  491. }
  492. }
  493. static void mdp4_crtc_err_irq(struct mdp4_irq *irq, uint32_t irqstatus)
  494. {
  495. struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
  496. struct drm_crtc *crtc = &mdp4_crtc->base;
  497. DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
  498. crtc_flush(crtc);
  499. }
  500. uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
  501. {
  502. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  503. return mdp4_crtc->vblank.irqmask;
  504. }
  505. void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
  506. {
  507. DBG("cancel: %p", file);
  508. complete_flip(crtc, file);
  509. }
  510. /* set dma config, ie. the format the encoder wants. */
  511. void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
  512. {
  513. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  514. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  515. mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
  516. }
  517. /* set interface for routing crtc->encoder: */
  518. void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf)
  519. {
  520. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  521. struct mdp4_kms *mdp4_kms = get_kms(crtc);
  522. uint32_t intf_sel;
  523. intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
  524. switch (mdp4_crtc->dma) {
  525. case DMA_P:
  526. intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
  527. intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
  528. break;
  529. case DMA_S:
  530. intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
  531. intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
  532. break;
  533. case DMA_E:
  534. intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
  535. intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
  536. break;
  537. }
  538. if (intf == INTF_DSI_VIDEO) {
  539. intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
  540. intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
  541. mdp4_crtc->mixer = 0;
  542. } else if (intf == INTF_DSI_CMD) {
  543. intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
  544. intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
  545. mdp4_crtc->mixer = 0;
  546. } else if (intf == INTF_LCDC_DTV){
  547. mdp4_crtc->mixer = 1;
  548. }
  549. blend_setup(crtc);
  550. DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
  551. mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
  552. }
  553. static void set_attach(struct drm_crtc *crtc, enum mdp4_pipe pipe_id,
  554. struct drm_plane *plane)
  555. {
  556. struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  557. BUG_ON(pipe_id >= ARRAY_SIZE(mdp4_crtc->planes));
  558. if (mdp4_crtc->planes[pipe_id] == plane)
  559. return;
  560. mdp4_crtc->planes[pipe_id] = plane;
  561. blend_setup(crtc);
  562. if (mdp4_crtc->enabled && (plane != mdp4_crtc->plane))
  563. crtc_flush(crtc);
  564. }
  565. void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane)
  566. {
  567. set_attach(crtc, mdp4_plane_pipe(plane), plane);
  568. }
  569. void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane)
  570. {
  571. set_attach(crtc, mdp4_plane_pipe(plane), NULL);
  572. }
  573. static const char *dma_names[] = {
  574. "DMA_P", "DMA_S", "DMA_E",
  575. };
  576. /* initialize crtc */
  577. struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
  578. struct drm_plane *plane, int id, int ovlp_id,
  579. enum mdp4_dma dma_id)
  580. {
  581. struct drm_crtc *crtc = NULL;
  582. struct mdp4_crtc *mdp4_crtc;
  583. int ret;
  584. mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
  585. if (!mdp4_crtc) {
  586. ret = -ENOMEM;
  587. goto fail;
  588. }
  589. crtc = &mdp4_crtc->base;
  590. mdp4_crtc->plane = plane;
  591. mdp4_crtc->ovlp = ovlp_id;
  592. mdp4_crtc->dma = dma_id;
  593. mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
  594. mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
  595. mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
  596. mdp4_crtc->err.irq = mdp4_crtc_err_irq;
  597. snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
  598. dma_names[dma_id], ovlp_id);
  599. spin_lock_init(&mdp4_crtc->cursor.lock);
  600. ret = drm_flip_work_init(&mdp4_crtc->unref_fb_work, 16,
  601. "unref fb", unref_fb_worker);
  602. if (ret)
  603. goto fail;
  604. ret = drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 64,
  605. "unref cursor", unref_cursor_worker);
  606. INIT_FENCE_CB(&mdp4_crtc->pageflip_cb, pageflip_cb);
  607. drm_crtc_init(dev, crtc, &mdp4_crtc_funcs);
  608. drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
  609. mdp4_plane_install_properties(mdp4_crtc->plane, &crtc->base);
  610. return crtc;
  611. fail:
  612. if (crtc)
  613. mdp4_crtc_destroy(crtc);
  614. return ERR_PTR(ret);
  615. }