intel_lvds.c 32 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. */
  29. #include <acpi/button.h>
  30. #include <linux/dmi.h>
  31. #include <linux/i2c.h>
  32. #include <linux/slab.h>
  33. #include <drm/drmP.h>
  34. #include <drm/drm_crtc.h>
  35. #include <drm/drm_edid.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39. #include <linux/acpi.h>
  40. /* Private structure for the integrated LVDS support */
  41. struct intel_lvds_connector {
  42. struct intel_connector base;
  43. struct notifier_block lid_notifier;
  44. };
  45. struct intel_lvds_encoder {
  46. struct intel_encoder base;
  47. bool is_dual_link;
  48. u32 reg;
  49. struct intel_lvds_connector *attached_connector;
  50. };
  51. static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  52. {
  53. return container_of(encoder, struct intel_lvds_encoder, base.base);
  54. }
  55. static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  56. {
  57. return container_of(connector, struct intel_lvds_connector, base.base);
  58. }
  59. static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  60. enum pipe *pipe)
  61. {
  62. struct drm_device *dev = encoder->base.dev;
  63. struct drm_i915_private *dev_priv = dev->dev_private;
  64. struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  65. u32 tmp;
  66. tmp = I915_READ(lvds_encoder->reg);
  67. if (!(tmp & LVDS_PORT_EN))
  68. return false;
  69. if (HAS_PCH_CPT(dev))
  70. *pipe = PORT_TO_PIPE_CPT(tmp);
  71. else
  72. *pipe = PORT_TO_PIPE(tmp);
  73. return true;
  74. }
  75. static void intel_lvds_get_config(struct intel_encoder *encoder,
  76. struct intel_crtc_config *pipe_config)
  77. {
  78. struct drm_device *dev = encoder->base.dev;
  79. struct drm_i915_private *dev_priv = dev->dev_private;
  80. u32 lvds_reg, tmp, flags = 0;
  81. int dotclock;
  82. if (HAS_PCH_SPLIT(dev))
  83. lvds_reg = PCH_LVDS;
  84. else
  85. lvds_reg = LVDS;
  86. tmp = I915_READ(lvds_reg);
  87. if (tmp & LVDS_HSYNC_POLARITY)
  88. flags |= DRM_MODE_FLAG_NHSYNC;
  89. else
  90. flags |= DRM_MODE_FLAG_PHSYNC;
  91. if (tmp & LVDS_VSYNC_POLARITY)
  92. flags |= DRM_MODE_FLAG_NVSYNC;
  93. else
  94. flags |= DRM_MODE_FLAG_PVSYNC;
  95. pipe_config->adjusted_mode.flags |= flags;
  96. /* gen2/3 store dither state in pfit control, needs to match */
  97. if (INTEL_INFO(dev)->gen < 4) {
  98. tmp = I915_READ(PFIT_CONTROL);
  99. pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
  100. }
  101. dotclock = pipe_config->port_clock;
  102. if (HAS_PCH_SPLIT(dev_priv->dev))
  103. ironlake_check_encoder_dotclock(pipe_config, dotclock);
  104. pipe_config->adjusted_mode.crtc_clock = dotclock;
  105. }
  106. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  107. * This is an exception to the general rule that mode_set doesn't turn
  108. * things on.
  109. */
  110. static void intel_pre_enable_lvds(struct intel_encoder *encoder)
  111. {
  112. struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  113. struct drm_device *dev = encoder->base.dev;
  114. struct drm_i915_private *dev_priv = dev->dev_private;
  115. struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  116. const struct drm_display_mode *adjusted_mode =
  117. &crtc->config.adjusted_mode;
  118. int pipe = crtc->pipe;
  119. u32 temp;
  120. if (HAS_PCH_SPLIT(dev)) {
  121. assert_fdi_rx_pll_disabled(dev_priv, pipe);
  122. assert_shared_dpll_disabled(dev_priv,
  123. intel_crtc_to_shared_dpll(crtc));
  124. } else {
  125. assert_pll_disabled(dev_priv, pipe);
  126. }
  127. temp = I915_READ(lvds_encoder->reg);
  128. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  129. if (HAS_PCH_CPT(dev)) {
  130. temp &= ~PORT_TRANS_SEL_MASK;
  131. temp |= PORT_TRANS_SEL_CPT(pipe);
  132. } else {
  133. if (pipe == 1) {
  134. temp |= LVDS_PIPEB_SELECT;
  135. } else {
  136. temp &= ~LVDS_PIPEB_SELECT;
  137. }
  138. }
  139. /* set the corresponsding LVDS_BORDER bit */
  140. temp &= ~LVDS_BORDER_ENABLE;
  141. temp |= crtc->config.gmch_pfit.lvds_border_bits;
  142. /* Set the B0-B3 data pairs corresponding to whether we're going to
  143. * set the DPLLs for dual-channel mode or not.
  144. */
  145. if (lvds_encoder->is_dual_link)
  146. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  147. else
  148. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  149. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  150. * appropriately here, but we need to look more thoroughly into how
  151. * panels behave in the two modes.
  152. */
  153. /* Set the dithering flag on LVDS as needed, note that there is no
  154. * special lvds dither control bit on pch-split platforms, dithering is
  155. * only controlled through the PIPECONF reg. */
  156. if (INTEL_INFO(dev)->gen == 4) {
  157. /* Bspec wording suggests that LVDS port dithering only exists
  158. * for 18bpp panels. */
  159. if (crtc->config.dither && crtc->config.pipe_bpp == 18)
  160. temp |= LVDS_ENABLE_DITHER;
  161. else
  162. temp &= ~LVDS_ENABLE_DITHER;
  163. }
  164. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  165. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  166. temp |= LVDS_HSYNC_POLARITY;
  167. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  168. temp |= LVDS_VSYNC_POLARITY;
  169. I915_WRITE(lvds_encoder->reg, temp);
  170. }
  171. /**
  172. * Sets the power state for the panel.
  173. */
  174. static void intel_enable_lvds(struct intel_encoder *encoder)
  175. {
  176. struct drm_device *dev = encoder->base.dev;
  177. struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  178. struct intel_connector *intel_connector =
  179. &lvds_encoder->attached_connector->base;
  180. struct drm_i915_private *dev_priv = dev->dev_private;
  181. u32 ctl_reg, stat_reg;
  182. if (HAS_PCH_SPLIT(dev)) {
  183. ctl_reg = PCH_PP_CONTROL;
  184. stat_reg = PCH_PP_STATUS;
  185. } else {
  186. ctl_reg = PP_CONTROL;
  187. stat_reg = PP_STATUS;
  188. }
  189. I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
  190. I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
  191. POSTING_READ(lvds_encoder->reg);
  192. if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
  193. DRM_ERROR("timed out waiting for panel to power on\n");
  194. intel_panel_enable_backlight(intel_connector);
  195. }
  196. static void intel_disable_lvds(struct intel_encoder *encoder)
  197. {
  198. struct drm_device *dev = encoder->base.dev;
  199. struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  200. struct intel_connector *intel_connector =
  201. &lvds_encoder->attached_connector->base;
  202. struct drm_i915_private *dev_priv = dev->dev_private;
  203. u32 ctl_reg, stat_reg;
  204. if (HAS_PCH_SPLIT(dev)) {
  205. ctl_reg = PCH_PP_CONTROL;
  206. stat_reg = PCH_PP_STATUS;
  207. } else {
  208. ctl_reg = PP_CONTROL;
  209. stat_reg = PP_STATUS;
  210. }
  211. intel_panel_disable_backlight(intel_connector);
  212. I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
  213. if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
  214. DRM_ERROR("timed out waiting for panel to power off\n");
  215. I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
  216. POSTING_READ(lvds_encoder->reg);
  217. }
  218. static int intel_lvds_mode_valid(struct drm_connector *connector,
  219. struct drm_display_mode *mode)
  220. {
  221. struct intel_connector *intel_connector = to_intel_connector(connector);
  222. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  223. if (mode->hdisplay > fixed_mode->hdisplay)
  224. return MODE_PANEL;
  225. if (mode->vdisplay > fixed_mode->vdisplay)
  226. return MODE_PANEL;
  227. return MODE_OK;
  228. }
  229. static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
  230. struct intel_crtc_config *pipe_config)
  231. {
  232. struct drm_device *dev = intel_encoder->base.dev;
  233. struct drm_i915_private *dev_priv = dev->dev_private;
  234. struct intel_lvds_encoder *lvds_encoder =
  235. to_lvds_encoder(&intel_encoder->base);
  236. struct intel_connector *intel_connector =
  237. &lvds_encoder->attached_connector->base;
  238. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  239. struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
  240. unsigned int lvds_bpp;
  241. /* Should never happen!! */
  242. if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
  243. DRM_ERROR("Can't support LVDS on pipe A\n");
  244. return false;
  245. }
  246. if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
  247. LVDS_A3_POWER_UP)
  248. lvds_bpp = 8*3;
  249. else
  250. lvds_bpp = 6*3;
  251. if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
  252. DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
  253. pipe_config->pipe_bpp, lvds_bpp);
  254. pipe_config->pipe_bpp = lvds_bpp;
  255. }
  256. /*
  257. * We have timings from the BIOS for the panel, put them in
  258. * to the adjusted mode. The CRTC will be set up for this mode,
  259. * with the panel scaling set up to source from the H/VDisplay
  260. * of the original mode.
  261. */
  262. intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
  263. adjusted_mode);
  264. if (HAS_PCH_SPLIT(dev)) {
  265. pipe_config->has_pch_encoder = true;
  266. intel_pch_panel_fitting(intel_crtc, pipe_config,
  267. intel_connector->panel.fitting_mode);
  268. } else {
  269. intel_gmch_panel_fitting(intel_crtc, pipe_config,
  270. intel_connector->panel.fitting_mode);
  271. }
  272. /*
  273. * XXX: It would be nice to support lower refresh rates on the
  274. * panels to reduce power consumption, and perhaps match the
  275. * user's requested refresh rate.
  276. */
  277. return true;
  278. }
  279. static void intel_lvds_mode_set(struct intel_encoder *encoder)
  280. {
  281. /*
  282. * We don't do anything here, the LVDS port is fully set up in the pre
  283. * enable hook - the ordering constraints for enabling the lvds port vs.
  284. * enabling the display pll are too strict.
  285. */
  286. }
  287. /**
  288. * Detect the LVDS connection.
  289. *
  290. * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
  291. * connected and closed means disconnected. We also send hotplug events as
  292. * needed, using lid status notification from the input layer.
  293. */
  294. static enum drm_connector_status
  295. intel_lvds_detect(struct drm_connector *connector, bool force)
  296. {
  297. struct drm_device *dev = connector->dev;
  298. enum drm_connector_status status;
  299. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  300. connector->base.id, drm_get_connector_name(connector));
  301. status = intel_panel_detect(dev);
  302. if (status != connector_status_unknown)
  303. return status;
  304. return connector_status_connected;
  305. }
  306. /**
  307. * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
  308. */
  309. static int intel_lvds_get_modes(struct drm_connector *connector)
  310. {
  311. struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
  312. struct drm_device *dev = connector->dev;
  313. struct drm_display_mode *mode;
  314. /* use cached edid if we have one */
  315. if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
  316. return drm_add_edid_modes(connector, lvds_connector->base.edid);
  317. mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
  318. if (mode == NULL)
  319. return 0;
  320. drm_mode_probed_add(connector, mode);
  321. return 1;
  322. }
  323. static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
  324. {
  325. DRM_INFO("Skipping forced modeset for %s\n", id->ident);
  326. return 1;
  327. }
  328. /* The GPU hangs up on these systems if modeset is performed on LID open */
  329. static const struct dmi_system_id intel_no_modeset_on_lid[] = {
  330. {
  331. .callback = intel_no_modeset_on_lid_dmi_callback,
  332. .ident = "Toshiba Tecra A11",
  333. .matches = {
  334. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  335. DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
  336. },
  337. },
  338. { } /* terminating entry */
  339. };
  340. /*
  341. * Lid events. Note the use of 'modeset':
  342. * - we set it to MODESET_ON_LID_OPEN on lid close,
  343. * and set it to MODESET_DONE on open
  344. * - we use it as a "only once" bit (ie we ignore
  345. * duplicate events where it was already properly set)
  346. * - the suspend/resume paths will set it to
  347. * MODESET_SUSPENDED and ignore the lid open event,
  348. * because they restore the mode ("lid open").
  349. */
  350. static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
  351. void *unused)
  352. {
  353. struct intel_lvds_connector *lvds_connector =
  354. container_of(nb, struct intel_lvds_connector, lid_notifier);
  355. struct drm_connector *connector = &lvds_connector->base.base;
  356. struct drm_device *dev = connector->dev;
  357. struct drm_i915_private *dev_priv = dev->dev_private;
  358. if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
  359. return NOTIFY_OK;
  360. mutex_lock(&dev_priv->modeset_restore_lock);
  361. if (dev_priv->modeset_restore == MODESET_SUSPENDED)
  362. goto exit;
  363. /*
  364. * check and update the status of LVDS connector after receiving
  365. * the LID nofication event.
  366. */
  367. connector->status = connector->funcs->detect(connector, false);
  368. /* Don't force modeset on machines where it causes a GPU lockup */
  369. if (dmi_check_system(intel_no_modeset_on_lid))
  370. goto exit;
  371. if (!acpi_lid_open()) {
  372. /* do modeset on next lid open event */
  373. dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
  374. goto exit;
  375. }
  376. if (dev_priv->modeset_restore == MODESET_DONE)
  377. goto exit;
  378. drm_modeset_lock_all(dev);
  379. intel_modeset_setup_hw_state(dev, true);
  380. drm_modeset_unlock_all(dev);
  381. dev_priv->modeset_restore = MODESET_DONE;
  382. exit:
  383. mutex_unlock(&dev_priv->modeset_restore_lock);
  384. return NOTIFY_OK;
  385. }
  386. /**
  387. * intel_lvds_destroy - unregister and free LVDS structures
  388. * @connector: connector to free
  389. *
  390. * Unregister the DDC bus for this connector then free the driver private
  391. * structure.
  392. */
  393. static void intel_lvds_destroy(struct drm_connector *connector)
  394. {
  395. struct intel_lvds_connector *lvds_connector =
  396. to_lvds_connector(connector);
  397. if (lvds_connector->lid_notifier.notifier_call)
  398. acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
  399. if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
  400. kfree(lvds_connector->base.edid);
  401. intel_panel_fini(&lvds_connector->base.panel);
  402. drm_connector_cleanup(connector);
  403. kfree(connector);
  404. }
  405. static int intel_lvds_set_property(struct drm_connector *connector,
  406. struct drm_property *property,
  407. uint64_t value)
  408. {
  409. struct intel_connector *intel_connector = to_intel_connector(connector);
  410. struct drm_device *dev = connector->dev;
  411. if (property == dev->mode_config.scaling_mode_property) {
  412. struct drm_crtc *crtc;
  413. if (value == DRM_MODE_SCALE_NONE) {
  414. DRM_DEBUG_KMS("no scaling not supported\n");
  415. return -EINVAL;
  416. }
  417. if (intel_connector->panel.fitting_mode == value) {
  418. /* the LVDS scaling property is not changed */
  419. return 0;
  420. }
  421. intel_connector->panel.fitting_mode = value;
  422. crtc = intel_attached_encoder(connector)->base.crtc;
  423. if (crtc && crtc->enabled) {
  424. /*
  425. * If the CRTC is enabled, the display will be changed
  426. * according to the new panel fitting mode.
  427. */
  428. intel_crtc_restore_mode(crtc);
  429. }
  430. }
  431. return 0;
  432. }
  433. static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
  434. .get_modes = intel_lvds_get_modes,
  435. .mode_valid = intel_lvds_mode_valid,
  436. .best_encoder = intel_best_encoder,
  437. };
  438. static const struct drm_connector_funcs intel_lvds_connector_funcs = {
  439. .dpms = intel_connector_dpms,
  440. .detect = intel_lvds_detect,
  441. .fill_modes = drm_helper_probe_single_connector_modes,
  442. .set_property = intel_lvds_set_property,
  443. .destroy = intel_lvds_destroy,
  444. };
  445. static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
  446. .destroy = intel_encoder_destroy,
  447. };
  448. static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
  449. {
  450. DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
  451. return 1;
  452. }
  453. /* These systems claim to have LVDS, but really don't */
  454. static const struct dmi_system_id intel_no_lvds[] = {
  455. {
  456. .callback = intel_no_lvds_dmi_callback,
  457. .ident = "Apple Mac Mini (Core series)",
  458. .matches = {
  459. DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
  460. DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
  461. },
  462. },
  463. {
  464. .callback = intel_no_lvds_dmi_callback,
  465. .ident = "Apple Mac Mini (Core 2 series)",
  466. .matches = {
  467. DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
  468. DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
  469. },
  470. },
  471. {
  472. .callback = intel_no_lvds_dmi_callback,
  473. .ident = "MSI IM-945GSE-A",
  474. .matches = {
  475. DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
  476. DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
  477. },
  478. },
  479. {
  480. .callback = intel_no_lvds_dmi_callback,
  481. .ident = "Dell Studio Hybrid",
  482. .matches = {
  483. DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  484. DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
  485. },
  486. },
  487. {
  488. .callback = intel_no_lvds_dmi_callback,
  489. .ident = "Dell OptiPlex FX170",
  490. .matches = {
  491. DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  492. DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
  493. },
  494. },
  495. {
  496. .callback = intel_no_lvds_dmi_callback,
  497. .ident = "AOpen Mini PC",
  498. .matches = {
  499. DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
  500. DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
  501. },
  502. },
  503. {
  504. .callback = intel_no_lvds_dmi_callback,
  505. .ident = "AOpen Mini PC MP915",
  506. .matches = {
  507. DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
  508. DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
  509. },
  510. },
  511. {
  512. .callback = intel_no_lvds_dmi_callback,
  513. .ident = "AOpen i915GMm-HFS",
  514. .matches = {
  515. DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
  516. DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
  517. },
  518. },
  519. {
  520. .callback = intel_no_lvds_dmi_callback,
  521. .ident = "AOpen i45GMx-I",
  522. .matches = {
  523. DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
  524. DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
  525. },
  526. },
  527. {
  528. .callback = intel_no_lvds_dmi_callback,
  529. .ident = "Aopen i945GTt-VFA",
  530. .matches = {
  531. DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
  532. },
  533. },
  534. {
  535. .callback = intel_no_lvds_dmi_callback,
  536. .ident = "Clientron U800",
  537. .matches = {
  538. DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
  539. DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
  540. },
  541. },
  542. {
  543. .callback = intel_no_lvds_dmi_callback,
  544. .ident = "Clientron E830",
  545. .matches = {
  546. DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
  547. DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
  548. },
  549. },
  550. {
  551. .callback = intel_no_lvds_dmi_callback,
  552. .ident = "Asus EeeBox PC EB1007",
  553. .matches = {
  554. DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
  555. DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
  556. },
  557. },
  558. {
  559. .callback = intel_no_lvds_dmi_callback,
  560. .ident = "Asus AT5NM10T-I",
  561. .matches = {
  562. DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
  563. DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
  564. },
  565. },
  566. {
  567. .callback = intel_no_lvds_dmi_callback,
  568. .ident = "Hewlett-Packard HP t5740",
  569. .matches = {
  570. DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
  571. DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
  572. },
  573. },
  574. {
  575. .callback = intel_no_lvds_dmi_callback,
  576. .ident = "Hewlett-Packard t5745",
  577. .matches = {
  578. DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
  579. DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
  580. },
  581. },
  582. {
  583. .callback = intel_no_lvds_dmi_callback,
  584. .ident = "Hewlett-Packard st5747",
  585. .matches = {
  586. DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
  587. DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
  588. },
  589. },
  590. {
  591. .callback = intel_no_lvds_dmi_callback,
  592. .ident = "MSI Wind Box DC500",
  593. .matches = {
  594. DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
  595. DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
  596. },
  597. },
  598. {
  599. .callback = intel_no_lvds_dmi_callback,
  600. .ident = "Gigabyte GA-D525TUD",
  601. .matches = {
  602. DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
  603. DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
  604. },
  605. },
  606. {
  607. .callback = intel_no_lvds_dmi_callback,
  608. .ident = "Supermicro X7SPA-H",
  609. .matches = {
  610. DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
  611. DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
  612. },
  613. },
  614. {
  615. .callback = intel_no_lvds_dmi_callback,
  616. .ident = "Fujitsu Esprimo Q900",
  617. .matches = {
  618. DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
  619. DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
  620. },
  621. },
  622. {
  623. .callback = intel_no_lvds_dmi_callback,
  624. .ident = "Intel D410PT",
  625. .matches = {
  626. DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
  627. DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
  628. },
  629. },
  630. {
  631. .callback = intel_no_lvds_dmi_callback,
  632. .ident = "Intel D425KT",
  633. .matches = {
  634. DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
  635. DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
  636. },
  637. },
  638. {
  639. .callback = intel_no_lvds_dmi_callback,
  640. .ident = "Intel D510MO",
  641. .matches = {
  642. DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
  643. DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
  644. },
  645. },
  646. {
  647. .callback = intel_no_lvds_dmi_callback,
  648. .ident = "Intel D525MW",
  649. .matches = {
  650. DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
  651. DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
  652. },
  653. },
  654. { } /* terminating entry */
  655. };
  656. /**
  657. * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
  658. * @dev: drm device
  659. * @connector: LVDS connector
  660. *
  661. * Find the reduced downclock for LVDS in EDID.
  662. */
  663. static void intel_find_lvds_downclock(struct drm_device *dev,
  664. struct drm_display_mode *fixed_mode,
  665. struct drm_connector *connector)
  666. {
  667. struct drm_i915_private *dev_priv = dev->dev_private;
  668. struct drm_display_mode *scan;
  669. int temp_downclock;
  670. temp_downclock = fixed_mode->clock;
  671. list_for_each_entry(scan, &connector->probed_modes, head) {
  672. /*
  673. * If one mode has the same resolution with the fixed_panel
  674. * mode while they have the different refresh rate, it means
  675. * that the reduced downclock is found for the LVDS. In such
  676. * case we can set the different FPx0/1 to dynamically select
  677. * between low and high frequency.
  678. */
  679. if (scan->hdisplay == fixed_mode->hdisplay &&
  680. scan->hsync_start == fixed_mode->hsync_start &&
  681. scan->hsync_end == fixed_mode->hsync_end &&
  682. scan->htotal == fixed_mode->htotal &&
  683. scan->vdisplay == fixed_mode->vdisplay &&
  684. scan->vsync_start == fixed_mode->vsync_start &&
  685. scan->vsync_end == fixed_mode->vsync_end &&
  686. scan->vtotal == fixed_mode->vtotal) {
  687. if (scan->clock < temp_downclock) {
  688. /*
  689. * The downclock is already found. But we
  690. * expect to find the lower downclock.
  691. */
  692. temp_downclock = scan->clock;
  693. }
  694. }
  695. }
  696. if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
  697. /* We found the downclock for LVDS. */
  698. dev_priv->lvds_downclock_avail = 1;
  699. dev_priv->lvds_downclock = temp_downclock;
  700. DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
  701. "Normal clock %dKhz, downclock %dKhz\n",
  702. fixed_mode->clock, temp_downclock);
  703. }
  704. }
  705. /*
  706. * Enumerate the child dev array parsed from VBT to check whether
  707. * the LVDS is present.
  708. * If it is present, return 1.
  709. * If it is not present, return false.
  710. * If no child dev is parsed from VBT, it assumes that the LVDS is present.
  711. */
  712. static bool lvds_is_present_in_vbt(struct drm_device *dev,
  713. u8 *i2c_pin)
  714. {
  715. struct drm_i915_private *dev_priv = dev->dev_private;
  716. int i;
  717. if (!dev_priv->vbt.child_dev_num)
  718. return true;
  719. for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
  720. union child_device_config *uchild = dev_priv->vbt.child_dev + i;
  721. struct old_child_dev_config *child = &uchild->old;
  722. /* If the device type is not LFP, continue.
  723. * We have to check both the new identifiers as well as the
  724. * old for compatibility with some BIOSes.
  725. */
  726. if (child->device_type != DEVICE_TYPE_INT_LFP &&
  727. child->device_type != DEVICE_TYPE_LFP)
  728. continue;
  729. if (intel_gmbus_is_port_valid(child->i2c_pin))
  730. *i2c_pin = child->i2c_pin;
  731. /* However, we cannot trust the BIOS writers to populate
  732. * the VBT correctly. Since LVDS requires additional
  733. * information from AIM blocks, a non-zero addin offset is
  734. * a good indicator that the LVDS is actually present.
  735. */
  736. if (child->addin_offset)
  737. return true;
  738. /* But even then some BIOS writers perform some black magic
  739. * and instantiate the device without reference to any
  740. * additional data. Trust that if the VBT was written into
  741. * the OpRegion then they have validated the LVDS's existence.
  742. */
  743. if (dev_priv->opregion.vbt)
  744. return true;
  745. }
  746. return false;
  747. }
  748. static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
  749. {
  750. DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
  751. return 1;
  752. }
  753. static const struct dmi_system_id intel_dual_link_lvds[] = {
  754. {
  755. .callback = intel_dual_link_lvds_callback,
  756. .ident = "Apple MacBook Pro (Core i5/i7 Series)",
  757. .matches = {
  758. DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
  759. DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
  760. },
  761. },
  762. { } /* terminating entry */
  763. };
  764. bool intel_is_dual_link_lvds(struct drm_device *dev)
  765. {
  766. struct intel_encoder *encoder;
  767. struct intel_lvds_encoder *lvds_encoder;
  768. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  769. base.head) {
  770. if (encoder->type == INTEL_OUTPUT_LVDS) {
  771. lvds_encoder = to_lvds_encoder(&encoder->base);
  772. return lvds_encoder->is_dual_link;
  773. }
  774. }
  775. return false;
  776. }
  777. static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
  778. {
  779. struct drm_device *dev = lvds_encoder->base.base.dev;
  780. unsigned int val;
  781. struct drm_i915_private *dev_priv = dev->dev_private;
  782. /* use the module option value if specified */
  783. if (i915_lvds_channel_mode > 0)
  784. return i915_lvds_channel_mode == 2;
  785. if (dmi_check_system(intel_dual_link_lvds))
  786. return true;
  787. /* BIOS should set the proper LVDS register value at boot, but
  788. * in reality, it doesn't set the value when the lid is closed;
  789. * we need to check "the value to be set" in VBT when LVDS
  790. * register is uninitialized.
  791. */
  792. val = I915_READ(lvds_encoder->reg);
  793. if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
  794. val = dev_priv->vbt.bios_lvds_val;
  795. return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
  796. }
  797. static bool intel_lvds_supported(struct drm_device *dev)
  798. {
  799. /* With the introduction of the PCH we gained a dedicated
  800. * LVDS presence pin, use it. */
  801. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  802. return true;
  803. /* Otherwise LVDS was only attached to mobile products,
  804. * except for the inglorious 830gm */
  805. if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
  806. return true;
  807. return false;
  808. }
  809. /**
  810. * intel_lvds_init - setup LVDS connectors on this device
  811. * @dev: drm device
  812. *
  813. * Create the connector, register the LVDS DDC bus, and try to figure out what
  814. * modes we can display on the LVDS panel (if present).
  815. */
  816. void intel_lvds_init(struct drm_device *dev)
  817. {
  818. struct drm_i915_private *dev_priv = dev->dev_private;
  819. struct intel_lvds_encoder *lvds_encoder;
  820. struct intel_encoder *intel_encoder;
  821. struct intel_lvds_connector *lvds_connector;
  822. struct intel_connector *intel_connector;
  823. struct drm_connector *connector;
  824. struct drm_encoder *encoder;
  825. struct drm_display_mode *scan; /* *modes, *bios_mode; */
  826. struct drm_display_mode *fixed_mode = NULL;
  827. struct edid *edid;
  828. struct drm_crtc *crtc;
  829. u32 lvds;
  830. int pipe;
  831. u8 pin;
  832. if (!intel_lvds_supported(dev))
  833. return;
  834. /* Skip init on machines we know falsely report LVDS */
  835. if (dmi_check_system(intel_no_lvds))
  836. return;
  837. pin = GMBUS_PORT_PANEL;
  838. if (!lvds_is_present_in_vbt(dev, &pin)) {
  839. DRM_DEBUG_KMS("LVDS is not present in VBT\n");
  840. return;
  841. }
  842. if (HAS_PCH_SPLIT(dev)) {
  843. if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
  844. return;
  845. if (dev_priv->vbt.edp_support) {
  846. DRM_DEBUG_KMS("disable LVDS for eDP support\n");
  847. return;
  848. }
  849. }
  850. lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
  851. if (!lvds_encoder)
  852. return;
  853. lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
  854. if (!lvds_connector) {
  855. kfree(lvds_encoder);
  856. return;
  857. }
  858. lvds_encoder->attached_connector = lvds_connector;
  859. intel_encoder = &lvds_encoder->base;
  860. encoder = &intel_encoder->base;
  861. intel_connector = &lvds_connector->base;
  862. connector = &intel_connector->base;
  863. drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
  864. DRM_MODE_CONNECTOR_LVDS);
  865. drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
  866. DRM_MODE_ENCODER_LVDS);
  867. intel_encoder->enable = intel_enable_lvds;
  868. intel_encoder->pre_enable = intel_pre_enable_lvds;
  869. intel_encoder->compute_config = intel_lvds_compute_config;
  870. intel_encoder->mode_set = intel_lvds_mode_set;
  871. intel_encoder->disable = intel_disable_lvds;
  872. intel_encoder->get_hw_state = intel_lvds_get_hw_state;
  873. intel_encoder->get_config = intel_lvds_get_config;
  874. intel_connector->get_hw_state = intel_connector_get_hw_state;
  875. intel_connector_attach_encoder(intel_connector, intel_encoder);
  876. intel_encoder->type = INTEL_OUTPUT_LVDS;
  877. intel_encoder->cloneable = false;
  878. if (HAS_PCH_SPLIT(dev))
  879. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  880. else if (IS_GEN4(dev))
  881. intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  882. else
  883. intel_encoder->crtc_mask = (1 << 1);
  884. drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
  885. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  886. connector->interlace_allowed = false;
  887. connector->doublescan_allowed = false;
  888. if (HAS_PCH_SPLIT(dev)) {
  889. lvds_encoder->reg = PCH_LVDS;
  890. } else {
  891. lvds_encoder->reg = LVDS;
  892. }
  893. /* create the scaling mode property */
  894. drm_mode_create_scaling_mode_property(dev);
  895. drm_object_attach_property(&connector->base,
  896. dev->mode_config.scaling_mode_property,
  897. DRM_MODE_SCALE_ASPECT);
  898. intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
  899. /*
  900. * LVDS discovery:
  901. * 1) check for EDID on DDC
  902. * 2) check for VBT data
  903. * 3) check to see if LVDS is already on
  904. * if none of the above, no panel
  905. * 4) make sure lid is open
  906. * if closed, act like it's not there for now
  907. */
  908. /*
  909. * Attempt to get the fixed panel mode from DDC. Assume that the
  910. * preferred mode is the right one.
  911. */
  912. edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
  913. if (edid) {
  914. if (drm_add_edid_modes(connector, edid)) {
  915. drm_mode_connector_update_edid_property(connector,
  916. edid);
  917. } else {
  918. kfree(edid);
  919. edid = ERR_PTR(-EINVAL);
  920. }
  921. } else {
  922. edid = ERR_PTR(-ENOENT);
  923. }
  924. lvds_connector->base.edid = edid;
  925. if (IS_ERR_OR_NULL(edid)) {
  926. /* Didn't get an EDID, so
  927. * Set wide sync ranges so we get all modes
  928. * handed to valid_mode for checking
  929. */
  930. connector->display_info.min_vfreq = 0;
  931. connector->display_info.max_vfreq = 200;
  932. connector->display_info.min_hfreq = 0;
  933. connector->display_info.max_hfreq = 200;
  934. }
  935. list_for_each_entry(scan, &connector->probed_modes, head) {
  936. if (scan->type & DRM_MODE_TYPE_PREFERRED) {
  937. DRM_DEBUG_KMS("using preferred mode from EDID: ");
  938. drm_mode_debug_printmodeline(scan);
  939. fixed_mode = drm_mode_duplicate(dev, scan);
  940. if (fixed_mode) {
  941. intel_find_lvds_downclock(dev, fixed_mode,
  942. connector);
  943. goto out;
  944. }
  945. }
  946. }
  947. /* Failed to get EDID, what about VBT? */
  948. if (dev_priv->vbt.lfp_lvds_vbt_mode) {
  949. DRM_DEBUG_KMS("using mode from VBT: ");
  950. drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
  951. fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
  952. if (fixed_mode) {
  953. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  954. goto out;
  955. }
  956. }
  957. /*
  958. * If we didn't get EDID, try checking if the panel is already turned
  959. * on. If so, assume that whatever is currently programmed is the
  960. * correct mode.
  961. */
  962. /* Ironlake: FIXME if still fail, not try pipe mode now */
  963. if (HAS_PCH_SPLIT(dev))
  964. goto failed;
  965. lvds = I915_READ(LVDS);
  966. pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
  967. crtc = intel_get_crtc_for_pipe(dev, pipe);
  968. if (crtc && (lvds & LVDS_PORT_EN)) {
  969. fixed_mode = intel_crtc_mode_get(dev, crtc);
  970. if (fixed_mode) {
  971. DRM_DEBUG_KMS("using current (BIOS) mode: ");
  972. drm_mode_debug_printmodeline(fixed_mode);
  973. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  974. goto out;
  975. }
  976. }
  977. /* If we still don't have a mode after all that, give up. */
  978. if (!fixed_mode)
  979. goto failed;
  980. out:
  981. lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
  982. DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
  983. lvds_encoder->is_dual_link ? "dual" : "single");
  984. /*
  985. * Unlock registers and just
  986. * leave them unlocked
  987. */
  988. if (HAS_PCH_SPLIT(dev)) {
  989. I915_WRITE(PCH_PP_CONTROL,
  990. I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
  991. } else {
  992. I915_WRITE(PP_CONTROL,
  993. I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
  994. }
  995. lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
  996. if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
  997. DRM_DEBUG_KMS("lid notifier registration failed\n");
  998. lvds_connector->lid_notifier.notifier_call = NULL;
  999. }
  1000. drm_sysfs_connector_add(connector);
  1001. intel_panel_init(&intel_connector->panel, fixed_mode);
  1002. intel_panel_setup_backlight(connector);
  1003. return;
  1004. failed:
  1005. DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
  1006. drm_connector_cleanup(connector);
  1007. drm_encoder_cleanup(encoder);
  1008. if (fixed_mode)
  1009. drm_mode_destroy(dev, fixed_mode);
  1010. kfree(lvds_encoder);
  1011. kfree(lvds_connector);
  1012. return;
  1013. }