i915_suspend.c 16 KB

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  1. /*
  2. *
  3. * Copyright 2008 (c) Intel Corporation
  4. * Jesse Barnes <jbarnes@virtuousgeek.org>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. */
  26. #include <drm/drmP.h>
  27. #include <drm/i915_drm.h>
  28. #include "intel_drv.h"
  29. #include "i915_reg.h"
  30. static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
  31. {
  32. struct drm_i915_private *dev_priv = dev->dev_private;
  33. I915_WRITE8(index_port, reg);
  34. return I915_READ8(data_port);
  35. }
  36. static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
  37. {
  38. struct drm_i915_private *dev_priv = dev->dev_private;
  39. I915_READ8(st01);
  40. I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
  41. return I915_READ8(VGA_AR_DATA_READ);
  42. }
  43. static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
  44. {
  45. struct drm_i915_private *dev_priv = dev->dev_private;
  46. I915_READ8(st01);
  47. I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
  48. I915_WRITE8(VGA_AR_DATA_WRITE, val);
  49. }
  50. static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
  51. {
  52. struct drm_i915_private *dev_priv = dev->dev_private;
  53. I915_WRITE8(index_port, reg);
  54. I915_WRITE8(data_port, val);
  55. }
  56. static void i915_save_vga(struct drm_device *dev)
  57. {
  58. struct drm_i915_private *dev_priv = dev->dev_private;
  59. int i;
  60. u16 cr_index, cr_data, st01;
  61. /* VGA state */
  62. dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
  63. dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
  64. dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
  65. dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
  66. /* VGA color palette registers */
  67. dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
  68. /* MSR bits */
  69. dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
  70. if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
  71. cr_index = VGA_CR_INDEX_CGA;
  72. cr_data = VGA_CR_DATA_CGA;
  73. st01 = VGA_ST01_CGA;
  74. } else {
  75. cr_index = VGA_CR_INDEX_MDA;
  76. cr_data = VGA_CR_DATA_MDA;
  77. st01 = VGA_ST01_MDA;
  78. }
  79. /* CRT controller regs */
  80. i915_write_indexed(dev, cr_index, cr_data, 0x11,
  81. i915_read_indexed(dev, cr_index, cr_data, 0x11) &
  82. (~0x80));
  83. for (i = 0; i <= 0x24; i++)
  84. dev_priv->regfile.saveCR[i] =
  85. i915_read_indexed(dev, cr_index, cr_data, i);
  86. /* Make sure we don't turn off CR group 0 writes */
  87. dev_priv->regfile.saveCR[0x11] &= ~0x80;
  88. /* Attribute controller registers */
  89. I915_READ8(st01);
  90. dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
  91. for (i = 0; i <= 0x14; i++)
  92. dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
  93. I915_READ8(st01);
  94. I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
  95. I915_READ8(st01);
  96. /* Graphics controller registers */
  97. for (i = 0; i < 9; i++)
  98. dev_priv->regfile.saveGR[i] =
  99. i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
  100. dev_priv->regfile.saveGR[0x10] =
  101. i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
  102. dev_priv->regfile.saveGR[0x11] =
  103. i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
  104. dev_priv->regfile.saveGR[0x18] =
  105. i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
  106. /* Sequencer registers */
  107. for (i = 0; i < 8; i++)
  108. dev_priv->regfile.saveSR[i] =
  109. i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
  110. }
  111. static void i915_restore_vga(struct drm_device *dev)
  112. {
  113. struct drm_i915_private *dev_priv = dev->dev_private;
  114. int i;
  115. u16 cr_index, cr_data, st01;
  116. /* VGA state */
  117. I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
  118. I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
  119. I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
  120. I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
  121. POSTING_READ(VGA_PD);
  122. udelay(150);
  123. /* MSR bits */
  124. I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
  125. if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
  126. cr_index = VGA_CR_INDEX_CGA;
  127. cr_data = VGA_CR_DATA_CGA;
  128. st01 = VGA_ST01_CGA;
  129. } else {
  130. cr_index = VGA_CR_INDEX_MDA;
  131. cr_data = VGA_CR_DATA_MDA;
  132. st01 = VGA_ST01_MDA;
  133. }
  134. /* Sequencer registers, don't write SR07 */
  135. for (i = 0; i < 7; i++)
  136. i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
  137. dev_priv->regfile.saveSR[i]);
  138. /* CRT controller regs */
  139. /* Enable CR group 0 writes */
  140. i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
  141. for (i = 0; i <= 0x24; i++)
  142. i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
  143. /* Graphics controller regs */
  144. for (i = 0; i < 9; i++)
  145. i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
  146. dev_priv->regfile.saveGR[i]);
  147. i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
  148. dev_priv->regfile.saveGR[0x10]);
  149. i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
  150. dev_priv->regfile.saveGR[0x11]);
  151. i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
  152. dev_priv->regfile.saveGR[0x18]);
  153. /* Attribute controller registers */
  154. I915_READ8(st01); /* switch back to index mode */
  155. for (i = 0; i <= 0x14; i++)
  156. i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
  157. I915_READ8(st01); /* switch back to index mode */
  158. I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
  159. I915_READ8(st01);
  160. /* VGA color palette registers */
  161. I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
  162. }
  163. static void i915_save_display(struct drm_device *dev)
  164. {
  165. struct drm_i915_private *dev_priv = dev->dev_private;
  166. unsigned long flags;
  167. /* Display arbitration control */
  168. if (INTEL_INFO(dev)->gen <= 4)
  169. dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
  170. /* This is only meaningful in non-KMS mode */
  171. /* Don't regfile.save them in KMS mode */
  172. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  173. i915_save_display_reg(dev);
  174. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  175. /* LVDS state */
  176. if (HAS_PCH_SPLIT(dev)) {
  177. dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
  178. dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
  179. dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
  180. dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
  181. dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
  182. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  183. dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
  184. } else if (IS_VALLEYVIEW(dev)) {
  185. dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
  186. dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
  187. dev_priv->regfile.saveBLC_PWM_CTL =
  188. I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
  189. dev_priv->regfile.saveBLC_HIST_CTL =
  190. I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
  191. dev_priv->regfile.saveBLC_PWM_CTL2 =
  192. I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
  193. dev_priv->regfile.saveBLC_PWM_CTL_B =
  194. I915_READ(VLV_BLC_PWM_CTL(PIPE_B));
  195. dev_priv->regfile.saveBLC_HIST_CTL_B =
  196. I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
  197. dev_priv->regfile.saveBLC_PWM_CTL2_B =
  198. I915_READ(VLV_BLC_PWM_CTL2(PIPE_B));
  199. } else {
  200. dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
  201. dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
  202. dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
  203. dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
  204. if (INTEL_INFO(dev)->gen >= 4)
  205. dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
  206. if (IS_MOBILE(dev) && !IS_I830(dev))
  207. dev_priv->regfile.saveLVDS = I915_READ(LVDS);
  208. }
  209. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  210. if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
  211. dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
  212. if (HAS_PCH_SPLIT(dev)) {
  213. dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
  214. dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
  215. dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
  216. } else {
  217. dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
  218. dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
  219. dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
  220. }
  221. /* Only regfile.save FBC state on the platform that supports FBC */
  222. if (I915_HAS_FBC(dev)) {
  223. if (HAS_PCH_SPLIT(dev)) {
  224. dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
  225. } else if (IS_GM45(dev)) {
  226. dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
  227. } else {
  228. dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
  229. dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
  230. dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
  231. dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
  232. }
  233. }
  234. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  235. i915_save_vga(dev);
  236. }
  237. static void i915_restore_display(struct drm_device *dev)
  238. {
  239. struct drm_i915_private *dev_priv = dev->dev_private;
  240. u32 mask = 0xffffffff;
  241. unsigned long flags;
  242. /* Display arbitration */
  243. if (INTEL_INFO(dev)->gen <= 4)
  244. I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
  245. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  246. i915_restore_display_reg(dev);
  247. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  248. /* LVDS state */
  249. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
  250. I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
  251. if (drm_core_check_feature(dev, DRIVER_MODESET))
  252. mask = ~LVDS_PORT_EN;
  253. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  254. I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
  255. else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
  256. I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
  257. if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
  258. I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
  259. if (HAS_PCH_SPLIT(dev)) {
  260. I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
  261. I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
  262. /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
  263. * otherwise we get blank eDP screen after S3 on some machines
  264. */
  265. I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
  266. I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
  267. I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
  268. I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
  269. I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
  270. I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
  271. I915_WRITE(RSTDBYCTL,
  272. dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
  273. } else if (IS_VALLEYVIEW(dev)) {
  274. I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A),
  275. dev_priv->regfile.saveBLC_PWM_CTL);
  276. I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
  277. dev_priv->regfile.saveBLC_HIST_CTL);
  278. I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A),
  279. dev_priv->regfile.saveBLC_PWM_CTL2);
  280. I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B),
  281. dev_priv->regfile.saveBLC_PWM_CTL);
  282. I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
  283. dev_priv->regfile.saveBLC_HIST_CTL);
  284. I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B),
  285. dev_priv->regfile.saveBLC_PWM_CTL2);
  286. } else {
  287. I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
  288. I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
  289. I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
  290. I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
  291. I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
  292. I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
  293. I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
  294. }
  295. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  296. /* only restore FBC info on the platform that supports FBC*/
  297. intel_disable_fbc(dev);
  298. if (I915_HAS_FBC(dev)) {
  299. if (HAS_PCH_SPLIT(dev)) {
  300. I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
  301. } else if (IS_GM45(dev)) {
  302. I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
  303. } else {
  304. I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
  305. I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
  306. I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
  307. I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
  308. }
  309. }
  310. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  311. i915_restore_vga(dev);
  312. else
  313. i915_redisable_vga(dev);
  314. }
  315. int i915_save_state(struct drm_device *dev)
  316. {
  317. struct drm_i915_private *dev_priv = dev->dev_private;
  318. int i;
  319. if (INTEL_INFO(dev)->gen <= 4)
  320. pci_read_config_byte(dev->pdev, LBB,
  321. &dev_priv->regfile.saveLBB);
  322. mutex_lock(&dev->struct_mutex);
  323. i915_save_display(dev);
  324. if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
  325. /* Interrupt state */
  326. if (HAS_PCH_SPLIT(dev)) {
  327. dev_priv->regfile.saveDEIER = I915_READ(DEIER);
  328. dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
  329. dev_priv->regfile.saveGTIER = I915_READ(GTIER);
  330. dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
  331. dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
  332. dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
  333. dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
  334. I915_READ(RSTDBYCTL);
  335. dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
  336. } else {
  337. dev_priv->regfile.saveIER = I915_READ(IER);
  338. dev_priv->regfile.saveIMR = I915_READ(IMR);
  339. }
  340. }
  341. intel_disable_gt_powersave(dev);
  342. /* Cache mode state */
  343. if (INTEL_INFO(dev)->gen < 7)
  344. dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
  345. /* Memory Arbitration state */
  346. dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
  347. /* Scratch space */
  348. for (i = 0; i < 16; i++) {
  349. dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
  350. dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
  351. }
  352. for (i = 0; i < 3; i++)
  353. dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
  354. mutex_unlock(&dev->struct_mutex);
  355. return 0;
  356. }
  357. int i915_restore_state(struct drm_device *dev)
  358. {
  359. struct drm_i915_private *dev_priv = dev->dev_private;
  360. int i;
  361. if (INTEL_INFO(dev)->gen <= 4)
  362. pci_write_config_byte(dev->pdev, LBB,
  363. dev_priv->regfile.saveLBB);
  364. mutex_lock(&dev->struct_mutex);
  365. i915_gem_restore_fences(dev);
  366. i915_restore_display(dev);
  367. if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
  368. /* Interrupt state */
  369. if (HAS_PCH_SPLIT(dev)) {
  370. I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
  371. I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
  372. I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
  373. I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
  374. I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
  375. I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
  376. I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
  377. } else {
  378. I915_WRITE(IER, dev_priv->regfile.saveIER);
  379. I915_WRITE(IMR, dev_priv->regfile.saveIMR);
  380. }
  381. }
  382. /* Cache mode state */
  383. if (INTEL_INFO(dev)->gen < 7)
  384. I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
  385. 0xffff0000);
  386. /* Memory arbitration state */
  387. I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
  388. for (i = 0; i < 16; i++) {
  389. I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
  390. I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
  391. }
  392. for (i = 0; i < 3; i++)
  393. I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
  394. mutex_unlock(&dev->struct_mutex);
  395. intel_i2c_reset(dev);
  396. return 0;
  397. }