armada_crtc.c 31 KB

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  1. /*
  2. * Copyright (C) 2012 Russell King
  3. * Rewritten from the dovefb driver, and Armada510 manuals.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/clk.h>
  10. #include <drm/drmP.h>
  11. #include <drm/drm_crtc_helper.h>
  12. #include "armada_crtc.h"
  13. #include "armada_drm.h"
  14. #include "armada_fb.h"
  15. #include "armada_gem.h"
  16. #include "armada_hw.h"
  17. struct armada_frame_work {
  18. struct drm_pending_vblank_event *event;
  19. struct armada_regs regs[4];
  20. struct drm_framebuffer *old_fb;
  21. };
  22. enum csc_mode {
  23. CSC_AUTO = 0,
  24. CSC_YUV_CCIR601 = 1,
  25. CSC_YUV_CCIR709 = 2,
  26. CSC_RGB_COMPUTER = 1,
  27. CSC_RGB_STUDIO = 2,
  28. };
  29. /*
  30. * A note about interlacing. Let's consider HDMI 1920x1080i.
  31. * The timing parameters we have from X are:
  32. * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
  33. * 1920 2448 2492 2640 1080 1084 1094 1125
  34. * Which get translated to:
  35. * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
  36. * 1920 2448 2492 2640 540 542 547 562
  37. *
  38. * This is how it is defined by CEA-861-D - line and pixel numbers are
  39. * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
  40. * line: 2640. The odd frame, the first active line is at line 21, and
  41. * the even frame, the first active line is 584.
  42. *
  43. * LN: 560 561 562 563 567 568 569
  44. * DE: ~~~|____________________________//__________________________
  45. * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  46. * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  47. * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
  48. *
  49. * LN: 1123 1124 1125 1 5 6 7
  50. * DE: ~~~|____________________________//__________________________
  51. * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  52. * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  53. * 23 blanking lines
  54. *
  55. * The Armada LCD Controller line and pixel numbers are, like X timings,
  56. * referenced to the top left of the active frame.
  57. *
  58. * So, translating these to our LCD controller:
  59. * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  60. * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  61. * Note: Vsync front porch remains constant!
  62. *
  63. * if (odd_frame) {
  64. * vtotal = mode->crtc_vtotal + 1;
  65. * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  66. * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  67. * } else {
  68. * vtotal = mode->crtc_vtotal;
  69. * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  70. * vhorizpos = mode->crtc_hsync_start;
  71. * }
  72. * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  73. *
  74. * So, we need to reprogram these registers on each vsync event:
  75. * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
  76. *
  77. * Note: we do not use the frame done interrupts because these appear
  78. * to happen too early, and lead to jitter on the display (presumably
  79. * they occur at the end of the last active line, before the vsync back
  80. * porch, which we're reprogramming.)
  81. */
  82. void
  83. armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
  84. {
  85. while (regs->offset != ~0) {
  86. void __iomem *reg = dcrtc->base + regs->offset;
  87. uint32_t val;
  88. val = regs->mask;
  89. if (val != 0)
  90. val &= readl_relaxed(reg);
  91. writel_relaxed(val | regs->val, reg);
  92. ++regs;
  93. }
  94. }
  95. #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
  96. static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
  97. {
  98. uint32_t dumb_ctrl;
  99. dumb_ctrl = dcrtc->cfg_dumb_ctrl;
  100. if (!dpms_blanked(dcrtc->dpms))
  101. dumb_ctrl |= CFG_DUMB_ENA;
  102. /*
  103. * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
  104. * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
  105. * force LCD_D[23:0] to output blank color, overriding the GPIO or
  106. * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
  107. */
  108. if (dpms_blanked(dcrtc->dpms) &&
  109. (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
  110. dumb_ctrl &= ~DUMB_MASK;
  111. dumb_ctrl |= DUMB_BLANK;
  112. }
  113. /*
  114. * The documentation doesn't indicate what the normal state of
  115. * the sync signals are. Sebastian Hesselbart kindly probed
  116. * these signals on his board to determine their state.
  117. *
  118. * The non-inverted state of the sync signals is active high.
  119. * Setting these bits makes the appropriate signal active low.
  120. */
  121. if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
  122. dumb_ctrl |= CFG_INV_CSYNC;
  123. if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
  124. dumb_ctrl |= CFG_INV_HSYNC;
  125. if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
  126. dumb_ctrl |= CFG_INV_VSYNC;
  127. if (dcrtc->dumb_ctrl != dumb_ctrl) {
  128. dcrtc->dumb_ctrl = dumb_ctrl;
  129. writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
  130. }
  131. }
  132. static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
  133. int x, int y, struct armada_regs *regs, bool interlaced)
  134. {
  135. struct armada_gem_object *obj = drm_fb_obj(fb);
  136. unsigned pitch = fb->pitches[0];
  137. unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
  138. uint32_t addr_odd, addr_even;
  139. unsigned i = 0;
  140. DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
  141. pitch, x, y, fb->bits_per_pixel);
  142. addr_odd = addr_even = obj->dev_addr + offset;
  143. if (interlaced) {
  144. addr_even += pitch;
  145. pitch *= 2;
  146. }
  147. /* write offset, base, and pitch */
  148. armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
  149. armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
  150. armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
  151. return i;
  152. }
  153. static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
  154. struct armada_frame_work *work)
  155. {
  156. struct drm_device *dev = dcrtc->crtc.dev;
  157. unsigned long flags;
  158. int ret;
  159. ret = drm_vblank_get(dev, dcrtc->num);
  160. if (ret) {
  161. DRM_ERROR("failed to acquire vblank counter\n");
  162. return ret;
  163. }
  164. spin_lock_irqsave(&dev->event_lock, flags);
  165. if (!dcrtc->frame_work)
  166. dcrtc->frame_work = work;
  167. else
  168. ret = -EBUSY;
  169. spin_unlock_irqrestore(&dev->event_lock, flags);
  170. if (ret)
  171. drm_vblank_put(dev, dcrtc->num);
  172. return ret;
  173. }
  174. static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
  175. {
  176. struct drm_device *dev = dcrtc->crtc.dev;
  177. struct armada_frame_work *work = dcrtc->frame_work;
  178. dcrtc->frame_work = NULL;
  179. armada_drm_crtc_update_regs(dcrtc, work->regs);
  180. if (work->event)
  181. drm_send_vblank_event(dev, dcrtc->num, work->event);
  182. drm_vblank_put(dev, dcrtc->num);
  183. /* Finally, queue the process-half of the cleanup. */
  184. __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
  185. kfree(work);
  186. }
  187. static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
  188. struct drm_framebuffer *fb, bool force)
  189. {
  190. struct armada_frame_work *work;
  191. if (!fb)
  192. return;
  193. if (force) {
  194. /* Display is disabled, so just drop the old fb */
  195. drm_framebuffer_unreference(fb);
  196. return;
  197. }
  198. work = kmalloc(sizeof(*work), GFP_KERNEL);
  199. if (work) {
  200. int i = 0;
  201. work->event = NULL;
  202. work->old_fb = fb;
  203. armada_reg_queue_end(work->regs, i);
  204. if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
  205. return;
  206. kfree(work);
  207. }
  208. /*
  209. * Oops - just drop the reference immediately and hope for
  210. * the best. The worst that will happen is the buffer gets
  211. * reused before it has finished being displayed.
  212. */
  213. drm_framebuffer_unreference(fb);
  214. }
  215. static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
  216. {
  217. struct drm_device *dev = dcrtc->crtc.dev;
  218. /*
  219. * Tell the DRM core that vblank IRQs aren't going to happen for
  220. * a while. This cleans up any pending vblank events for us.
  221. */
  222. drm_vblank_off(dev, dcrtc->num);
  223. /* Handle any pending flip event. */
  224. spin_lock_irq(&dev->event_lock);
  225. if (dcrtc->frame_work)
  226. armada_drm_crtc_complete_frame_work(dcrtc);
  227. spin_unlock_irq(&dev->event_lock);
  228. }
  229. void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
  230. int idx)
  231. {
  232. }
  233. void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
  234. int idx)
  235. {
  236. }
  237. /* The mode_config.mutex will be held for this call */
  238. static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
  239. {
  240. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  241. if (dcrtc->dpms != dpms) {
  242. dcrtc->dpms = dpms;
  243. armada_drm_crtc_update(dcrtc);
  244. if (dpms_blanked(dpms))
  245. armada_drm_vblank_off(dcrtc);
  246. }
  247. }
  248. /*
  249. * Prepare for a mode set. Turn off overlay to ensure that we don't end
  250. * up with the overlay size being bigger than the active screen size.
  251. * We rely upon X refreshing this state after the mode set has completed.
  252. *
  253. * The mode_config.mutex will be held for this call
  254. */
  255. static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
  256. {
  257. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  258. struct drm_plane *plane;
  259. /*
  260. * If we have an overlay plane associated with this CRTC, disable
  261. * it before the modeset to avoid its coordinates being outside
  262. * the new mode parameters. DRM doesn't provide help with this.
  263. */
  264. plane = dcrtc->plane;
  265. if (plane) {
  266. struct drm_framebuffer *fb = plane->fb;
  267. plane->funcs->disable_plane(plane);
  268. plane->fb = NULL;
  269. plane->crtc = NULL;
  270. drm_framebuffer_unreference(fb);
  271. }
  272. }
  273. /* The mode_config.mutex will be held for this call */
  274. static void armada_drm_crtc_commit(struct drm_crtc *crtc)
  275. {
  276. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  277. if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
  278. dcrtc->dpms = DRM_MODE_DPMS_ON;
  279. armada_drm_crtc_update(dcrtc);
  280. }
  281. }
  282. /* The mode_config.mutex will be held for this call */
  283. static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
  284. const struct drm_display_mode *mode, struct drm_display_mode *adj)
  285. {
  286. struct armada_private *priv = crtc->dev->dev_private;
  287. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  288. int ret;
  289. /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
  290. if (!priv->variant->has_spu_adv_reg &&
  291. adj->flags & DRM_MODE_FLAG_INTERLACE)
  292. return false;
  293. /* Check whether the display mode is possible */
  294. ret = priv->variant->crtc_compute_clock(dcrtc, adj, NULL);
  295. if (ret)
  296. return false;
  297. return true;
  298. }
  299. void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
  300. {
  301. struct armada_vbl_event *e, *n;
  302. void __iomem *base = dcrtc->base;
  303. if (stat & DMA_FF_UNDERFLOW)
  304. DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
  305. if (stat & GRA_FF_UNDERFLOW)
  306. DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
  307. if (stat & VSYNC_IRQ)
  308. drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
  309. spin_lock(&dcrtc->irq_lock);
  310. list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
  311. list_del_init(&e->node);
  312. drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
  313. e->fn(dcrtc, e->data);
  314. }
  315. if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
  316. int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
  317. uint32_t val;
  318. writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
  319. writel_relaxed(dcrtc->v[i].spu_v_h_total,
  320. base + LCD_SPUT_V_H_TOTAL);
  321. val = readl_relaxed(base + LCD_SPU_ADV_REG);
  322. val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
  323. val |= dcrtc->v[i].spu_adv_reg;
  324. writel_relaxed(val, base + LCD_SPU_ADV_REG);
  325. }
  326. if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
  327. writel_relaxed(dcrtc->cursor_hw_pos,
  328. base + LCD_SPU_HWC_OVSA_HPXL_VLN);
  329. writel_relaxed(dcrtc->cursor_hw_sz,
  330. base + LCD_SPU_HWC_HPXL_VLN);
  331. armada_updatel(CFG_HWC_ENA,
  332. CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
  333. base + LCD_SPU_DMA_CTRL0);
  334. dcrtc->cursor_update = false;
  335. armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
  336. }
  337. spin_unlock(&dcrtc->irq_lock);
  338. if (stat & GRA_FRAME_IRQ) {
  339. struct drm_device *dev = dcrtc->crtc.dev;
  340. spin_lock(&dev->event_lock);
  341. if (dcrtc->frame_work)
  342. armada_drm_crtc_complete_frame_work(dcrtc);
  343. spin_unlock(&dev->event_lock);
  344. wake_up(&dcrtc->frame_wait);
  345. }
  346. }
  347. /* These are locked by dev->vbl_lock */
  348. void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
  349. {
  350. if (dcrtc->irq_ena & mask) {
  351. dcrtc->irq_ena &= ~mask;
  352. writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
  353. }
  354. }
  355. void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
  356. {
  357. if ((dcrtc->irq_ena & mask) != mask) {
  358. dcrtc->irq_ena |= mask;
  359. writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
  360. if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
  361. writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
  362. }
  363. }
  364. static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
  365. {
  366. struct drm_display_mode *adj = &dcrtc->crtc.mode;
  367. uint32_t val = 0;
  368. if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
  369. val |= CFG_CSC_YUV_CCIR709;
  370. if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
  371. val |= CFG_CSC_RGB_STUDIO;
  372. /*
  373. * In auto mode, set the colorimetry, based upon the HDMI spec.
  374. * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
  375. * ITU601. It may be more appropriate to set this depending on
  376. * the source - but what if the graphic frame is YUV and the
  377. * video frame is RGB?
  378. */
  379. if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
  380. !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
  381. (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
  382. if (dcrtc->csc_yuv_mode == CSC_AUTO)
  383. val |= CFG_CSC_YUV_CCIR709;
  384. }
  385. /*
  386. * We assume we're connected to a TV-like device, so the YUV->RGB
  387. * conversion should produce a limited range. We should set this
  388. * depending on the connectors attached to this CRTC, and what
  389. * kind of device they report being connected.
  390. */
  391. if (dcrtc->csc_rgb_mode == CSC_AUTO)
  392. val |= CFG_CSC_RGB_STUDIO;
  393. return val;
  394. }
  395. /* The mode_config.mutex will be held for this call */
  396. static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
  397. struct drm_display_mode *mode, struct drm_display_mode *adj,
  398. int x, int y, struct drm_framebuffer *old_fb)
  399. {
  400. struct armada_private *priv = crtc->dev->dev_private;
  401. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  402. struct armada_regs regs[17];
  403. uint32_t lm, rm, tm, bm, val, sclk;
  404. unsigned long flags;
  405. unsigned i;
  406. bool interlaced;
  407. drm_framebuffer_reference(crtc->fb);
  408. interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
  409. i = armada_drm_crtc_calc_fb(dcrtc->crtc.fb, x, y, regs, interlaced);
  410. rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
  411. lm = adj->crtc_htotal - adj->crtc_hsync_end;
  412. bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
  413. tm = adj->crtc_vtotal - adj->crtc_vsync_end;
  414. DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
  415. adj->crtc_hdisplay,
  416. adj->crtc_hsync_start,
  417. adj->crtc_hsync_end,
  418. adj->crtc_htotal, lm, rm);
  419. DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
  420. adj->crtc_vdisplay,
  421. adj->crtc_vsync_start,
  422. adj->crtc_vsync_end,
  423. adj->crtc_vtotal, tm, bm);
  424. /* Wait for pending flips to complete */
  425. wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
  426. drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
  427. crtc->mode = *adj;
  428. val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
  429. if (val != dcrtc->dumb_ctrl) {
  430. dcrtc->dumb_ctrl = val;
  431. writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
  432. }
  433. /* Now compute the divider for real */
  434. priv->variant->crtc_compute_clock(dcrtc, adj, &sclk);
  435. /* Ensure graphic fifo is enabled */
  436. armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
  437. armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
  438. if (interlaced ^ dcrtc->interlaced) {
  439. if (adj->flags & DRM_MODE_FLAG_INTERLACE)
  440. drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
  441. else
  442. drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
  443. dcrtc->interlaced = interlaced;
  444. }
  445. spin_lock_irqsave(&dcrtc->irq_lock, flags);
  446. /* Even interlaced/progressive frame */
  447. dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
  448. adj->crtc_htotal;
  449. dcrtc->v[1].spu_v_porch = tm << 16 | bm;
  450. val = adj->crtc_hsync_start;
  451. dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
  452. priv->variant->spu_adv_reg;
  453. if (interlaced) {
  454. /* Odd interlaced frame */
  455. dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
  456. (1 << 16);
  457. dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
  458. val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
  459. dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
  460. priv->variant->spu_adv_reg;
  461. } else {
  462. dcrtc->v[0] = dcrtc->v[1];
  463. }
  464. val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
  465. armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
  466. armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
  467. armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
  468. armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
  469. armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
  470. armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
  471. LCD_SPUT_V_H_TOTAL);
  472. if (priv->variant->has_spu_adv_reg) {
  473. armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
  474. ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
  475. ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
  476. }
  477. val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
  478. val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.fb)->fmt);
  479. val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.fb)->mod);
  480. if (drm_fb_to_armada_fb(dcrtc->crtc.fb)->fmt > CFG_420)
  481. val |= CFG_PALETTE_ENA;
  482. if (interlaced)
  483. val |= CFG_GRA_FTOGGLE;
  484. armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
  485. CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
  486. CFG_SWAPYU | CFG_YUV2RGB) |
  487. CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
  488. LCD_SPU_DMA_CTRL0);
  489. val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
  490. armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
  491. val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
  492. armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
  493. armada_reg_queue_end(regs, i);
  494. armada_drm_crtc_update_regs(dcrtc, regs);
  495. spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
  496. armada_drm_crtc_update(dcrtc);
  497. drm_vblank_post_modeset(crtc->dev, dcrtc->num);
  498. armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
  499. return 0;
  500. }
  501. /* The mode_config.mutex will be held for this call */
  502. static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  503. struct drm_framebuffer *old_fb)
  504. {
  505. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  506. struct armada_regs regs[4];
  507. unsigned i;
  508. i = armada_drm_crtc_calc_fb(crtc->fb, crtc->x, crtc->y, regs,
  509. dcrtc->interlaced);
  510. armada_reg_queue_end(regs, i);
  511. /* Wait for pending flips to complete */
  512. wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
  513. /* Take a reference to the new fb as we're using it */
  514. drm_framebuffer_reference(crtc->fb);
  515. /* Update the base in the CRTC */
  516. armada_drm_crtc_update_regs(dcrtc, regs);
  517. /* Drop our previously held reference */
  518. armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
  519. return 0;
  520. }
  521. static void armada_drm_crtc_load_lut(struct drm_crtc *crtc)
  522. {
  523. }
  524. /* The mode_config.mutex will be held for this call */
  525. static void armada_drm_crtc_disable(struct drm_crtc *crtc)
  526. {
  527. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  528. armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  529. armada_drm_crtc_finish_fb(dcrtc, crtc->fb, true);
  530. /* Power down most RAMs and FIFOs */
  531. writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
  532. CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
  533. CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
  534. }
  535. static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
  536. .dpms = armada_drm_crtc_dpms,
  537. .prepare = armada_drm_crtc_prepare,
  538. .commit = armada_drm_crtc_commit,
  539. .mode_fixup = armada_drm_crtc_mode_fixup,
  540. .mode_set = armada_drm_crtc_mode_set,
  541. .mode_set_base = armada_drm_crtc_mode_set_base,
  542. .load_lut = armada_drm_crtc_load_lut,
  543. .disable = armada_drm_crtc_disable,
  544. };
  545. static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
  546. unsigned stride, unsigned width, unsigned height)
  547. {
  548. uint32_t addr;
  549. unsigned y;
  550. addr = SRAM_HWC32_RAM1;
  551. for (y = 0; y < height; y++) {
  552. uint32_t *p = &pix[y * stride];
  553. unsigned x;
  554. for (x = 0; x < width; x++, p++) {
  555. uint32_t val = *p;
  556. val = (val & 0xff00ff00) |
  557. (val & 0x000000ff) << 16 |
  558. (val & 0x00ff0000) >> 16;
  559. writel_relaxed(val,
  560. base + LCD_SPU_SRAM_WRDAT);
  561. writel_relaxed(addr | SRAM_WRITE,
  562. base + LCD_SPU_SRAM_CTRL);
  563. addr += 1;
  564. if ((addr & 0x00ff) == 0)
  565. addr += 0xf00;
  566. if ((addr & 0x30ff) == 0)
  567. addr = SRAM_HWC32_RAM2;
  568. }
  569. }
  570. }
  571. static void armada_drm_crtc_cursor_tran(void __iomem *base)
  572. {
  573. unsigned addr;
  574. for (addr = 0; addr < 256; addr++) {
  575. /* write the default value */
  576. writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
  577. writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
  578. base + LCD_SPU_SRAM_CTRL);
  579. }
  580. }
  581. static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
  582. {
  583. uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
  584. uint32_t yoff, yscr, h = dcrtc->cursor_h;
  585. uint32_t para1;
  586. /*
  587. * Calculate the visible width and height of the cursor,
  588. * screen position, and the position in the cursor bitmap.
  589. */
  590. if (dcrtc->cursor_x < 0) {
  591. xoff = -dcrtc->cursor_x;
  592. xscr = 0;
  593. w -= min(xoff, w);
  594. } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
  595. xoff = 0;
  596. xscr = dcrtc->cursor_x;
  597. w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
  598. } else {
  599. xoff = 0;
  600. xscr = dcrtc->cursor_x;
  601. }
  602. if (dcrtc->cursor_y < 0) {
  603. yoff = -dcrtc->cursor_y;
  604. yscr = 0;
  605. h -= min(yoff, h);
  606. } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
  607. yoff = 0;
  608. yscr = dcrtc->cursor_y;
  609. h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
  610. } else {
  611. yoff = 0;
  612. yscr = dcrtc->cursor_y;
  613. }
  614. /* On interlaced modes, the vertical cursor size must be halved */
  615. s = dcrtc->cursor_w;
  616. if (dcrtc->interlaced) {
  617. s *= 2;
  618. yscr /= 2;
  619. h /= 2;
  620. }
  621. if (!dcrtc->cursor_obj || !h || !w) {
  622. spin_lock_irq(&dcrtc->irq_lock);
  623. armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
  624. dcrtc->cursor_update = false;
  625. armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
  626. spin_unlock_irq(&dcrtc->irq_lock);
  627. return 0;
  628. }
  629. para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
  630. armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
  631. dcrtc->base + LCD_SPU_SRAM_PARA1);
  632. /*
  633. * Initialize the transparency if the SRAM was powered down.
  634. * We must also reload the cursor data as well.
  635. */
  636. if (!(para1 & CFG_CSB_256x32)) {
  637. armada_drm_crtc_cursor_tran(dcrtc->base);
  638. reload = true;
  639. }
  640. if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
  641. spin_lock_irq(&dcrtc->irq_lock);
  642. armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
  643. dcrtc->cursor_update = false;
  644. armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
  645. spin_unlock_irq(&dcrtc->irq_lock);
  646. reload = true;
  647. }
  648. if (reload) {
  649. struct armada_gem_object *obj = dcrtc->cursor_obj;
  650. uint32_t *pix;
  651. /* Set the top-left corner of the cursor image */
  652. pix = obj->addr;
  653. pix += yoff * s + xoff;
  654. armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
  655. }
  656. /* Reload the cursor position, size and enable in the IRQ handler */
  657. spin_lock_irq(&dcrtc->irq_lock);
  658. dcrtc->cursor_hw_pos = yscr << 16 | xscr;
  659. dcrtc->cursor_hw_sz = h << 16 | w;
  660. dcrtc->cursor_update = true;
  661. armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
  662. spin_unlock_irq(&dcrtc->irq_lock);
  663. return 0;
  664. }
  665. static void cursor_update(void *data)
  666. {
  667. armada_drm_crtc_cursor_update(data, true);
  668. }
  669. static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
  670. struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
  671. {
  672. struct drm_device *dev = crtc->dev;
  673. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  674. struct armada_private *priv = crtc->dev->dev_private;
  675. struct armada_gem_object *obj = NULL;
  676. int ret;
  677. /* If no cursor support, replicate drm's return value */
  678. if (!priv->variant->has_spu_adv_reg)
  679. return -ENXIO;
  680. if (handle && w > 0 && h > 0) {
  681. /* maximum size is 64x32 or 32x64 */
  682. if (w > 64 || h > 64 || (w > 32 && h > 32))
  683. return -ENOMEM;
  684. obj = armada_gem_object_lookup(dev, file, handle);
  685. if (!obj)
  686. return -ENOENT;
  687. /* Must be a kernel-mapped object */
  688. if (!obj->addr) {
  689. drm_gem_object_unreference_unlocked(&obj->obj);
  690. return -EINVAL;
  691. }
  692. if (obj->obj.size < w * h * 4) {
  693. DRM_ERROR("buffer is too small\n");
  694. drm_gem_object_unreference_unlocked(&obj->obj);
  695. return -ENOMEM;
  696. }
  697. }
  698. mutex_lock(&dev->struct_mutex);
  699. if (dcrtc->cursor_obj) {
  700. dcrtc->cursor_obj->update = NULL;
  701. dcrtc->cursor_obj->update_data = NULL;
  702. drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
  703. }
  704. dcrtc->cursor_obj = obj;
  705. dcrtc->cursor_w = w;
  706. dcrtc->cursor_h = h;
  707. ret = armada_drm_crtc_cursor_update(dcrtc, true);
  708. if (obj) {
  709. obj->update_data = dcrtc;
  710. obj->update = cursor_update;
  711. }
  712. mutex_unlock(&dev->struct_mutex);
  713. return ret;
  714. }
  715. static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  716. {
  717. struct drm_device *dev = crtc->dev;
  718. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  719. struct armada_private *priv = crtc->dev->dev_private;
  720. int ret;
  721. /* If no cursor support, replicate drm's return value */
  722. if (!priv->variant->has_spu_adv_reg)
  723. return -EFAULT;
  724. mutex_lock(&dev->struct_mutex);
  725. dcrtc->cursor_x = x;
  726. dcrtc->cursor_y = y;
  727. ret = armada_drm_crtc_cursor_update(dcrtc, false);
  728. mutex_unlock(&dev->struct_mutex);
  729. return ret;
  730. }
  731. static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
  732. {
  733. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  734. struct armada_private *priv = crtc->dev->dev_private;
  735. if (dcrtc->cursor_obj)
  736. drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
  737. priv->dcrtc[dcrtc->num] = NULL;
  738. drm_crtc_cleanup(&dcrtc->crtc);
  739. if (!IS_ERR(dcrtc->clk))
  740. clk_disable_unprepare(dcrtc->clk);
  741. kfree(dcrtc);
  742. }
  743. /*
  744. * The mode_config lock is held here, to prevent races between this
  745. * and a mode_set.
  746. */
  747. static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
  748. struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
  749. {
  750. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  751. struct armada_frame_work *work;
  752. struct drm_device *dev = crtc->dev;
  753. unsigned long flags;
  754. unsigned i;
  755. int ret;
  756. /* We don't support changing the pixel format */
  757. if (fb->pixel_format != crtc->fb->pixel_format)
  758. return -EINVAL;
  759. work = kmalloc(sizeof(*work), GFP_KERNEL);
  760. if (!work)
  761. return -ENOMEM;
  762. work->event = event;
  763. work->old_fb = dcrtc->crtc.fb;
  764. i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
  765. dcrtc->interlaced);
  766. armada_reg_queue_end(work->regs, i);
  767. /*
  768. * Hold the old framebuffer for the work - DRM appears to drop our
  769. * reference to the old framebuffer in drm_mode_page_flip_ioctl().
  770. */
  771. drm_framebuffer_reference(work->old_fb);
  772. ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
  773. if (ret) {
  774. /*
  775. * Undo our reference above; DRM does not drop the reference
  776. * to this object on error, so that's okay.
  777. */
  778. drm_framebuffer_unreference(work->old_fb);
  779. kfree(work);
  780. return ret;
  781. }
  782. /*
  783. * Don't take a reference on the new framebuffer;
  784. * drm_mode_page_flip_ioctl() has already grabbed a reference and
  785. * will _not_ drop that reference on successful return from this
  786. * function. Simply mark this new framebuffer as the current one.
  787. */
  788. dcrtc->crtc.fb = fb;
  789. /*
  790. * Finally, if the display is blanked, we won't receive an
  791. * interrupt, so complete it now.
  792. */
  793. if (dpms_blanked(dcrtc->dpms)) {
  794. spin_lock_irqsave(&dev->event_lock, flags);
  795. if (dcrtc->frame_work)
  796. armada_drm_crtc_complete_frame_work(dcrtc);
  797. spin_unlock_irqrestore(&dev->event_lock, flags);
  798. }
  799. return 0;
  800. }
  801. static int
  802. armada_drm_crtc_set_property(struct drm_crtc *crtc,
  803. struct drm_property *property, uint64_t val)
  804. {
  805. struct armada_private *priv = crtc->dev->dev_private;
  806. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  807. bool update_csc = false;
  808. if (property == priv->csc_yuv_prop) {
  809. dcrtc->csc_yuv_mode = val;
  810. update_csc = true;
  811. } else if (property == priv->csc_rgb_prop) {
  812. dcrtc->csc_rgb_mode = val;
  813. update_csc = true;
  814. }
  815. if (update_csc) {
  816. uint32_t val;
  817. val = dcrtc->spu_iopad_ctrl |
  818. armada_drm_crtc_calculate_csc(dcrtc);
  819. writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
  820. }
  821. return 0;
  822. }
  823. static struct drm_crtc_funcs armada_crtc_funcs = {
  824. .cursor_set = armada_drm_crtc_cursor_set,
  825. .cursor_move = armada_drm_crtc_cursor_move,
  826. .destroy = armada_drm_crtc_destroy,
  827. .set_config = drm_crtc_helper_set_config,
  828. .page_flip = armada_drm_crtc_page_flip,
  829. .set_property = armada_drm_crtc_set_property,
  830. };
  831. static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
  832. { CSC_AUTO, "Auto" },
  833. { CSC_YUV_CCIR601, "CCIR601" },
  834. { CSC_YUV_CCIR709, "CCIR709" },
  835. };
  836. static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
  837. { CSC_AUTO, "Auto" },
  838. { CSC_RGB_COMPUTER, "Computer system" },
  839. { CSC_RGB_STUDIO, "Studio" },
  840. };
  841. static int armada_drm_crtc_create_properties(struct drm_device *dev)
  842. {
  843. struct armada_private *priv = dev->dev_private;
  844. if (priv->csc_yuv_prop)
  845. return 0;
  846. priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
  847. "CSC_YUV", armada_drm_csc_yuv_enum_list,
  848. ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
  849. priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
  850. "CSC_RGB", armada_drm_csc_rgb_enum_list,
  851. ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
  852. if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
  853. return -ENOMEM;
  854. return 0;
  855. }
  856. int armada_drm_crtc_create(struct drm_device *dev, unsigned num,
  857. struct resource *res)
  858. {
  859. struct armada_private *priv = dev->dev_private;
  860. struct armada_crtc *dcrtc;
  861. void __iomem *base;
  862. int ret;
  863. ret = armada_drm_crtc_create_properties(dev);
  864. if (ret)
  865. return ret;
  866. base = devm_request_and_ioremap(dev->dev, res);
  867. if (!base) {
  868. DRM_ERROR("failed to ioremap register\n");
  869. return -ENOMEM;
  870. }
  871. dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
  872. if (!dcrtc) {
  873. DRM_ERROR("failed to allocate Armada crtc\n");
  874. return -ENOMEM;
  875. }
  876. dcrtc->base = base;
  877. dcrtc->num = num;
  878. dcrtc->clk = ERR_PTR(-EINVAL);
  879. dcrtc->csc_yuv_mode = CSC_AUTO;
  880. dcrtc->csc_rgb_mode = CSC_AUTO;
  881. dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
  882. dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
  883. spin_lock_init(&dcrtc->irq_lock);
  884. dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
  885. INIT_LIST_HEAD(&dcrtc->vbl_list);
  886. init_waitqueue_head(&dcrtc->frame_wait);
  887. /* Initialize some registers which we don't otherwise set */
  888. writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
  889. writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
  890. writel_relaxed(dcrtc->spu_iopad_ctrl,
  891. dcrtc->base + LCD_SPU_IOPAD_CONTROL);
  892. writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
  893. writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
  894. CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
  895. CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
  896. writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
  897. writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
  898. if (priv->variant->crtc_init) {
  899. ret = priv->variant->crtc_init(dcrtc);
  900. if (ret) {
  901. kfree(dcrtc);
  902. return ret;
  903. }
  904. }
  905. /* Ensure AXI pipeline is enabled */
  906. armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
  907. priv->dcrtc[dcrtc->num] = dcrtc;
  908. drm_crtc_init(dev, &dcrtc->crtc, &armada_crtc_funcs);
  909. drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
  910. drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
  911. dcrtc->csc_yuv_mode);
  912. drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
  913. dcrtc->csc_rgb_mode);
  914. return armada_overlay_plane_create(dev, 1 << dcrtc->num);
  915. }