atmel_usba_udc.c 48 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/device.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/list.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/gadget.h>
  21. #include <linux/delay.h>
  22. #include <asm/gpio.h>
  23. #include <asm/arch/board.h>
  24. #include "atmel_usba_udc.h"
  25. static struct usba_udc the_udc;
  26. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  27. #include <linux/debugfs.h>
  28. #include <linux/uaccess.h>
  29. static int queue_dbg_open(struct inode *inode, struct file *file)
  30. {
  31. struct usba_ep *ep = inode->i_private;
  32. struct usba_request *req, *req_copy;
  33. struct list_head *queue_data;
  34. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  35. if (!queue_data)
  36. return -ENOMEM;
  37. INIT_LIST_HEAD(queue_data);
  38. spin_lock_irq(&ep->udc->lock);
  39. list_for_each_entry(req, &ep->queue, queue) {
  40. req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
  41. if (!req_copy)
  42. goto fail;
  43. memcpy(req_copy, req, sizeof(*req_copy));
  44. list_add_tail(&req_copy->queue, queue_data);
  45. }
  46. spin_unlock_irq(&ep->udc->lock);
  47. file->private_data = queue_data;
  48. return 0;
  49. fail:
  50. spin_unlock_irq(&ep->udc->lock);
  51. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  52. list_del(&req->queue);
  53. kfree(req);
  54. }
  55. kfree(queue_data);
  56. return -ENOMEM;
  57. }
  58. /*
  59. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  60. *
  61. * b: buffer address
  62. * l: buffer length
  63. * I/i: interrupt/no interrupt
  64. * Z/z: zero/no zero
  65. * S/s: short ok/short not ok
  66. * s: status
  67. * n: nr_packets
  68. * F/f: submitted/not submitted to FIFO
  69. * D/d: using/not using DMA
  70. * L/l: last transaction/not last transaction
  71. */
  72. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  73. size_t nbytes, loff_t *ppos)
  74. {
  75. struct list_head *queue = file->private_data;
  76. struct usba_request *req, *tmp_req;
  77. size_t len, remaining, actual = 0;
  78. char tmpbuf[38];
  79. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  80. return -EFAULT;
  81. mutex_lock(&file->f_dentry->d_inode->i_mutex);
  82. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  83. len = snprintf(tmpbuf, sizeof(tmpbuf),
  84. "%8p %08x %c%c%c %5d %c%c%c\n",
  85. req->req.buf, req->req.length,
  86. req->req.no_interrupt ? 'i' : 'I',
  87. req->req.zero ? 'Z' : 'z',
  88. req->req.short_not_ok ? 's' : 'S',
  89. req->req.status,
  90. req->submitted ? 'F' : 'f',
  91. req->using_dma ? 'D' : 'd',
  92. req->last_transaction ? 'L' : 'l');
  93. len = min(len, sizeof(tmpbuf));
  94. if (len > nbytes)
  95. break;
  96. list_del(&req->queue);
  97. kfree(req);
  98. remaining = __copy_to_user(buf, tmpbuf, len);
  99. actual += len - remaining;
  100. if (remaining)
  101. break;
  102. nbytes -= len;
  103. buf += len;
  104. }
  105. mutex_unlock(&file->f_dentry->d_inode->i_mutex);
  106. return actual;
  107. }
  108. static int queue_dbg_release(struct inode *inode, struct file *file)
  109. {
  110. struct list_head *queue_data = file->private_data;
  111. struct usba_request *req, *tmp_req;
  112. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  113. list_del(&req->queue);
  114. kfree(req);
  115. }
  116. kfree(queue_data);
  117. return 0;
  118. }
  119. static int regs_dbg_open(struct inode *inode, struct file *file)
  120. {
  121. struct usba_udc *udc;
  122. unsigned int i;
  123. u32 *data;
  124. int ret = -ENOMEM;
  125. mutex_lock(&inode->i_mutex);
  126. udc = inode->i_private;
  127. data = kmalloc(inode->i_size, GFP_KERNEL);
  128. if (!data)
  129. goto out;
  130. spin_lock_irq(&udc->lock);
  131. for (i = 0; i < inode->i_size / 4; i++)
  132. data[i] = __raw_readl(udc->regs + i * 4);
  133. spin_unlock_irq(&udc->lock);
  134. file->private_data = data;
  135. ret = 0;
  136. out:
  137. mutex_unlock(&inode->i_mutex);
  138. return ret;
  139. }
  140. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  141. size_t nbytes, loff_t *ppos)
  142. {
  143. struct inode *inode = file->f_dentry->d_inode;
  144. int ret;
  145. mutex_lock(&inode->i_mutex);
  146. ret = simple_read_from_buffer(buf, nbytes, ppos,
  147. file->private_data,
  148. file->f_dentry->d_inode->i_size);
  149. mutex_unlock(&inode->i_mutex);
  150. return ret;
  151. }
  152. static int regs_dbg_release(struct inode *inode, struct file *file)
  153. {
  154. kfree(file->private_data);
  155. return 0;
  156. }
  157. const struct file_operations queue_dbg_fops = {
  158. .owner = THIS_MODULE,
  159. .open = queue_dbg_open,
  160. .llseek = no_llseek,
  161. .read = queue_dbg_read,
  162. .release = queue_dbg_release,
  163. };
  164. const struct file_operations regs_dbg_fops = {
  165. .owner = THIS_MODULE,
  166. .open = regs_dbg_open,
  167. .llseek = generic_file_llseek,
  168. .read = regs_dbg_read,
  169. .release = regs_dbg_release,
  170. };
  171. static void usba_ep_init_debugfs(struct usba_udc *udc,
  172. struct usba_ep *ep)
  173. {
  174. struct dentry *ep_root;
  175. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  176. if (!ep_root)
  177. goto err_root;
  178. ep->debugfs_dir = ep_root;
  179. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  180. ep, &queue_dbg_fops);
  181. if (!ep->debugfs_queue)
  182. goto err_queue;
  183. if (ep->can_dma) {
  184. ep->debugfs_dma_status
  185. = debugfs_create_u32("dma_status", 0400, ep_root,
  186. &ep->last_dma_status);
  187. if (!ep->debugfs_dma_status)
  188. goto err_dma_status;
  189. }
  190. if (ep_is_control(ep)) {
  191. ep->debugfs_state
  192. = debugfs_create_u32("state", 0400, ep_root,
  193. &ep->state);
  194. if (!ep->debugfs_state)
  195. goto err_state;
  196. }
  197. return;
  198. err_state:
  199. if (ep->can_dma)
  200. debugfs_remove(ep->debugfs_dma_status);
  201. err_dma_status:
  202. debugfs_remove(ep->debugfs_queue);
  203. err_queue:
  204. debugfs_remove(ep_root);
  205. err_root:
  206. dev_err(&ep->udc->pdev->dev,
  207. "failed to create debugfs directory for %s\n", ep->ep.name);
  208. }
  209. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  210. {
  211. debugfs_remove(ep->debugfs_queue);
  212. debugfs_remove(ep->debugfs_dma_status);
  213. debugfs_remove(ep->debugfs_state);
  214. debugfs_remove(ep->debugfs_dir);
  215. ep->debugfs_dma_status = NULL;
  216. ep->debugfs_dir = NULL;
  217. }
  218. static void usba_init_debugfs(struct usba_udc *udc)
  219. {
  220. struct dentry *root, *regs;
  221. struct resource *regs_resource;
  222. root = debugfs_create_dir(udc->gadget.name, NULL);
  223. if (IS_ERR(root) || !root)
  224. goto err_root;
  225. udc->debugfs_root = root;
  226. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  227. if (!regs)
  228. goto err_regs;
  229. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  230. CTRL_IOMEM_ID);
  231. regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
  232. udc->debugfs_regs = regs;
  233. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  234. return;
  235. err_regs:
  236. debugfs_remove(root);
  237. err_root:
  238. udc->debugfs_root = NULL;
  239. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  240. }
  241. static void usba_cleanup_debugfs(struct usba_udc *udc)
  242. {
  243. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  244. debugfs_remove(udc->debugfs_regs);
  245. debugfs_remove(udc->debugfs_root);
  246. udc->debugfs_regs = NULL;
  247. udc->debugfs_root = NULL;
  248. }
  249. #else
  250. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  251. struct usba_ep *ep)
  252. {
  253. }
  254. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  255. {
  256. }
  257. static inline void usba_init_debugfs(struct usba_udc *udc)
  258. {
  259. }
  260. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  261. {
  262. }
  263. #endif
  264. static int vbus_is_present(struct usba_udc *udc)
  265. {
  266. if (udc->vbus_pin != -1)
  267. return gpio_get_value(udc->vbus_pin);
  268. /* No Vbus detection: Assume always present */
  269. return 1;
  270. }
  271. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  272. {
  273. unsigned int transaction_len;
  274. transaction_len = req->req.length - req->req.actual;
  275. req->last_transaction = 1;
  276. if (transaction_len > ep->ep.maxpacket) {
  277. transaction_len = ep->ep.maxpacket;
  278. req->last_transaction = 0;
  279. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  280. req->last_transaction = 0;
  281. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  282. ep->ep.name, req, transaction_len,
  283. req->last_transaction ? ", done" : "");
  284. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  285. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  286. req->req.actual += transaction_len;
  287. }
  288. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  289. {
  290. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  291. ep->ep.name, req, req->req.length);
  292. req->req.actual = 0;
  293. req->submitted = 1;
  294. if (req->using_dma) {
  295. if (req->req.length == 0) {
  296. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  297. return;
  298. }
  299. if (req->req.zero)
  300. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  301. else
  302. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  303. usba_dma_writel(ep, ADDRESS, req->req.dma);
  304. usba_dma_writel(ep, CONTROL, req->ctrl);
  305. } else {
  306. next_fifo_transaction(ep, req);
  307. if (req->last_transaction) {
  308. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  309. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  310. } else {
  311. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  312. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  313. }
  314. }
  315. }
  316. static void submit_next_request(struct usba_ep *ep)
  317. {
  318. struct usba_request *req;
  319. if (list_empty(&ep->queue)) {
  320. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  321. return;
  322. }
  323. req = list_entry(ep->queue.next, struct usba_request, queue);
  324. if (!req->submitted)
  325. submit_request(ep, req);
  326. }
  327. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  328. {
  329. ep->state = STATUS_STAGE_IN;
  330. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  331. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  332. }
  333. static void receive_data(struct usba_ep *ep)
  334. {
  335. struct usba_udc *udc = ep->udc;
  336. struct usba_request *req;
  337. unsigned long status;
  338. unsigned int bytecount, nr_busy;
  339. int is_complete = 0;
  340. status = usba_ep_readl(ep, STA);
  341. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  342. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  343. while (nr_busy > 0) {
  344. if (list_empty(&ep->queue)) {
  345. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  346. break;
  347. }
  348. req = list_entry(ep->queue.next,
  349. struct usba_request, queue);
  350. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  351. if (status & (1 << 31))
  352. is_complete = 1;
  353. if (req->req.actual + bytecount >= req->req.length) {
  354. is_complete = 1;
  355. bytecount = req->req.length - req->req.actual;
  356. }
  357. memcpy_fromio(req->req.buf + req->req.actual,
  358. ep->fifo, bytecount);
  359. req->req.actual += bytecount;
  360. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  361. if (is_complete) {
  362. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  363. req->req.status = 0;
  364. list_del_init(&req->queue);
  365. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  366. spin_unlock(&udc->lock);
  367. req->req.complete(&ep->ep, &req->req);
  368. spin_lock(&udc->lock);
  369. }
  370. status = usba_ep_readl(ep, STA);
  371. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  372. if (is_complete && ep_is_control(ep)) {
  373. send_status(udc, ep);
  374. break;
  375. }
  376. }
  377. }
  378. static void
  379. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  380. {
  381. struct usba_udc *udc = ep->udc;
  382. WARN_ON(!list_empty(&req->queue));
  383. if (req->req.status == -EINPROGRESS)
  384. req->req.status = status;
  385. if (req->mapped) {
  386. dma_unmap_single(
  387. &udc->pdev->dev, req->req.dma, req->req.length,
  388. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  389. req->req.dma = DMA_ADDR_INVALID;
  390. req->mapped = 0;
  391. }
  392. DBG(DBG_GADGET | DBG_REQ,
  393. "%s: req %p complete: status %d, actual %u\n",
  394. ep->ep.name, req, req->req.status, req->req.actual);
  395. spin_unlock(&udc->lock);
  396. req->req.complete(&ep->ep, &req->req);
  397. spin_lock(&udc->lock);
  398. }
  399. static void
  400. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  401. {
  402. struct usba_request *req, *tmp_req;
  403. list_for_each_entry_safe(req, tmp_req, list, queue) {
  404. list_del_init(&req->queue);
  405. request_complete(ep, req, status);
  406. }
  407. }
  408. static int
  409. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  410. {
  411. struct usba_ep *ep = to_usba_ep(_ep);
  412. struct usba_udc *udc = ep->udc;
  413. unsigned long flags, ept_cfg, maxpacket;
  414. unsigned int nr_trans;
  415. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  416. maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
  417. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  418. || ep->index == 0
  419. || desc->bDescriptorType != USB_DT_ENDPOINT
  420. || maxpacket == 0
  421. || maxpacket > ep->fifo_size) {
  422. DBG(DBG_ERR, "ep_enable: Invalid argument");
  423. return -EINVAL;
  424. }
  425. ep->is_isoc = 0;
  426. ep->is_in = 0;
  427. if (maxpacket <= 8)
  428. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  429. else
  430. /* LSB is bit 1, not 0 */
  431. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  432. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  433. ep->ep.name, ept_cfg, maxpacket);
  434. if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  435. ep->is_in = 1;
  436. ept_cfg |= USBA_EPT_DIR_IN;
  437. }
  438. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  439. case USB_ENDPOINT_XFER_CONTROL:
  440. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  441. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  442. break;
  443. case USB_ENDPOINT_XFER_ISOC:
  444. if (!ep->can_isoc) {
  445. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  446. ep->ep.name);
  447. return -EINVAL;
  448. }
  449. /*
  450. * Bits 11:12 specify number of _additional_
  451. * transactions per microframe.
  452. */
  453. nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
  454. if (nr_trans > 3)
  455. return -EINVAL;
  456. ep->is_isoc = 1;
  457. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  458. /*
  459. * Do triple-buffering on high-bandwidth iso endpoints.
  460. */
  461. if (nr_trans > 1 && ep->nr_banks == 3)
  462. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  463. else
  464. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  465. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  466. break;
  467. case USB_ENDPOINT_XFER_BULK:
  468. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  469. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  470. break;
  471. case USB_ENDPOINT_XFER_INT:
  472. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  473. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  474. break;
  475. }
  476. spin_lock_irqsave(&ep->udc->lock, flags);
  477. if (ep->desc) {
  478. spin_unlock_irqrestore(&ep->udc->lock, flags);
  479. DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
  480. return -EBUSY;
  481. }
  482. ep->desc = desc;
  483. ep->ep.maxpacket = maxpacket;
  484. usba_ep_writel(ep, CFG, ept_cfg);
  485. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  486. if (ep->can_dma) {
  487. u32 ctrl;
  488. usba_writel(udc, INT_ENB,
  489. (usba_readl(udc, INT_ENB)
  490. | USBA_BF(EPT_INT, 1 << ep->index)
  491. | USBA_BF(DMA_INT, 1 << ep->index)));
  492. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  493. usba_ep_writel(ep, CTL_ENB, ctrl);
  494. } else {
  495. usba_writel(udc, INT_ENB,
  496. (usba_readl(udc, INT_ENB)
  497. | USBA_BF(EPT_INT, 1 << ep->index)));
  498. }
  499. spin_unlock_irqrestore(&udc->lock, flags);
  500. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  501. (unsigned long)usba_ep_readl(ep, CFG));
  502. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  503. (unsigned long)usba_readl(udc, INT_ENB));
  504. return 0;
  505. }
  506. static int usba_ep_disable(struct usb_ep *_ep)
  507. {
  508. struct usba_ep *ep = to_usba_ep(_ep);
  509. struct usba_udc *udc = ep->udc;
  510. LIST_HEAD(req_list);
  511. unsigned long flags;
  512. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  513. spin_lock_irqsave(&udc->lock, flags);
  514. if (!ep->desc) {
  515. spin_unlock_irqrestore(&udc->lock, flags);
  516. DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
  517. return -EINVAL;
  518. }
  519. ep->desc = NULL;
  520. list_splice_init(&ep->queue, &req_list);
  521. if (ep->can_dma) {
  522. usba_dma_writel(ep, CONTROL, 0);
  523. usba_dma_writel(ep, ADDRESS, 0);
  524. usba_dma_readl(ep, STATUS);
  525. }
  526. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  527. usba_writel(udc, INT_ENB,
  528. usba_readl(udc, INT_ENB)
  529. & ~USBA_BF(EPT_INT, 1 << ep->index));
  530. request_complete_list(ep, &req_list, -ESHUTDOWN);
  531. spin_unlock_irqrestore(&udc->lock, flags);
  532. return 0;
  533. }
  534. static struct usb_request *
  535. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  536. {
  537. struct usba_request *req;
  538. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  539. req = kzalloc(sizeof(*req), gfp_flags);
  540. if (!req)
  541. return NULL;
  542. INIT_LIST_HEAD(&req->queue);
  543. req->req.dma = DMA_ADDR_INVALID;
  544. return &req->req;
  545. }
  546. static void
  547. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  548. {
  549. struct usba_request *req = to_usba_req(_req);
  550. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  551. kfree(req);
  552. }
  553. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  554. struct usba_request *req, gfp_t gfp_flags)
  555. {
  556. unsigned long flags;
  557. int ret;
  558. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  559. ep->ep.name, req->req.length, req->req.dma,
  560. req->req.zero ? 'Z' : 'z',
  561. req->req.short_not_ok ? 'S' : 's',
  562. req->req.no_interrupt ? 'I' : 'i');
  563. if (req->req.length > 0x10000) {
  564. /* Lengths from 0 to 65536 (inclusive) are supported */
  565. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  566. return -EINVAL;
  567. }
  568. req->using_dma = 1;
  569. if (req->req.dma == DMA_ADDR_INVALID) {
  570. req->req.dma = dma_map_single(
  571. &udc->pdev->dev, req->req.buf, req->req.length,
  572. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  573. req->mapped = 1;
  574. } else {
  575. dma_sync_single_for_device(
  576. &udc->pdev->dev, req->req.dma, req->req.length,
  577. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  578. req->mapped = 0;
  579. }
  580. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  581. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  582. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  583. if (ep->is_in)
  584. req->ctrl |= USBA_DMA_END_BUF_EN;
  585. /*
  586. * Add this request to the queue and submit for DMA if
  587. * possible. Check if we're still alive first -- we may have
  588. * received a reset since last time we checked.
  589. */
  590. ret = -ESHUTDOWN;
  591. spin_lock_irqsave(&udc->lock, flags);
  592. if (ep->desc) {
  593. if (list_empty(&ep->queue))
  594. submit_request(ep, req);
  595. list_add_tail(&req->queue, &ep->queue);
  596. ret = 0;
  597. }
  598. spin_unlock_irqrestore(&udc->lock, flags);
  599. return ret;
  600. }
  601. static int
  602. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  603. {
  604. struct usba_request *req = to_usba_req(_req);
  605. struct usba_ep *ep = to_usba_ep(_ep);
  606. struct usba_udc *udc = ep->udc;
  607. unsigned long flags;
  608. int ret;
  609. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  610. ep->ep.name, req, _req->length);
  611. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
  612. return -ESHUTDOWN;
  613. req->submitted = 0;
  614. req->using_dma = 0;
  615. req->last_transaction = 0;
  616. _req->status = -EINPROGRESS;
  617. _req->actual = 0;
  618. if (ep->can_dma)
  619. return queue_dma(udc, ep, req, gfp_flags);
  620. /* May have received a reset since last time we checked */
  621. ret = -ESHUTDOWN;
  622. spin_lock_irqsave(&udc->lock, flags);
  623. if (ep->desc) {
  624. list_add_tail(&req->queue, &ep->queue);
  625. if (ep->is_in || (ep_is_control(ep)
  626. && (ep->state == DATA_STAGE_IN
  627. || ep->state == STATUS_STAGE_IN)))
  628. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  629. else
  630. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  631. ret = 0;
  632. }
  633. spin_unlock_irqrestore(&udc->lock, flags);
  634. return ret;
  635. }
  636. static void
  637. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  638. {
  639. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  640. }
  641. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  642. {
  643. unsigned int timeout;
  644. u32 status;
  645. /*
  646. * Stop the DMA controller. When writing both CH_EN
  647. * and LINK to 0, the other bits are not affected.
  648. */
  649. usba_dma_writel(ep, CONTROL, 0);
  650. /* Wait for the FIFO to empty */
  651. for (timeout = 40; timeout; --timeout) {
  652. status = usba_dma_readl(ep, STATUS);
  653. if (!(status & USBA_DMA_CH_EN))
  654. break;
  655. udelay(1);
  656. }
  657. if (pstatus)
  658. *pstatus = status;
  659. if (timeout == 0) {
  660. dev_err(&ep->udc->pdev->dev,
  661. "%s: timed out waiting for DMA FIFO to empty\n",
  662. ep->ep.name);
  663. return -ETIMEDOUT;
  664. }
  665. return 0;
  666. }
  667. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  668. {
  669. struct usba_ep *ep = to_usba_ep(_ep);
  670. struct usba_udc *udc = ep->udc;
  671. struct usba_request *req = to_usba_req(_req);
  672. unsigned long flags;
  673. u32 status;
  674. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  675. ep->ep.name, req);
  676. spin_lock_irqsave(&udc->lock, flags);
  677. if (req->using_dma) {
  678. /*
  679. * If this request is currently being transferred,
  680. * stop the DMA controller and reset the FIFO.
  681. */
  682. if (ep->queue.next == &req->queue) {
  683. status = usba_dma_readl(ep, STATUS);
  684. if (status & USBA_DMA_CH_EN)
  685. stop_dma(ep, &status);
  686. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  687. ep->last_dma_status = status;
  688. #endif
  689. usba_writel(udc, EPT_RST, 1 << ep->index);
  690. usba_update_req(ep, req, status);
  691. }
  692. }
  693. /*
  694. * Errors should stop the queue from advancing until the
  695. * completion function returns.
  696. */
  697. list_del_init(&req->queue);
  698. request_complete(ep, req, -ECONNRESET);
  699. /* Process the next request if any */
  700. submit_next_request(ep);
  701. spin_unlock_irqrestore(&udc->lock, flags);
  702. return 0;
  703. }
  704. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  705. {
  706. struct usba_ep *ep = to_usba_ep(_ep);
  707. struct usba_udc *udc = ep->udc;
  708. unsigned long flags;
  709. int ret = 0;
  710. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  711. value ? "set" : "clear");
  712. if (!ep->desc) {
  713. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  714. ep->ep.name);
  715. return -ENODEV;
  716. }
  717. if (ep->is_isoc) {
  718. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  719. ep->ep.name);
  720. return -ENOTTY;
  721. }
  722. spin_lock_irqsave(&udc->lock, flags);
  723. /*
  724. * We can't halt IN endpoints while there are still data to be
  725. * transferred
  726. */
  727. if (!list_empty(&ep->queue)
  728. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  729. & USBA_BF(BUSY_BANKS, -1L))))) {
  730. ret = -EAGAIN;
  731. } else {
  732. if (value)
  733. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  734. else
  735. usba_ep_writel(ep, CLR_STA,
  736. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  737. usba_ep_readl(ep, STA);
  738. }
  739. spin_unlock_irqrestore(&udc->lock, flags);
  740. return ret;
  741. }
  742. static int usba_ep_fifo_status(struct usb_ep *_ep)
  743. {
  744. struct usba_ep *ep = to_usba_ep(_ep);
  745. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  746. }
  747. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  748. {
  749. struct usba_ep *ep = to_usba_ep(_ep);
  750. struct usba_udc *udc = ep->udc;
  751. usba_writel(udc, EPT_RST, 1 << ep->index);
  752. }
  753. static const struct usb_ep_ops usba_ep_ops = {
  754. .enable = usba_ep_enable,
  755. .disable = usba_ep_disable,
  756. .alloc_request = usba_ep_alloc_request,
  757. .free_request = usba_ep_free_request,
  758. .queue = usba_ep_queue,
  759. .dequeue = usba_ep_dequeue,
  760. .set_halt = usba_ep_set_halt,
  761. .fifo_status = usba_ep_fifo_status,
  762. .fifo_flush = usba_ep_fifo_flush,
  763. };
  764. static int usba_udc_get_frame(struct usb_gadget *gadget)
  765. {
  766. struct usba_udc *udc = to_usba_udc(gadget);
  767. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  768. }
  769. static int usba_udc_wakeup(struct usb_gadget *gadget)
  770. {
  771. struct usba_udc *udc = to_usba_udc(gadget);
  772. unsigned long flags;
  773. u32 ctrl;
  774. int ret = -EINVAL;
  775. spin_lock_irqsave(&udc->lock, flags);
  776. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  777. ctrl = usba_readl(udc, CTRL);
  778. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  779. ret = 0;
  780. }
  781. spin_unlock_irqrestore(&udc->lock, flags);
  782. return ret;
  783. }
  784. static int
  785. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  786. {
  787. struct usba_udc *udc = to_usba_udc(gadget);
  788. unsigned long flags;
  789. spin_lock_irqsave(&udc->lock, flags);
  790. if (is_selfpowered)
  791. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  792. else
  793. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  794. spin_unlock_irqrestore(&udc->lock, flags);
  795. return 0;
  796. }
  797. static const struct usb_gadget_ops usba_udc_ops = {
  798. .get_frame = usba_udc_get_frame,
  799. .wakeup = usba_udc_wakeup,
  800. .set_selfpowered = usba_udc_set_selfpowered,
  801. };
  802. #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
  803. { \
  804. .ep = { \
  805. .ops = &usba_ep_ops, \
  806. .name = nam, \
  807. .maxpacket = maxpkt, \
  808. }, \
  809. .udc = &the_udc, \
  810. .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
  811. .fifo_size = maxpkt, \
  812. .nr_banks = maxbk, \
  813. .index = idx, \
  814. .can_dma = dma, \
  815. .can_isoc = isoc, \
  816. }
  817. static struct usba_ep usba_ep[] = {
  818. EP("ep0", 0, 64, 1, 0, 0),
  819. EP("ep1", 1, 512, 2, 1, 1),
  820. EP("ep2", 2, 512, 2, 1, 1),
  821. EP("ep3-int", 3, 64, 3, 1, 0),
  822. EP("ep4-int", 4, 64, 3, 1, 0),
  823. EP("ep5", 5, 1024, 3, 1, 1),
  824. EP("ep6", 6, 1024, 3, 1, 1),
  825. };
  826. #undef EP
  827. static struct usb_endpoint_descriptor usba_ep0_desc = {
  828. .bLength = USB_DT_ENDPOINT_SIZE,
  829. .bDescriptorType = USB_DT_ENDPOINT,
  830. .bEndpointAddress = 0,
  831. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  832. .wMaxPacketSize = __constant_cpu_to_le16(64),
  833. /* FIXME: I have no idea what to put here */
  834. .bInterval = 1,
  835. };
  836. static void nop_release(struct device *dev)
  837. {
  838. }
  839. static struct usba_udc the_udc = {
  840. .gadget = {
  841. .ops = &usba_udc_ops,
  842. .ep0 = &usba_ep[0].ep,
  843. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  844. .is_dualspeed = 1,
  845. .name = "atmel_usba_udc",
  846. .dev = {
  847. .bus_id = "gadget",
  848. .release = nop_release,
  849. },
  850. },
  851. .lock = SPIN_LOCK_UNLOCKED,
  852. };
  853. /*
  854. * Called with interrupts disabled and udc->lock held.
  855. */
  856. static void reset_all_endpoints(struct usba_udc *udc)
  857. {
  858. struct usba_ep *ep;
  859. struct usba_request *req, *tmp_req;
  860. usba_writel(udc, EPT_RST, ~0UL);
  861. ep = to_usba_ep(udc->gadget.ep0);
  862. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  863. list_del_init(&req->queue);
  864. request_complete(ep, req, -ECONNRESET);
  865. }
  866. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  867. if (ep->desc) {
  868. spin_unlock(&udc->lock);
  869. usba_ep_disable(&ep->ep);
  870. spin_lock(&udc->lock);
  871. }
  872. }
  873. }
  874. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  875. {
  876. struct usba_ep *ep;
  877. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  878. return to_usba_ep(udc->gadget.ep0);
  879. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  880. u8 bEndpointAddress;
  881. if (!ep->desc)
  882. continue;
  883. bEndpointAddress = ep->desc->bEndpointAddress;
  884. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  885. continue;
  886. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  887. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  888. return ep;
  889. }
  890. return NULL;
  891. }
  892. /* Called with interrupts disabled and udc->lock held */
  893. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  894. {
  895. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  896. ep->state = WAIT_FOR_SETUP;
  897. }
  898. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  899. {
  900. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  901. return 1;
  902. return 0;
  903. }
  904. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  905. {
  906. u32 regval;
  907. DBG(DBG_BUS, "setting address %u...\n", addr);
  908. regval = usba_readl(udc, CTRL);
  909. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  910. usba_writel(udc, CTRL, regval);
  911. }
  912. static int do_test_mode(struct usba_udc *udc)
  913. {
  914. static const char test_packet_buffer[] = {
  915. /* JKJKJKJK * 9 */
  916. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  917. /* JJKKJJKK * 8 */
  918. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  919. /* JJKKJJKK * 8 */
  920. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  921. /* JJJJJJJKKKKKKK * 8 */
  922. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  923. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  924. /* JJJJJJJK * 8 */
  925. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  926. /* {JKKKKKKK * 10}, JK */
  927. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  928. };
  929. struct usba_ep *ep;
  930. struct device *dev = &udc->pdev->dev;
  931. int test_mode;
  932. test_mode = udc->test_mode;
  933. /* Start from a clean slate */
  934. reset_all_endpoints(udc);
  935. switch (test_mode) {
  936. case 0x0100:
  937. /* Test_J */
  938. usba_writel(udc, TST, USBA_TST_J_MODE);
  939. dev_info(dev, "Entering Test_J mode...\n");
  940. break;
  941. case 0x0200:
  942. /* Test_K */
  943. usba_writel(udc, TST, USBA_TST_K_MODE);
  944. dev_info(dev, "Entering Test_K mode...\n");
  945. break;
  946. case 0x0300:
  947. /*
  948. * Test_SE0_NAK: Force high-speed mode and set up ep0
  949. * for Bulk IN transfers
  950. */
  951. ep = &usba_ep[0];
  952. usba_writel(udc, TST,
  953. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  954. usba_ep_writel(ep, CFG,
  955. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  956. | USBA_EPT_DIR_IN
  957. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  958. | USBA_BF(BK_NUMBER, 1));
  959. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  960. set_protocol_stall(udc, ep);
  961. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  962. } else {
  963. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  964. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  965. }
  966. break;
  967. case 0x0400:
  968. /* Test_Packet */
  969. ep = &usba_ep[0];
  970. usba_ep_writel(ep, CFG,
  971. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  972. | USBA_EPT_DIR_IN
  973. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  974. | USBA_BF(BK_NUMBER, 1));
  975. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  976. set_protocol_stall(udc, ep);
  977. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  978. } else {
  979. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  980. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  981. memcpy_toio(ep->fifo, test_packet_buffer,
  982. sizeof(test_packet_buffer));
  983. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  984. dev_info(dev, "Entering Test_Packet mode...\n");
  985. }
  986. break;
  987. default:
  988. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  989. return -EINVAL;
  990. }
  991. return 0;
  992. }
  993. /* Avoid overly long expressions */
  994. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  995. {
  996. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  997. return true;
  998. return false;
  999. }
  1000. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1001. {
  1002. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
  1003. return true;
  1004. return false;
  1005. }
  1006. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1007. {
  1008. if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
  1009. return true;
  1010. return false;
  1011. }
  1012. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1013. struct usb_ctrlrequest *crq)
  1014. {
  1015. int retval = 0;;
  1016. switch (crq->bRequest) {
  1017. case USB_REQ_GET_STATUS: {
  1018. u16 status;
  1019. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1020. status = cpu_to_le16(udc->devstatus);
  1021. } else if (crq->bRequestType
  1022. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1023. status = __constant_cpu_to_le16(0);
  1024. } else if (crq->bRequestType
  1025. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1026. struct usba_ep *target;
  1027. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1028. if (!target)
  1029. goto stall;
  1030. status = 0;
  1031. if (is_stalled(udc, target))
  1032. status |= __constant_cpu_to_le16(1);
  1033. } else
  1034. goto delegate;
  1035. /* Write directly to the FIFO. No queueing is done. */
  1036. if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
  1037. goto stall;
  1038. ep->state = DATA_STAGE_IN;
  1039. __raw_writew(status, ep->fifo);
  1040. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1041. break;
  1042. }
  1043. case USB_REQ_CLEAR_FEATURE: {
  1044. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1045. if (feature_is_dev_remote_wakeup(crq))
  1046. udc->devstatus
  1047. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1048. else
  1049. /* Can't CLEAR_FEATURE TEST_MODE */
  1050. goto stall;
  1051. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1052. struct usba_ep *target;
  1053. if (crq->wLength != __constant_cpu_to_le16(0)
  1054. || !feature_is_ep_halt(crq))
  1055. goto stall;
  1056. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1057. if (!target)
  1058. goto stall;
  1059. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1060. if (target->index != 0)
  1061. usba_ep_writel(target, CLR_STA,
  1062. USBA_TOGGLE_CLR);
  1063. } else {
  1064. goto delegate;
  1065. }
  1066. send_status(udc, ep);
  1067. break;
  1068. }
  1069. case USB_REQ_SET_FEATURE: {
  1070. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1071. if (feature_is_dev_test_mode(crq)) {
  1072. send_status(udc, ep);
  1073. ep->state = STATUS_STAGE_TEST;
  1074. udc->test_mode = le16_to_cpu(crq->wIndex);
  1075. return 0;
  1076. } else if (feature_is_dev_remote_wakeup(crq)) {
  1077. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1078. } else {
  1079. goto stall;
  1080. }
  1081. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1082. struct usba_ep *target;
  1083. if (crq->wLength != __constant_cpu_to_le16(0)
  1084. || !feature_is_ep_halt(crq))
  1085. goto stall;
  1086. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1087. if (!target)
  1088. goto stall;
  1089. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1090. } else
  1091. goto delegate;
  1092. send_status(udc, ep);
  1093. break;
  1094. }
  1095. case USB_REQ_SET_ADDRESS:
  1096. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1097. goto delegate;
  1098. set_address(udc, le16_to_cpu(crq->wValue));
  1099. send_status(udc, ep);
  1100. ep->state = STATUS_STAGE_ADDR;
  1101. break;
  1102. default:
  1103. delegate:
  1104. spin_unlock(&udc->lock);
  1105. retval = udc->driver->setup(&udc->gadget, crq);
  1106. spin_lock(&udc->lock);
  1107. }
  1108. return retval;
  1109. stall:
  1110. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1111. "halting endpoint...\n",
  1112. ep->ep.name, crq->bRequestType, crq->bRequest,
  1113. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1114. le16_to_cpu(crq->wLength));
  1115. set_protocol_stall(udc, ep);
  1116. return -1;
  1117. }
  1118. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1119. {
  1120. struct usba_request *req;
  1121. u32 epstatus;
  1122. u32 epctrl;
  1123. restart:
  1124. epstatus = usba_ep_readl(ep, STA);
  1125. epctrl = usba_ep_readl(ep, CTL);
  1126. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1127. ep->ep.name, ep->state, epstatus, epctrl);
  1128. req = NULL;
  1129. if (!list_empty(&ep->queue))
  1130. req = list_entry(ep->queue.next,
  1131. struct usba_request, queue);
  1132. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1133. if (req->submitted)
  1134. next_fifo_transaction(ep, req);
  1135. else
  1136. submit_request(ep, req);
  1137. if (req->last_transaction) {
  1138. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1139. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1140. }
  1141. goto restart;
  1142. }
  1143. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1144. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1145. switch (ep->state) {
  1146. case DATA_STAGE_IN:
  1147. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1148. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1149. ep->state = STATUS_STAGE_OUT;
  1150. break;
  1151. case STATUS_STAGE_ADDR:
  1152. /* Activate our new address */
  1153. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1154. | USBA_FADDR_EN));
  1155. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1156. ep->state = WAIT_FOR_SETUP;
  1157. break;
  1158. case STATUS_STAGE_IN:
  1159. if (req) {
  1160. list_del_init(&req->queue);
  1161. request_complete(ep, req, 0);
  1162. submit_next_request(ep);
  1163. }
  1164. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1165. ep->state = WAIT_FOR_SETUP;
  1166. break;
  1167. case STATUS_STAGE_TEST:
  1168. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1169. ep->state = WAIT_FOR_SETUP;
  1170. if (do_test_mode(udc))
  1171. set_protocol_stall(udc, ep);
  1172. break;
  1173. default:
  1174. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1175. "halting endpoint...\n",
  1176. ep->ep.name, ep->state);
  1177. set_protocol_stall(udc, ep);
  1178. break;
  1179. }
  1180. goto restart;
  1181. }
  1182. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1183. switch (ep->state) {
  1184. case STATUS_STAGE_OUT:
  1185. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1186. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1187. if (req) {
  1188. list_del_init(&req->queue);
  1189. request_complete(ep, req, 0);
  1190. }
  1191. ep->state = WAIT_FOR_SETUP;
  1192. break;
  1193. case DATA_STAGE_OUT:
  1194. receive_data(ep);
  1195. break;
  1196. default:
  1197. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1198. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1199. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1200. "halting endpoint...\n",
  1201. ep->ep.name, ep->state);
  1202. set_protocol_stall(udc, ep);
  1203. break;
  1204. }
  1205. goto restart;
  1206. }
  1207. if (epstatus & USBA_RX_SETUP) {
  1208. union {
  1209. struct usb_ctrlrequest crq;
  1210. unsigned long data[2];
  1211. } crq;
  1212. unsigned int pkt_len;
  1213. int ret;
  1214. if (ep->state != WAIT_FOR_SETUP) {
  1215. /*
  1216. * Didn't expect a SETUP packet at this
  1217. * point. Clean up any pending requests (which
  1218. * may be successful).
  1219. */
  1220. int status = -EPROTO;
  1221. /*
  1222. * RXRDY and TXCOMP are dropped when SETUP
  1223. * packets arrive. Just pretend we received
  1224. * the status packet.
  1225. */
  1226. if (ep->state == STATUS_STAGE_OUT
  1227. || ep->state == STATUS_STAGE_IN) {
  1228. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1229. status = 0;
  1230. }
  1231. if (req) {
  1232. list_del_init(&req->queue);
  1233. request_complete(ep, req, status);
  1234. }
  1235. }
  1236. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1237. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1238. if (pkt_len != sizeof(crq)) {
  1239. pr_warning("udc: Invalid packet length %u "
  1240. "(expected %lu)\n", pkt_len, sizeof(crq));
  1241. set_protocol_stall(udc, ep);
  1242. return;
  1243. }
  1244. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1245. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1246. /* Free up one bank in the FIFO so that we can
  1247. * generate or receive a reply right away. */
  1248. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1249. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1250. ep->state, crq.crq.bRequestType,
  1251. crq.crq.bRequest); */
  1252. if (crq.crq.bRequestType & USB_DIR_IN) {
  1253. /*
  1254. * The USB 2.0 spec states that "if wLength is
  1255. * zero, there is no data transfer phase."
  1256. * However, testusb #14 seems to actually
  1257. * expect a data phase even if wLength = 0...
  1258. */
  1259. ep->state = DATA_STAGE_IN;
  1260. } else {
  1261. if (crq.crq.wLength != __constant_cpu_to_le16(0))
  1262. ep->state = DATA_STAGE_OUT;
  1263. else
  1264. ep->state = STATUS_STAGE_IN;
  1265. }
  1266. ret = -1;
  1267. if (ep->index == 0)
  1268. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1269. else {
  1270. spin_unlock(&udc->lock);
  1271. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1272. spin_lock(&udc->lock);
  1273. }
  1274. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1275. crq.crq.bRequestType, crq.crq.bRequest,
  1276. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1277. if (ret < 0) {
  1278. /* Let the host know that we failed */
  1279. set_protocol_stall(udc, ep);
  1280. }
  1281. }
  1282. }
  1283. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1284. {
  1285. struct usba_request *req;
  1286. u32 epstatus;
  1287. u32 epctrl;
  1288. epstatus = usba_ep_readl(ep, STA);
  1289. epctrl = usba_ep_readl(ep, CTL);
  1290. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1291. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1292. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1293. if (list_empty(&ep->queue)) {
  1294. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1295. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1296. return;
  1297. }
  1298. req = list_entry(ep->queue.next, struct usba_request, queue);
  1299. if (req->using_dma) {
  1300. /* Send a zero-length packet */
  1301. usba_ep_writel(ep, SET_STA,
  1302. USBA_TX_PK_RDY);
  1303. usba_ep_writel(ep, CTL_DIS,
  1304. USBA_TX_PK_RDY);
  1305. list_del_init(&req->queue);
  1306. submit_next_request(ep);
  1307. request_complete(ep, req, 0);
  1308. } else {
  1309. if (req->submitted)
  1310. next_fifo_transaction(ep, req);
  1311. else
  1312. submit_request(ep, req);
  1313. if (req->last_transaction) {
  1314. list_del_init(&req->queue);
  1315. submit_next_request(ep);
  1316. request_complete(ep, req, 0);
  1317. }
  1318. }
  1319. epstatus = usba_ep_readl(ep, STA);
  1320. epctrl = usba_ep_readl(ep, CTL);
  1321. }
  1322. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1323. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1324. receive_data(ep);
  1325. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1326. }
  1327. }
  1328. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1329. {
  1330. struct usba_request *req;
  1331. u32 status, control, pending;
  1332. status = usba_dma_readl(ep, STATUS);
  1333. control = usba_dma_readl(ep, CONTROL);
  1334. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1335. ep->last_dma_status = status;
  1336. #endif
  1337. pending = status & control;
  1338. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1339. if (status & USBA_DMA_CH_EN) {
  1340. dev_err(&udc->pdev->dev,
  1341. "DMA_CH_EN is set after transfer is finished!\n");
  1342. dev_err(&udc->pdev->dev,
  1343. "status=%#08x, pending=%#08x, control=%#08x\n",
  1344. status, pending, control);
  1345. /*
  1346. * try to pretend nothing happened. We might have to
  1347. * do something here...
  1348. */
  1349. }
  1350. if (list_empty(&ep->queue))
  1351. /* Might happen if a reset comes along at the right moment */
  1352. return;
  1353. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1354. req = list_entry(ep->queue.next, struct usba_request, queue);
  1355. usba_update_req(ep, req, status);
  1356. list_del_init(&req->queue);
  1357. submit_next_request(ep);
  1358. request_complete(ep, req, 0);
  1359. }
  1360. }
  1361. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1362. {
  1363. struct usba_udc *udc = devid;
  1364. u32 status;
  1365. u32 dma_status;
  1366. u32 ep_status;
  1367. spin_lock(&udc->lock);
  1368. status = usba_readl(udc, INT_STA);
  1369. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1370. if (status & USBA_DET_SUSPEND) {
  1371. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1372. DBG(DBG_BUS, "Suspend detected\n");
  1373. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1374. && udc->driver && udc->driver->suspend) {
  1375. spin_unlock(&udc->lock);
  1376. udc->driver->suspend(&udc->gadget);
  1377. spin_lock(&udc->lock);
  1378. }
  1379. }
  1380. if (status & USBA_WAKE_UP) {
  1381. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1382. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1383. }
  1384. if (status & USBA_END_OF_RESUME) {
  1385. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1386. DBG(DBG_BUS, "Resume detected\n");
  1387. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1388. && udc->driver && udc->driver->resume) {
  1389. spin_unlock(&udc->lock);
  1390. udc->driver->resume(&udc->gadget);
  1391. spin_lock(&udc->lock);
  1392. }
  1393. }
  1394. dma_status = USBA_BFEXT(DMA_INT, status);
  1395. if (dma_status) {
  1396. int i;
  1397. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1398. if (dma_status & (1 << i))
  1399. usba_dma_irq(udc, &usba_ep[i]);
  1400. }
  1401. ep_status = USBA_BFEXT(EPT_INT, status);
  1402. if (ep_status) {
  1403. int i;
  1404. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1405. if (ep_status & (1 << i)) {
  1406. if (ep_is_control(&usba_ep[i]))
  1407. usba_control_irq(udc, &usba_ep[i]);
  1408. else
  1409. usba_ep_irq(udc, &usba_ep[i]);
  1410. }
  1411. }
  1412. if (status & USBA_END_OF_RESET) {
  1413. struct usba_ep *ep0;
  1414. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1415. reset_all_endpoints(udc);
  1416. if (status & USBA_HIGH_SPEED) {
  1417. DBG(DBG_BUS, "High-speed bus reset detected\n");
  1418. udc->gadget.speed = USB_SPEED_HIGH;
  1419. } else {
  1420. DBG(DBG_BUS, "Full-speed bus reset detected\n");
  1421. udc->gadget.speed = USB_SPEED_FULL;
  1422. }
  1423. ep0 = &usba_ep[0];
  1424. ep0->desc = &usba_ep0_desc;
  1425. ep0->state = WAIT_FOR_SETUP;
  1426. usba_ep_writel(ep0, CFG,
  1427. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1428. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1429. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1430. usba_ep_writel(ep0, CTL_ENB,
  1431. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1432. usba_writel(udc, INT_ENB,
  1433. (usba_readl(udc, INT_ENB)
  1434. | USBA_BF(EPT_INT, 1)
  1435. | USBA_DET_SUSPEND
  1436. | USBA_END_OF_RESUME));
  1437. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1438. dev_warn(&udc->pdev->dev,
  1439. "WARNING: EP0 configuration is invalid!\n");
  1440. }
  1441. spin_unlock(&udc->lock);
  1442. return IRQ_HANDLED;
  1443. }
  1444. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1445. {
  1446. struct usba_udc *udc = devid;
  1447. int vbus;
  1448. /* debounce */
  1449. udelay(10);
  1450. spin_lock(&udc->lock);
  1451. /* May happen if Vbus pin toggles during probe() */
  1452. if (!udc->driver)
  1453. goto out;
  1454. vbus = gpio_get_value(udc->vbus_pin);
  1455. if (vbus != udc->vbus_prev) {
  1456. if (vbus) {
  1457. usba_writel(udc, CTRL, USBA_EN_USBA);
  1458. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1459. } else {
  1460. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1461. reset_all_endpoints(udc);
  1462. usba_writel(udc, CTRL, 0);
  1463. spin_unlock(&udc->lock);
  1464. udc->driver->disconnect(&udc->gadget);
  1465. spin_lock(&udc->lock);
  1466. }
  1467. udc->vbus_prev = vbus;
  1468. }
  1469. out:
  1470. spin_unlock(&udc->lock);
  1471. return IRQ_HANDLED;
  1472. }
  1473. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1474. {
  1475. struct usba_udc *udc = &the_udc;
  1476. unsigned long flags;
  1477. int ret;
  1478. if (!udc->pdev)
  1479. return -ENODEV;
  1480. spin_lock_irqsave(&udc->lock, flags);
  1481. if (udc->driver) {
  1482. spin_unlock_irqrestore(&udc->lock, flags);
  1483. return -EBUSY;
  1484. }
  1485. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1486. udc->driver = driver;
  1487. udc->gadget.dev.driver = &driver->driver;
  1488. spin_unlock_irqrestore(&udc->lock, flags);
  1489. clk_enable(udc->pclk);
  1490. clk_enable(udc->hclk);
  1491. ret = driver->bind(&udc->gadget);
  1492. if (ret) {
  1493. DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
  1494. driver->driver.name, ret);
  1495. goto err_driver_bind;
  1496. }
  1497. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1498. udc->vbus_prev = 0;
  1499. if (udc->vbus_pin != -1)
  1500. enable_irq(gpio_to_irq(udc->vbus_pin));
  1501. /* If Vbus is present, enable the controller and wait for reset */
  1502. spin_lock_irqsave(&udc->lock, flags);
  1503. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1504. usba_writel(udc, CTRL, USBA_EN_USBA);
  1505. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1506. }
  1507. spin_unlock_irqrestore(&udc->lock, flags);
  1508. return 0;
  1509. err_driver_bind:
  1510. udc->driver = NULL;
  1511. udc->gadget.dev.driver = NULL;
  1512. return ret;
  1513. }
  1514. EXPORT_SYMBOL(usb_gadget_register_driver);
  1515. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1516. {
  1517. struct usba_udc *udc = &the_udc;
  1518. unsigned long flags;
  1519. if (!udc->pdev)
  1520. return -ENODEV;
  1521. if (driver != udc->driver)
  1522. return -EINVAL;
  1523. if (udc->vbus_pin != -1)
  1524. disable_irq(gpio_to_irq(udc->vbus_pin));
  1525. spin_lock_irqsave(&udc->lock, flags);
  1526. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1527. reset_all_endpoints(udc);
  1528. spin_unlock_irqrestore(&udc->lock, flags);
  1529. /* This will also disable the DP pullup */
  1530. usba_writel(udc, CTRL, 0);
  1531. driver->unbind(&udc->gadget);
  1532. udc->gadget.dev.driver = NULL;
  1533. udc->driver = NULL;
  1534. clk_disable(udc->hclk);
  1535. clk_disable(udc->pclk);
  1536. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1537. return 0;
  1538. }
  1539. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1540. static int __init usba_udc_probe(struct platform_device *pdev)
  1541. {
  1542. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1543. struct resource *regs, *fifo;
  1544. struct clk *pclk, *hclk;
  1545. struct usba_udc *udc = &the_udc;
  1546. int irq, ret, i;
  1547. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1548. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1549. if (!regs || !fifo)
  1550. return -ENXIO;
  1551. irq = platform_get_irq(pdev, 0);
  1552. if (irq < 0)
  1553. return irq;
  1554. pclk = clk_get(&pdev->dev, "pclk");
  1555. if (IS_ERR(pclk))
  1556. return PTR_ERR(pclk);
  1557. hclk = clk_get(&pdev->dev, "hclk");
  1558. if (IS_ERR(hclk)) {
  1559. ret = PTR_ERR(hclk);
  1560. goto err_get_hclk;
  1561. }
  1562. udc->pdev = pdev;
  1563. udc->pclk = pclk;
  1564. udc->hclk = hclk;
  1565. udc->vbus_pin = -1;
  1566. ret = -ENOMEM;
  1567. udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
  1568. if (!udc->regs) {
  1569. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1570. goto err_map_regs;
  1571. }
  1572. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1573. (unsigned long)regs->start, udc->regs);
  1574. udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
  1575. if (!udc->fifo) {
  1576. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1577. goto err_map_fifo;
  1578. }
  1579. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1580. (unsigned long)fifo->start, udc->fifo);
  1581. device_initialize(&udc->gadget.dev);
  1582. udc->gadget.dev.parent = &pdev->dev;
  1583. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1584. platform_set_drvdata(pdev, udc);
  1585. /* Make sure we start from a clean slate */
  1586. clk_enable(pclk);
  1587. usba_writel(udc, CTRL, 0);
  1588. clk_disable(pclk);
  1589. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1590. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1591. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1592. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1593. for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
  1594. struct usba_ep *ep = &usba_ep[i];
  1595. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1596. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1597. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1598. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1599. }
  1600. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1601. if (ret) {
  1602. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1603. irq, ret);
  1604. goto err_request_irq;
  1605. }
  1606. udc->irq = irq;
  1607. ret = device_add(&udc->gadget.dev);
  1608. if (ret) {
  1609. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1610. goto err_device_add;
  1611. }
  1612. if (pdata && pdata->vbus_pin >= 0) {
  1613. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1614. udc->vbus_pin = pdata->vbus_pin;
  1615. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1616. usba_vbus_irq, 0,
  1617. "atmel_usba_udc", udc);
  1618. if (ret) {
  1619. gpio_free(udc->vbus_pin);
  1620. udc->vbus_pin = -1;
  1621. dev_warn(&udc->pdev->dev,
  1622. "failed to request vbus irq; "
  1623. "assuming always on\n");
  1624. } else {
  1625. disable_irq(gpio_to_irq(udc->vbus_pin));
  1626. }
  1627. }
  1628. }
  1629. usba_init_debugfs(udc);
  1630. for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
  1631. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1632. return 0;
  1633. err_device_add:
  1634. free_irq(irq, udc);
  1635. err_request_irq:
  1636. iounmap(udc->fifo);
  1637. err_map_fifo:
  1638. iounmap(udc->regs);
  1639. err_map_regs:
  1640. clk_put(hclk);
  1641. err_get_hclk:
  1642. clk_put(pclk);
  1643. platform_set_drvdata(pdev, NULL);
  1644. return ret;
  1645. }
  1646. static int __exit usba_udc_remove(struct platform_device *pdev)
  1647. {
  1648. struct usba_udc *udc;
  1649. int i;
  1650. udc = platform_get_drvdata(pdev);
  1651. for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
  1652. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1653. usba_cleanup_debugfs(udc);
  1654. if (udc->vbus_pin != -1)
  1655. gpio_free(udc->vbus_pin);
  1656. free_irq(udc->irq, udc);
  1657. iounmap(udc->fifo);
  1658. iounmap(udc->regs);
  1659. clk_put(udc->hclk);
  1660. clk_put(udc->pclk);
  1661. device_unregister(&udc->gadget.dev);
  1662. return 0;
  1663. }
  1664. static struct platform_driver udc_driver = {
  1665. .remove = __exit_p(usba_udc_remove),
  1666. .driver = {
  1667. .name = "atmel_usba_udc",
  1668. },
  1669. };
  1670. static int __init udc_init(void)
  1671. {
  1672. return platform_driver_probe(&udc_driver, usba_udc_probe);
  1673. }
  1674. module_init(udc_init);
  1675. static void __exit udc_exit(void)
  1676. {
  1677. platform_driver_unregister(&udc_driver);
  1678. }
  1679. module_exit(udc_exit);
  1680. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1681. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
  1682. MODULE_LICENSE("GPL");