hdmiphy_drv.c 11 KB

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  1. /*
  2. * Samsung HDMI Physical interface driver
  3. *
  4. * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
  5. * Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/i2c.h>
  14. #include <linux/slab.h>
  15. #include <linux/clk.h>
  16. #include <linux/io.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/err.h>
  20. #include <media/v4l2-subdev.h>
  21. MODULE_AUTHOR("Tomasz Stanislawski <t.stanislaws@samsung.com>");
  22. MODULE_DESCRIPTION("Samsung HDMI Physical interface driver");
  23. MODULE_LICENSE("GPL");
  24. struct hdmiphy_conf {
  25. unsigned long pixclk;
  26. const u8 *data;
  27. };
  28. struct hdmiphy_ctx {
  29. struct v4l2_subdev sd;
  30. const struct hdmiphy_conf *conf_tab;
  31. };
  32. static const struct hdmiphy_conf hdmiphy_conf_s5pv210[] = {
  33. { .pixclk = 27000000, .data = (u8 [32]) {
  34. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
  35. 0x6B, 0x10, 0x02, 0x52, 0xDF, 0xF2, 0x54, 0x87,
  36. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  37. 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, }
  38. },
  39. { .pixclk = 27027000, .data = (u8 [32]) {
  40. 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
  41. 0x6B, 0x10, 0x02, 0x52, 0xDF, 0xF2, 0x54, 0x87,
  42. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  43. 0x22, 0x40, 0xE2, 0x26, 0x00, 0x00, 0x00, 0x00, }
  44. },
  45. { .pixclk = 74176000, .data = (u8 [32]) {
  46. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B,
  47. 0x6D, 0x10, 0x01, 0x52, 0xEF, 0xF3, 0x54, 0xB9,
  48. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  49. 0x22, 0x40, 0xA5, 0x26, 0x01, 0x00, 0x00, 0x00, }
  50. },
  51. { .pixclk = 74250000, .data = (u8 [32]) {
  52. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40,
  53. 0x6A, 0x10, 0x01, 0x52, 0xFF, 0xF1, 0x54, 0xBA,
  54. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
  55. 0x22, 0x40, 0xA4, 0x26, 0x01, 0x00, 0x00, 0x00, }
  56. },
  57. { /* end marker */ }
  58. };
  59. static const struct hdmiphy_conf hdmiphy_conf_exynos4210[] = {
  60. { .pixclk = 27000000, .data = (u8 [32]) {
  61. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
  62. 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
  63. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  64. 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, }
  65. },
  66. { .pixclk = 27027000, .data = (u8 [32]) {
  67. 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
  68. 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
  69. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  70. 0x22, 0x40, 0xE2, 0x26, 0x00, 0x00, 0x00, 0x00, }
  71. },
  72. { .pixclk = 74176000, .data = (u8 [32]) {
  73. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B,
  74. 0x6D, 0x10, 0x01, 0x51, 0xEF, 0xF3, 0x54, 0xB9,
  75. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  76. 0x22, 0x40, 0xA5, 0x26, 0x01, 0x00, 0x00, 0x00, }
  77. },
  78. { .pixclk = 74250000, .data = (u8 [32]) {
  79. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40,
  80. 0x6A, 0x10, 0x01, 0x51, 0xFF, 0xF1, 0x54, 0xBA,
  81. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
  82. 0x22, 0x40, 0xA4, 0x26, 0x01, 0x00, 0x00, 0x00, }
  83. },
  84. { .pixclk = 148352000, .data = (u8 [32]) {
  85. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B,
  86. 0x6D, 0x18, 0x00, 0x51, 0xEF, 0xF3, 0x54, 0xB9,
  87. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  88. 0x11, 0x40, 0xA5, 0x26, 0x02, 0x00, 0x00, 0x00, }
  89. },
  90. { .pixclk = 148500000, .data = (u8 [32]) {
  91. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40,
  92. 0x6A, 0x18, 0x00, 0x51, 0xFF, 0xF1, 0x54, 0xBA,
  93. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
  94. 0x11, 0x40, 0xA4, 0x26, 0x02, 0x00, 0x00, 0x00, }
  95. },
  96. { /* end marker */ }
  97. };
  98. static const struct hdmiphy_conf hdmiphy_conf_exynos4212[] = {
  99. { .pixclk = 27000000, .data = (u8 [32]) {
  100. 0x01, 0x11, 0x2D, 0x75, 0x00, 0x01, 0x00, 0x08,
  101. 0x82, 0x00, 0x0E, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
  102. 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x71,
  103. 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
  104. },
  105. { .pixclk = 27027000, .data = (u8 [32]) {
  106. 0x01, 0x91, 0x2D, 0x72, 0x00, 0x64, 0x12, 0x08,
  107. 0x43, 0x20, 0x0E, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
  108. 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x71,
  109. 0x54, 0xE2, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
  110. },
  111. { .pixclk = 74176000, .data = (u8 [32]) {
  112. 0x01, 0x91, 0x3E, 0x35, 0x00, 0x5B, 0xDE, 0x08,
  113. 0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
  114. 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x52,
  115. 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
  116. },
  117. { .pixclk = 74250000, .data = (u8 [32]) {
  118. 0x01, 0x91, 0x3E, 0x35, 0x00, 0x40, 0xF0, 0x08,
  119. 0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
  120. 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x52,
  121. 0x54, 0xA4, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
  122. },
  123. { .pixclk = 148500000, .data = (u8 [32]) {
  124. 0x01, 0x91, 0x3E, 0x15, 0x00, 0x40, 0xF0, 0x08,
  125. 0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
  126. 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0xA4,
  127. 0x54, 0x4A, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, }
  128. },
  129. { /* end marker */ }
  130. };
  131. static const struct hdmiphy_conf hdmiphy_conf_exynos4412[] = {
  132. { .pixclk = 27000000, .data = (u8 [32]) {
  133. 0x01, 0x11, 0x2D, 0x75, 0x40, 0x01, 0x00, 0x08,
  134. 0x82, 0x00, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  135. 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
  136. 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
  137. },
  138. { .pixclk = 27027000, .data = (u8 [32]) {
  139. 0x01, 0x91, 0x2D, 0x72, 0x40, 0x64, 0x12, 0x08,
  140. 0x43, 0x20, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
  141. 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
  142. 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
  143. },
  144. { .pixclk = 74176000, .data = (u8 [32]) {
  145. 0x01, 0x91, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0x08,
  146. 0x81, 0x20, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  147. 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
  148. 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
  149. },
  150. { .pixclk = 74250000, .data = (u8 [32]) {
  151. 0x01, 0x91, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
  152. 0x81, 0x20, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  153. 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
  154. 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
  155. },
  156. { .pixclk = 148500000, .data = (u8 [32]) {
  157. 0x01, 0x91, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
  158. 0x81, 0x20, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
  159. 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
  160. 0x54, 0x4B, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, }
  161. },
  162. { /* end marker */ }
  163. };
  164. static inline struct hdmiphy_ctx *sd_to_ctx(struct v4l2_subdev *sd)
  165. {
  166. return container_of(sd, struct hdmiphy_ctx, sd);
  167. }
  168. static unsigned long hdmiphy_preset_to_pixclk(u32 preset)
  169. {
  170. static const unsigned long pixclk[] = {
  171. [V4L2_DV_480P59_94] = 27000000,
  172. [V4L2_DV_576P50] = 27000000,
  173. [V4L2_DV_720P59_94] = 74176000,
  174. [V4L2_DV_720P50] = 74250000,
  175. [V4L2_DV_720P60] = 74250000,
  176. [V4L2_DV_1080P24] = 74250000,
  177. [V4L2_DV_1080P30] = 74250000,
  178. [V4L2_DV_1080I50] = 74250000,
  179. [V4L2_DV_1080I60] = 74250000,
  180. [V4L2_DV_1080P50] = 148500000,
  181. [V4L2_DV_1080P60] = 148500000,
  182. };
  183. if (preset < ARRAY_SIZE(pixclk))
  184. return pixclk[preset];
  185. else
  186. return 0;
  187. }
  188. static const u8 *hdmiphy_find_conf(unsigned long pixclk,
  189. const struct hdmiphy_conf *conf)
  190. {
  191. for (; conf->pixclk; ++conf)
  192. if (conf->pixclk == pixclk)
  193. return conf->data;
  194. return NULL;
  195. }
  196. static int hdmiphy_s_power(struct v4l2_subdev *sd, int on)
  197. {
  198. /* to be implemented */
  199. return 0;
  200. }
  201. static int hdmiphy_s_dv_preset(struct v4l2_subdev *sd,
  202. struct v4l2_dv_preset *preset)
  203. {
  204. const u8 *data = NULL;
  205. u8 buffer[32];
  206. int ret;
  207. struct hdmiphy_ctx *ctx = sd_to_ctx(sd);
  208. struct i2c_client *client = v4l2_get_subdevdata(sd);
  209. unsigned long pixclk;
  210. struct device *dev = &client->dev;
  211. dev_info(dev, "s_dv_preset(preset = %d)\n", preset->preset);
  212. pixclk = hdmiphy_preset_to_pixclk(preset->preset);
  213. data = hdmiphy_find_conf(pixclk, ctx->conf_tab);
  214. if (!data) {
  215. dev_err(dev, "format not supported\n");
  216. return -EINVAL;
  217. }
  218. /* storing configuration to the device */
  219. memcpy(buffer, data, 32);
  220. ret = i2c_master_send(client, buffer, 32);
  221. if (ret != 32) {
  222. dev_err(dev, "failed to configure HDMIPHY via I2C\n");
  223. return -EIO;
  224. }
  225. return 0;
  226. }
  227. static int hdmiphy_s_dv_timings(struct v4l2_subdev *sd,
  228. struct v4l2_dv_timings *timings)
  229. {
  230. const u8 *data;
  231. u8 buffer[32];
  232. int ret;
  233. struct hdmiphy_ctx *ctx = sd_to_ctx(sd);
  234. struct i2c_client *client = v4l2_get_subdevdata(sd);
  235. struct device *dev = &client->dev;
  236. unsigned long pixclk = timings->bt.pixelclock;
  237. dev_info(dev, "s_dv_timings\n");
  238. if ((timings->bt.flags & V4L2_DV_FL_REDUCED_FPS) && pixclk == 74250000)
  239. pixclk = 74176000;
  240. data = hdmiphy_find_conf(pixclk, ctx->conf_tab);
  241. if (!data) {
  242. dev_err(dev, "format not supported\n");
  243. return -EINVAL;
  244. }
  245. /* storing configuration to the device */
  246. memcpy(buffer, data, 32);
  247. ret = i2c_master_send(client, buffer, 32);
  248. if (ret != 32) {
  249. dev_err(dev, "failed to configure HDMIPHY via I2C\n");
  250. return -EIO;
  251. }
  252. return 0;
  253. }
  254. static int hdmiphy_dv_timings_cap(struct v4l2_subdev *sd,
  255. struct v4l2_dv_timings_cap *cap)
  256. {
  257. cap->type = V4L2_DV_BT_656_1120;
  258. /* The phy only determines the pixelclock, leave the other values
  259. * at 0 to signify that we have no information for them. */
  260. cap->bt.min_pixelclock = 27000000;
  261. cap->bt.max_pixelclock = 148500000;
  262. return 0;
  263. }
  264. static int hdmiphy_s_stream(struct v4l2_subdev *sd, int enable)
  265. {
  266. struct i2c_client *client = v4l2_get_subdevdata(sd);
  267. struct device *dev = &client->dev;
  268. u8 buffer[2];
  269. int ret;
  270. dev_info(dev, "s_stream(%d)\n", enable);
  271. /* going to/from configuration from/to operation mode */
  272. buffer[0] = 0x1f;
  273. buffer[1] = enable ? 0x80 : 0x00;
  274. ret = i2c_master_send(client, buffer, 2);
  275. if (ret != 2) {
  276. dev_err(dev, "stream (%d) failed\n", enable);
  277. return -EIO;
  278. }
  279. return 0;
  280. }
  281. static const struct v4l2_subdev_core_ops hdmiphy_core_ops = {
  282. .s_power = hdmiphy_s_power,
  283. };
  284. static const struct v4l2_subdev_video_ops hdmiphy_video_ops = {
  285. .s_dv_preset = hdmiphy_s_dv_preset,
  286. .s_dv_timings = hdmiphy_s_dv_timings,
  287. .dv_timings_cap = hdmiphy_dv_timings_cap,
  288. .s_stream = hdmiphy_s_stream,
  289. };
  290. static const struct v4l2_subdev_ops hdmiphy_ops = {
  291. .core = &hdmiphy_core_ops,
  292. .video = &hdmiphy_video_ops,
  293. };
  294. static int hdmiphy_probe(struct i2c_client *client,
  295. const struct i2c_device_id *id)
  296. {
  297. struct hdmiphy_ctx *ctx;
  298. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  299. if (!ctx)
  300. return -ENOMEM;
  301. ctx->conf_tab = (struct hdmiphy_conf *)id->driver_data;
  302. v4l2_i2c_subdev_init(&ctx->sd, client, &hdmiphy_ops);
  303. dev_info(&client->dev, "probe successful\n");
  304. return 0;
  305. }
  306. static int hdmiphy_remove(struct i2c_client *client)
  307. {
  308. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  309. struct hdmiphy_ctx *ctx = sd_to_ctx(sd);
  310. kfree(ctx);
  311. dev_info(&client->dev, "remove successful\n");
  312. return 0;
  313. }
  314. static const struct i2c_device_id hdmiphy_id[] = {
  315. { "hdmiphy", (unsigned long)hdmiphy_conf_exynos4210 },
  316. { "hdmiphy-s5pv210", (unsigned long)hdmiphy_conf_s5pv210 },
  317. { "hdmiphy-exynos4210", (unsigned long)hdmiphy_conf_exynos4210 },
  318. { "hdmiphy-exynos4212", (unsigned long)hdmiphy_conf_exynos4212 },
  319. { "hdmiphy-exynos4412", (unsigned long)hdmiphy_conf_exynos4412 },
  320. { },
  321. };
  322. MODULE_DEVICE_TABLE(i2c, hdmiphy_id);
  323. static struct i2c_driver hdmiphy_driver = {
  324. .driver = {
  325. .name = "s5p-hdmiphy",
  326. .owner = THIS_MODULE,
  327. },
  328. .probe = hdmiphy_probe,
  329. .remove = hdmiphy_remove,
  330. .id_table = hdmiphy_id,
  331. };
  332. module_i2c_driver(hdmiphy_driver);