wm8962.c 58 KB

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  1. /*
  2. * wm8962.c -- WM8962 ALSA SoC Audio driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/gcd.h>
  19. #include <linux/gpio.h>
  20. #include <linux/i2c.h>
  21. #include <linux/input.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/slab.h>
  25. #include <linux/workqueue.h>
  26. #include <sound/core.h>
  27. #include <sound/jack.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/soc.h>
  31. #include <sound/soc-dapm.h>
  32. #include <sound/initval.h>
  33. #include <sound/tlv.h>
  34. #include <sound/wm8962.h>
  35. #include "wm8962.h"
  36. #define WM8962_NUM_SUPPLIES 8
  37. static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  38. "DCVDD",
  39. "DBVDD",
  40. "AVDD",
  41. "CPVDD",
  42. "MICVDD",
  43. "PLLVDD",
  44. "SPKVDD1",
  45. "SPKVDD2",
  46. };
  47. /* codec private data */
  48. struct wm8962_priv {
  49. struct snd_soc_codec *codec;
  50. u16 reg_cache[WM8962_MAX_REGISTER + 1];
  51. int sysclk;
  52. int sysclk_rate;
  53. int bclk; /* Desired BCLK */
  54. int lrclk;
  55. int fll_src;
  56. int fll_fref;
  57. int fll_fout;
  58. struct delayed_work mic_work;
  59. struct snd_soc_jack *jack;
  60. struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  61. struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  62. #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  63. struct input_dev *beep;
  64. struct work_struct beep_work;
  65. int beep_rate;
  66. #endif
  67. #ifdef CONFIG_GPIOLIB
  68. struct gpio_chip gpio_chip;
  69. #endif
  70. };
  71. /* We can't use the same notifier block for more than one supply and
  72. * there's no way I can see to get from a callback to the caller
  73. * except container_of().
  74. */
  75. #define WM8962_REGULATOR_EVENT(n) \
  76. static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  77. unsigned long event, void *data) \
  78. { \
  79. struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  80. disable_nb[n]); \
  81. if (event & REGULATOR_EVENT_DISABLE) { \
  82. wm8962->codec->cache_sync = 1; \
  83. } \
  84. return 0; \
  85. }
  86. WM8962_REGULATOR_EVENT(0)
  87. WM8962_REGULATOR_EVENT(1)
  88. WM8962_REGULATOR_EVENT(2)
  89. WM8962_REGULATOR_EVENT(3)
  90. WM8962_REGULATOR_EVENT(4)
  91. WM8962_REGULATOR_EVENT(5)
  92. WM8962_REGULATOR_EVENT(6)
  93. WM8962_REGULATOR_EVENT(7)
  94. static int wm8962_volatile_register(unsigned int reg)
  95. {
  96. if (wm8962_reg_access[reg].vol)
  97. return 1;
  98. else
  99. return 0;
  100. }
  101. static int wm8962_readable_register(unsigned int reg)
  102. {
  103. if (wm8962_reg_access[reg].read)
  104. return 1;
  105. else
  106. return 0;
  107. }
  108. static int wm8962_reset(struct snd_soc_codec *codec)
  109. {
  110. return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
  111. }
  112. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
  113. static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
  114. static const unsigned int mixinpga_tlv[] = {
  115. TLV_DB_RANGE_HEAD(7),
  116. 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
  117. 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
  118. 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
  119. 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
  120. 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
  121. };
  122. static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
  123. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  124. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  125. static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
  126. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  127. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  128. static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
  129. static const unsigned int classd_tlv[] = {
  130. TLV_DB_RANGE_HEAD(7),
  131. 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
  132. 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
  133. };
  134. /* The VU bits for the headphones are in a different register to the mute
  135. * bits and only take effect on the PGA if it is actually powered.
  136. */
  137. static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
  138. struct snd_ctl_elem_value *ucontrol)
  139. {
  140. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  141. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  142. u16 *reg_cache = wm8962->reg_cache;
  143. int ret;
  144. /* Apply the update (if any) */
  145. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  146. if (ret == 0)
  147. return 0;
  148. /* If the left PGA is enabled hit that VU bit... */
  149. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
  150. return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
  151. reg_cache[WM8962_HPOUTL_VOLUME]);
  152. /* ...otherwise the right. The VU is stereo. */
  153. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
  154. return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
  155. reg_cache[WM8962_HPOUTR_VOLUME]);
  156. return 0;
  157. }
  158. /* The VU bits for the speakers are in a different register to the mute
  159. * bits and only take effect on the PGA if it is actually powered.
  160. */
  161. static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
  162. struct snd_ctl_elem_value *ucontrol)
  163. {
  164. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  165. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  166. u16 *reg_cache = wm8962->reg_cache;
  167. int ret;
  168. /* Apply the update (if any) */
  169. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  170. if (ret == 0)
  171. return 0;
  172. /* If the left PGA is enabled hit that VU bit... */
  173. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
  174. return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
  175. reg_cache[WM8962_SPKOUTL_VOLUME]);
  176. /* ...otherwise the right. The VU is stereo. */
  177. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
  178. return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
  179. reg_cache[WM8962_SPKOUTR_VOLUME]);
  180. return 0;
  181. }
  182. static const struct snd_kcontrol_new wm8962_snd_controls[] = {
  183. SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
  184. SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
  185. mixin_tlv),
  186. SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
  187. mixinpga_tlv),
  188. SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
  189. mixin_tlv),
  190. SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
  191. mixin_tlv),
  192. SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
  193. mixinpga_tlv),
  194. SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
  195. mixin_tlv),
  196. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
  197. WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
  198. SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
  199. WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
  200. SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
  201. WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
  202. SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
  203. WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
  204. SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
  205. WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
  206. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
  207. WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
  208. SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
  209. SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
  210. 5, 1, 0),
  211. SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
  212. SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
  213. WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
  214. SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
  215. snd_soc_get_volsw, wm8962_put_hp_sw),
  216. SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
  217. 7, 1, 0),
  218. SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
  219. hp_tlv),
  220. SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
  221. WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
  222. SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
  223. 3, 7, 0, bypass_tlv),
  224. SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
  225. 0, 7, 0, bypass_tlv),
  226. SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
  227. 7, 1, 1, inmix_tlv),
  228. SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
  229. 6, 1, 1, inmix_tlv),
  230. SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
  231. 3, 7, 0, bypass_tlv),
  232. SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
  233. 0, 7, 0, bypass_tlv),
  234. SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
  235. 7, 1, 1, inmix_tlv),
  236. SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
  237. 6, 1, 1, inmix_tlv),
  238. SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
  239. classd_tlv),
  240. };
  241. static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
  242. SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
  243. SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
  244. snd_soc_get_volsw, wm8962_put_spk_sw),
  245. SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
  246. SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
  247. SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  248. 3, 7, 0, bypass_tlv),
  249. SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  250. 0, 7, 0, bypass_tlv),
  251. SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  252. 7, 1, 1, inmix_tlv),
  253. SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  254. 6, 1, 1, inmix_tlv),
  255. SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  256. 7, 1, 0, inmix_tlv),
  257. SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  258. 6, 1, 0, inmix_tlv),
  259. };
  260. static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
  261. SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
  262. WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
  263. SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
  264. snd_soc_get_volsw, wm8962_put_spk_sw),
  265. SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
  266. 7, 1, 0),
  267. SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
  268. WM8962_SPEAKER_MIXER_4, 8, 1, 1),
  269. SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  270. 3, 7, 0, bypass_tlv),
  271. SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  272. 0, 7, 0, bypass_tlv),
  273. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  274. 7, 1, 1, inmix_tlv),
  275. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  276. 6, 1, 1, inmix_tlv),
  277. SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  278. 7, 1, 0, inmix_tlv),
  279. SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  280. 6, 1, 0, inmix_tlv),
  281. SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
  282. 3, 7, 0, bypass_tlv),
  283. SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
  284. 0, 7, 0, bypass_tlv),
  285. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
  286. 7, 1, 1, inmix_tlv),
  287. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
  288. 6, 1, 1, inmix_tlv),
  289. SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  290. 5, 1, 0, inmix_tlv),
  291. SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  292. 4, 1, 0, inmix_tlv),
  293. };
  294. static int sysclk_event(struct snd_soc_dapm_widget *w,
  295. struct snd_kcontrol *kcontrol, int event)
  296. {
  297. struct snd_soc_codec *codec = w->codec;
  298. int src;
  299. int fll;
  300. src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
  301. switch (src) {
  302. case 0: /* MCLK */
  303. fll = 0;
  304. break;
  305. case 0x200: /* FLL */
  306. fll = 1;
  307. break;
  308. default:
  309. dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
  310. return -EINVAL;
  311. }
  312. switch (event) {
  313. case SND_SOC_DAPM_PRE_PMU:
  314. if (fll)
  315. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  316. WM8962_FLL_ENA, WM8962_FLL_ENA);
  317. break;
  318. case SND_SOC_DAPM_POST_PMD:
  319. if (fll)
  320. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  321. WM8962_FLL_ENA, 0);
  322. break;
  323. default:
  324. BUG();
  325. return -EINVAL;
  326. }
  327. return 0;
  328. }
  329. static int cp_event(struct snd_soc_dapm_widget *w,
  330. struct snd_kcontrol *kcontrol, int event)
  331. {
  332. switch (event) {
  333. case SND_SOC_DAPM_POST_PMU:
  334. msleep(5);
  335. break;
  336. default:
  337. BUG();
  338. return -EINVAL;
  339. }
  340. return 0;
  341. }
  342. static int hp_event(struct snd_soc_dapm_widget *w,
  343. struct snd_kcontrol *kcontrol, int event)
  344. {
  345. struct snd_soc_codec *codec = w->codec;
  346. int timeout;
  347. int reg;
  348. int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
  349. WM8962_DCS_STARTUP_DONE_HP1R);
  350. switch (event) {
  351. case SND_SOC_DAPM_POST_PMU:
  352. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  353. WM8962_HP1L_ENA | WM8962_HP1R_ENA,
  354. WM8962_HP1L_ENA | WM8962_HP1R_ENA);
  355. udelay(20);
  356. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  357. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
  358. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
  359. /* Start the DC servo */
  360. snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
  361. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  362. WM8962_HP1L_DCS_STARTUP |
  363. WM8962_HP1R_DCS_STARTUP,
  364. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  365. WM8962_HP1L_DCS_STARTUP |
  366. WM8962_HP1R_DCS_STARTUP);
  367. /* Wait for it to complete, should be well under 100ms */
  368. timeout = 0;
  369. do {
  370. msleep(1);
  371. reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
  372. if (reg < 0) {
  373. dev_err(codec->dev,
  374. "Failed to read DCS status: %d\n",
  375. reg);
  376. continue;
  377. }
  378. dev_dbg(codec->dev, "DCS status: %x\n", reg);
  379. } while (++timeout < 200 && (reg & expected) != expected);
  380. if ((reg & expected) != expected)
  381. dev_err(codec->dev, "DC servo timed out\n");
  382. else
  383. dev_dbg(codec->dev, "DC servo complete after %dms\n",
  384. timeout);
  385. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  386. WM8962_HP1L_ENA_OUTP |
  387. WM8962_HP1R_ENA_OUTP,
  388. WM8962_HP1L_ENA_OUTP |
  389. WM8962_HP1R_ENA_OUTP);
  390. udelay(20);
  391. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  392. WM8962_HP1L_RMV_SHORT |
  393. WM8962_HP1R_RMV_SHORT,
  394. WM8962_HP1L_RMV_SHORT |
  395. WM8962_HP1R_RMV_SHORT);
  396. break;
  397. case SND_SOC_DAPM_PRE_PMD:
  398. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  399. WM8962_HP1L_RMV_SHORT |
  400. WM8962_HP1R_RMV_SHORT, 0);
  401. udelay(20);
  402. snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
  403. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  404. WM8962_HP1L_DCS_STARTUP |
  405. WM8962_HP1R_DCS_STARTUP,
  406. 0);
  407. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  408. WM8962_HP1L_ENA | WM8962_HP1R_ENA |
  409. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
  410. WM8962_HP1L_ENA_OUTP |
  411. WM8962_HP1R_ENA_OUTP, 0);
  412. break;
  413. default:
  414. BUG();
  415. return -EINVAL;
  416. }
  417. return 0;
  418. }
  419. /* VU bits for the output PGAs only take effect while the PGA is powered */
  420. static int out_pga_event(struct snd_soc_dapm_widget *w,
  421. struct snd_kcontrol *kcontrol, int event)
  422. {
  423. struct snd_soc_codec *codec = w->codec;
  424. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  425. u16 *reg_cache = wm8962->reg_cache;
  426. int reg;
  427. switch (w->shift) {
  428. case WM8962_HPOUTR_PGA_ENA_SHIFT:
  429. reg = WM8962_HPOUTR_VOLUME;
  430. break;
  431. case WM8962_HPOUTL_PGA_ENA_SHIFT:
  432. reg = WM8962_HPOUTL_VOLUME;
  433. break;
  434. case WM8962_SPKOUTR_PGA_ENA_SHIFT:
  435. reg = WM8962_SPKOUTR_VOLUME;
  436. break;
  437. case WM8962_SPKOUTL_PGA_ENA_SHIFT:
  438. reg = WM8962_SPKOUTL_VOLUME;
  439. break;
  440. default:
  441. BUG();
  442. return -EINVAL;
  443. }
  444. switch (event) {
  445. case SND_SOC_DAPM_POST_PMU:
  446. return snd_soc_write(codec, reg, reg_cache[reg]);
  447. default:
  448. BUG();
  449. return -EINVAL;
  450. }
  451. }
  452. static const char *st_text[] = { "None", "Right", "Left" };
  453. static const struct soc_enum str_enum =
  454. SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
  455. static const struct snd_kcontrol_new str_mux =
  456. SOC_DAPM_ENUM("Right Sidetone", str_enum);
  457. static const struct soc_enum stl_enum =
  458. SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
  459. static const struct snd_kcontrol_new stl_mux =
  460. SOC_DAPM_ENUM("Left Sidetone", stl_enum);
  461. static const char *outmux_text[] = { "DAC", "Mixer" };
  462. static const struct soc_enum spkoutr_enum =
  463. SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
  464. static const struct snd_kcontrol_new spkoutr_mux =
  465. SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
  466. static const struct soc_enum spkoutl_enum =
  467. SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
  468. static const struct snd_kcontrol_new spkoutl_mux =
  469. SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
  470. static const struct soc_enum hpoutr_enum =
  471. SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
  472. static const struct snd_kcontrol_new hpoutr_mux =
  473. SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
  474. static const struct soc_enum hpoutl_enum =
  475. SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
  476. static const struct snd_kcontrol_new hpoutl_mux =
  477. SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
  478. static const struct snd_kcontrol_new inpgal[] = {
  479. SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
  480. SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
  481. SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
  482. SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
  483. };
  484. static const struct snd_kcontrol_new inpgar[] = {
  485. SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
  486. SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
  487. SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
  488. SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
  489. };
  490. static const struct snd_kcontrol_new mixinl[] = {
  491. SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
  492. SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
  493. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
  494. };
  495. static const struct snd_kcontrol_new mixinr[] = {
  496. SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
  497. SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
  498. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
  499. };
  500. static const struct snd_kcontrol_new hpmixl[] = {
  501. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
  502. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
  503. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
  504. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
  505. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
  506. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
  507. };
  508. static const struct snd_kcontrol_new hpmixr[] = {
  509. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
  510. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
  511. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
  512. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
  513. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
  514. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
  515. };
  516. static const struct snd_kcontrol_new spkmixl[] = {
  517. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
  518. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
  519. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
  520. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
  521. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
  522. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
  523. };
  524. static const struct snd_kcontrol_new spkmixr[] = {
  525. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
  526. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
  527. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
  528. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
  529. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
  530. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
  531. };
  532. static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
  533. SND_SOC_DAPM_INPUT("IN1L"),
  534. SND_SOC_DAPM_INPUT("IN1R"),
  535. SND_SOC_DAPM_INPUT("IN2L"),
  536. SND_SOC_DAPM_INPUT("IN2R"),
  537. SND_SOC_DAPM_INPUT("IN3L"),
  538. SND_SOC_DAPM_INPUT("IN3R"),
  539. SND_SOC_DAPM_INPUT("IN4L"),
  540. SND_SOC_DAPM_INPUT("IN4R"),
  541. SND_SOC_DAPM_INPUT("Beep"),
  542. SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
  543. SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
  544. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
  545. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  546. SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
  547. SND_SOC_DAPM_POST_PMU),
  548. SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
  549. SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
  550. inpgal, ARRAY_SIZE(inpgal)),
  551. SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
  552. inpgar, ARRAY_SIZE(inpgar)),
  553. SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
  554. mixinl, ARRAY_SIZE(mixinl)),
  555. SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
  556. mixinr, ARRAY_SIZE(mixinr)),
  557. SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
  558. SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
  559. SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
  560. SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
  561. SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
  562. SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
  563. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  564. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  565. SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
  566. hpmixl, ARRAY_SIZE(hpmixl)),
  567. SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
  568. hpmixr, ARRAY_SIZE(hpmixr)),
  569. SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
  570. out_pga_event, SND_SOC_DAPM_POST_PMU),
  571. SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
  572. out_pga_event, SND_SOC_DAPM_POST_PMU),
  573. SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
  574. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  575. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  576. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  577. };
  578. static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
  579. SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
  580. spkmixl, ARRAY_SIZE(spkmixl)),
  581. SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  582. out_pga_event, SND_SOC_DAPM_POST_PMU),
  583. SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  584. SND_SOC_DAPM_OUTPUT("SPKOUT"),
  585. };
  586. static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
  587. SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
  588. spkmixl, ARRAY_SIZE(spkmixl)),
  589. SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
  590. spkmixr, ARRAY_SIZE(spkmixr)),
  591. SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  592. out_pga_event, SND_SOC_DAPM_POST_PMU),
  593. SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
  594. out_pga_event, SND_SOC_DAPM_POST_PMU),
  595. SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  596. SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
  597. SND_SOC_DAPM_OUTPUT("SPKOUTL"),
  598. SND_SOC_DAPM_OUTPUT("SPKOUTR"),
  599. };
  600. static const struct snd_soc_dapm_route wm8962_intercon[] = {
  601. { "INPGAL", "IN1L Switch", "IN1L" },
  602. { "INPGAL", "IN2L Switch", "IN2L" },
  603. { "INPGAL", "IN3L Switch", "IN3L" },
  604. { "INPGAL", "IN4L Switch", "IN4L" },
  605. { "INPGAR", "IN1R Switch", "IN1R" },
  606. { "INPGAR", "IN2R Switch", "IN2R" },
  607. { "INPGAR", "IN3R Switch", "IN3R" },
  608. { "INPGAR", "IN4R Switch", "IN4R" },
  609. { "MIXINL", "IN2L Switch", "IN2L" },
  610. { "MIXINL", "IN3L Switch", "IN3L" },
  611. { "MIXINL", "PGA Switch", "INPGAL" },
  612. { "MIXINR", "IN2R Switch", "IN2R" },
  613. { "MIXINR", "IN3R Switch", "IN3R" },
  614. { "MIXINR", "PGA Switch", "INPGAR" },
  615. { "ADCL", NULL, "SYSCLK" },
  616. { "ADCL", NULL, "TOCLK" },
  617. { "ADCL", NULL, "MIXINL" },
  618. { "ADCR", NULL, "SYSCLK" },
  619. { "ADCR", NULL, "TOCLK" },
  620. { "ADCR", NULL, "MIXINR" },
  621. { "STL", "Left", "ADCL" },
  622. { "STL", "Right", "ADCR" },
  623. { "STR", "Left", "ADCL" },
  624. { "STR", "Right", "ADCR" },
  625. { "DACL", NULL, "SYSCLK" },
  626. { "DACL", NULL, "TOCLK" },
  627. { "DACL", NULL, "Beep" },
  628. { "DACL", NULL, "STL" },
  629. { "DACR", NULL, "SYSCLK" },
  630. { "DACR", NULL, "TOCLK" },
  631. { "DACR", NULL, "Beep" },
  632. { "DACR", NULL, "STR" },
  633. { "HPMIXL", "IN4L Switch", "IN4L" },
  634. { "HPMIXL", "IN4R Switch", "IN4R" },
  635. { "HPMIXL", "DACL Switch", "DACL" },
  636. { "HPMIXL", "DACR Switch", "DACR" },
  637. { "HPMIXL", "MIXINL Switch", "MIXINL" },
  638. { "HPMIXL", "MIXINR Switch", "MIXINR" },
  639. { "HPMIXR", "IN4L Switch", "IN4L" },
  640. { "HPMIXR", "IN4R Switch", "IN4R" },
  641. { "HPMIXR", "DACL Switch", "DACL" },
  642. { "HPMIXR", "DACR Switch", "DACR" },
  643. { "HPMIXR", "MIXINL Switch", "MIXINL" },
  644. { "HPMIXR", "MIXINR Switch", "MIXINR" },
  645. { "Left Bypass", NULL, "HPMIXL" },
  646. { "Left Bypass", NULL, "Class G" },
  647. { "Right Bypass", NULL, "HPMIXR" },
  648. { "Right Bypass", NULL, "Class G" },
  649. { "HPOUTL PGA", "Mixer", "Left Bypass" },
  650. { "HPOUTL PGA", "DAC", "DACL" },
  651. { "HPOUTR PGA", "Mixer", "Right Bypass" },
  652. { "HPOUTR PGA", "DAC", "DACR" },
  653. { "HPOUT", NULL, "HPOUTL PGA" },
  654. { "HPOUT", NULL, "HPOUTR PGA" },
  655. { "HPOUT", NULL, "Charge Pump" },
  656. { "HPOUT", NULL, "SYSCLK" },
  657. { "HPOUT", NULL, "TOCLK" },
  658. { "HPOUTL", NULL, "HPOUT" },
  659. { "HPOUTR", NULL, "HPOUT" },
  660. };
  661. static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
  662. { "Speaker Mixer", "IN4L Switch", "IN4L" },
  663. { "Speaker Mixer", "IN4R Switch", "IN4R" },
  664. { "Speaker Mixer", "DACL Switch", "DACL" },
  665. { "Speaker Mixer", "DACR Switch", "DACR" },
  666. { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
  667. { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
  668. { "Speaker PGA", "Mixer", "Speaker Mixer" },
  669. { "Speaker PGA", "DAC", "DACL" },
  670. { "Speaker Output", NULL, "Speaker PGA" },
  671. { "Speaker Output", NULL, "SYSCLK" },
  672. { "Speaker Output", NULL, "TOCLK" },
  673. { "SPKOUT", NULL, "Speaker Output" },
  674. };
  675. static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
  676. { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
  677. { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
  678. { "SPKOUTL Mixer", "DACL Switch", "DACL" },
  679. { "SPKOUTL Mixer", "DACR Switch", "DACR" },
  680. { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
  681. { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
  682. { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
  683. { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
  684. { "SPKOUTR Mixer", "DACL Switch", "DACL" },
  685. { "SPKOUTR Mixer", "DACR Switch", "DACR" },
  686. { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
  687. { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
  688. { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
  689. { "SPKOUTL PGA", "DAC", "DACL" },
  690. { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
  691. { "SPKOUTR PGA", "DAC", "DACR" },
  692. { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
  693. { "SPKOUTL Output", NULL, "SYSCLK" },
  694. { "SPKOUTL Output", NULL, "TOCLK" },
  695. { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
  696. { "SPKOUTR Output", NULL, "SYSCLK" },
  697. { "SPKOUTR Output", NULL, "TOCLK" },
  698. { "SPKOUTL", NULL, "SPKOUTL Output" },
  699. { "SPKOUTR", NULL, "SPKOUTR Output" },
  700. };
  701. static int wm8962_add_widgets(struct snd_soc_codec *codec)
  702. {
  703. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  704. snd_soc_add_controls(codec, wm8962_snd_controls,
  705. ARRAY_SIZE(wm8962_snd_controls));
  706. if (pdata && pdata->spk_mono)
  707. snd_soc_add_controls(codec, wm8962_spk_mono_controls,
  708. ARRAY_SIZE(wm8962_spk_mono_controls));
  709. else
  710. snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
  711. ARRAY_SIZE(wm8962_spk_stereo_controls));
  712. snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
  713. ARRAY_SIZE(wm8962_dapm_widgets));
  714. if (pdata && pdata->spk_mono)
  715. snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
  716. ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
  717. else
  718. snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
  719. ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
  720. snd_soc_dapm_add_routes(codec, wm8962_intercon,
  721. ARRAY_SIZE(wm8962_intercon));
  722. if (pdata && pdata->spk_mono)
  723. snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
  724. ARRAY_SIZE(wm8962_spk_mono_intercon));
  725. else
  726. snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
  727. ARRAY_SIZE(wm8962_spk_stereo_intercon));
  728. snd_soc_dapm_disable_pin(codec, "Beep");
  729. return 0;
  730. }
  731. static void wm8962_sync_cache(struct snd_soc_codec *codec)
  732. {
  733. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  734. int i;
  735. if (!codec->cache_sync)
  736. return;
  737. dev_dbg(codec->dev, "Syncing cache\n");
  738. codec->cache_only = 0;
  739. /* Sync back cached values if they're different from the
  740. * hardware default.
  741. */
  742. for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
  743. if (i == WM8962_SOFTWARE_RESET)
  744. continue;
  745. if (wm8962->reg_cache[i] == wm8962_reg[i])
  746. continue;
  747. snd_soc_write(codec, i, wm8962->reg_cache[i]);
  748. }
  749. codec->cache_sync = 0;
  750. }
  751. /* -1 for reserved values */
  752. static const int bclk_divs[] = {
  753. 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
  754. };
  755. static void wm8962_configure_bclk(struct snd_soc_codec *codec)
  756. {
  757. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  758. int dspclk, i;
  759. int clocking2 = 0;
  760. int aif2 = 0;
  761. if (!wm8962->bclk) {
  762. dev_dbg(codec->dev, "No BCLK rate configured\n");
  763. return;
  764. }
  765. dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
  766. if (dspclk < 0) {
  767. dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
  768. return;
  769. }
  770. dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
  771. switch (dspclk) {
  772. case 0:
  773. dspclk = wm8962->sysclk_rate;
  774. break;
  775. case 1:
  776. dspclk = wm8962->sysclk_rate / 2;
  777. break;
  778. case 2:
  779. dspclk = wm8962->sysclk_rate / 4;
  780. break;
  781. default:
  782. dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
  783. dspclk = wm8962->sysclk;
  784. }
  785. dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
  786. /* We're expecting an exact match */
  787. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  788. if (bclk_divs[i] < 0)
  789. continue;
  790. if (dspclk / bclk_divs[i] == wm8962->bclk) {
  791. dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
  792. bclk_divs[i], wm8962->bclk);
  793. clocking2 |= i;
  794. break;
  795. }
  796. }
  797. if (i == ARRAY_SIZE(bclk_divs)) {
  798. dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
  799. dspclk / wm8962->bclk);
  800. return;
  801. }
  802. aif2 |= wm8962->bclk / wm8962->lrclk;
  803. dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
  804. wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
  805. snd_soc_update_bits(codec, WM8962_CLOCKING2,
  806. WM8962_BCLK_DIV_MASK, clocking2);
  807. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
  808. WM8962_AIF_RATE_MASK, aif2);
  809. }
  810. static int wm8962_set_bias_level(struct snd_soc_codec *codec,
  811. enum snd_soc_bias_level level)
  812. {
  813. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  814. int ret;
  815. if (level == codec->bias_level)
  816. return 0;
  817. switch (level) {
  818. case SND_SOC_BIAS_ON:
  819. break;
  820. case SND_SOC_BIAS_PREPARE:
  821. /* VMID 2*50k */
  822. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  823. WM8962_VMID_SEL_MASK, 0x80);
  824. break;
  825. case SND_SOC_BIAS_STANDBY:
  826. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  827. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  828. wm8962->supplies);
  829. if (ret != 0) {
  830. dev_err(codec->dev,
  831. "Failed to enable supplies: %d\n",
  832. ret);
  833. return ret;
  834. }
  835. wm8962_sync_cache(codec);
  836. snd_soc_update_bits(codec, WM8962_ANTI_POP,
  837. WM8962_STARTUP_BIAS_ENA |
  838. WM8962_VMID_BUF_ENA,
  839. WM8962_STARTUP_BIAS_ENA |
  840. WM8962_VMID_BUF_ENA);
  841. /* Bias enable at 2*50k for ramp */
  842. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  843. WM8962_VMID_SEL_MASK |
  844. WM8962_BIAS_ENA,
  845. WM8962_BIAS_ENA | 0x180);
  846. msleep(5);
  847. snd_soc_update_bits(codec, WM8962_CLOCKING2,
  848. WM8962_CLKREG_OVD,
  849. WM8962_CLKREG_OVD);
  850. wm8962_configure_bclk(codec);
  851. }
  852. /* VMID 2*250k */
  853. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  854. WM8962_VMID_SEL_MASK, 0x100);
  855. break;
  856. case SND_SOC_BIAS_OFF:
  857. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  858. WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
  859. snd_soc_update_bits(codec, WM8962_ANTI_POP,
  860. WM8962_STARTUP_BIAS_ENA |
  861. WM8962_VMID_BUF_ENA, 0);
  862. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
  863. wm8962->supplies);
  864. break;
  865. }
  866. codec->bias_level = level;
  867. return 0;
  868. }
  869. static const struct {
  870. int rate;
  871. int reg;
  872. } sr_vals[] = {
  873. { 48000, 0 },
  874. { 44100, 0 },
  875. { 32000, 1 },
  876. { 22050, 2 },
  877. { 24000, 2 },
  878. { 16000, 3 },
  879. { 11025, 4 },
  880. { 12000, 4 },
  881. { 8000, 5 },
  882. { 88200, 6 },
  883. { 96000, 6 },
  884. };
  885. static const int sysclk_rates[] = {
  886. 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
  887. };
  888. static int wm8962_hw_params(struct snd_pcm_substream *substream,
  889. struct snd_pcm_hw_params *params,
  890. struct snd_soc_dai *dai)
  891. {
  892. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  893. struct snd_soc_codec *codec = rtd->codec;
  894. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  895. int rate = params_rate(params);
  896. int i;
  897. int aif0 = 0;
  898. int adctl3 = 0;
  899. int clocking4 = 0;
  900. wm8962->bclk = snd_soc_params_to_bclk(params);
  901. wm8962->lrclk = params_rate(params);
  902. for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
  903. if (sr_vals[i].rate == rate) {
  904. adctl3 |= sr_vals[i].reg;
  905. break;
  906. }
  907. }
  908. if (i == ARRAY_SIZE(sr_vals)) {
  909. dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
  910. return -EINVAL;
  911. }
  912. if (rate % 8000 == 0)
  913. adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
  914. for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
  915. if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
  916. clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
  917. break;
  918. }
  919. }
  920. if (i == ARRAY_SIZE(sysclk_rates)) {
  921. dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
  922. wm8962->sysclk_rate / rate);
  923. return -EINVAL;
  924. }
  925. switch (params_format(params)) {
  926. case SNDRV_PCM_FORMAT_S16_LE:
  927. break;
  928. case SNDRV_PCM_FORMAT_S20_3LE:
  929. aif0 |= 0x40;
  930. break;
  931. case SNDRV_PCM_FORMAT_S24_LE:
  932. aif0 |= 0x80;
  933. break;
  934. case SNDRV_PCM_FORMAT_S32_LE:
  935. aif0 |= 0xc0;
  936. break;
  937. default:
  938. return -EINVAL;
  939. }
  940. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
  941. WM8962_WL_MASK, aif0);
  942. snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
  943. WM8962_SAMPLE_RATE_INT_MODE |
  944. WM8962_SAMPLE_RATE_MASK, adctl3);
  945. snd_soc_update_bits(codec, WM8962_CLOCKING_4,
  946. WM8962_SYSCLK_RATE_MASK, clocking4);
  947. wm8962_configure_bclk(codec);
  948. return 0;
  949. }
  950. static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  951. unsigned int freq, int dir)
  952. {
  953. struct snd_soc_codec *codec = dai->codec;
  954. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  955. int src;
  956. switch (clk_id) {
  957. case WM8962_SYSCLK_MCLK:
  958. wm8962->sysclk = WM8962_SYSCLK_MCLK;
  959. src = 0;
  960. break;
  961. case WM8962_SYSCLK_FLL:
  962. wm8962->sysclk = WM8962_SYSCLK_FLL;
  963. src = 1 << WM8962_SYSCLK_SRC_SHIFT;
  964. WARN_ON(freq != wm8962->fll_fout);
  965. break;
  966. default:
  967. return -EINVAL;
  968. }
  969. snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
  970. src);
  971. wm8962->sysclk_rate = freq;
  972. return 0;
  973. }
  974. static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  975. {
  976. struct snd_soc_codec *codec = dai->codec;
  977. int aif0 = 0;
  978. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  979. case SND_SOC_DAIFMT_DSP_A:
  980. aif0 |= WM8962_LRCLK_INV;
  981. case SND_SOC_DAIFMT_DSP_B:
  982. aif0 |= 3;
  983. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  984. case SND_SOC_DAIFMT_NB_NF:
  985. case SND_SOC_DAIFMT_IB_NF:
  986. break;
  987. default:
  988. return -EINVAL;
  989. }
  990. break;
  991. case SND_SOC_DAIFMT_RIGHT_J:
  992. break;
  993. case SND_SOC_DAIFMT_LEFT_J:
  994. aif0 |= 1;
  995. break;
  996. case SND_SOC_DAIFMT_I2S:
  997. aif0 |= 2;
  998. break;
  999. default:
  1000. return -EINVAL;
  1001. }
  1002. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1003. case SND_SOC_DAIFMT_NB_NF:
  1004. break;
  1005. case SND_SOC_DAIFMT_IB_NF:
  1006. aif0 |= WM8962_BCLK_INV;
  1007. break;
  1008. case SND_SOC_DAIFMT_NB_IF:
  1009. aif0 |= WM8962_LRCLK_INV;
  1010. break;
  1011. case SND_SOC_DAIFMT_IB_IF:
  1012. aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
  1013. break;
  1014. default:
  1015. return -EINVAL;
  1016. }
  1017. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1018. case SND_SOC_DAIFMT_CBM_CFM:
  1019. aif0 |= WM8962_MSTR;
  1020. break;
  1021. case SND_SOC_DAIFMT_CBS_CFS:
  1022. break;
  1023. default:
  1024. return -EINVAL;
  1025. }
  1026. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
  1027. WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
  1028. WM8962_LRCLK_INV, aif0);
  1029. return 0;
  1030. }
  1031. struct _fll_div {
  1032. u16 fll_fratio;
  1033. u16 fll_outdiv;
  1034. u16 fll_refclk_div;
  1035. u16 n;
  1036. u16 theta;
  1037. u16 lambda;
  1038. };
  1039. /* The size in bits of the FLL divide multiplied by 10
  1040. * to allow rounding later */
  1041. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1042. static struct {
  1043. unsigned int min;
  1044. unsigned int max;
  1045. u16 fll_fratio;
  1046. int ratio;
  1047. } fll_fratios[] = {
  1048. { 0, 64000, 4, 16 },
  1049. { 64000, 128000, 3, 8 },
  1050. { 128000, 256000, 2, 4 },
  1051. { 256000, 1000000, 1, 2 },
  1052. { 1000000, 13500000, 0, 1 },
  1053. };
  1054. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1055. unsigned int Fout)
  1056. {
  1057. unsigned int target;
  1058. unsigned int div;
  1059. unsigned int fratio, gcd_fll;
  1060. int i;
  1061. /* Fref must be <=13.5MHz */
  1062. div = 1;
  1063. fll_div->fll_refclk_div = 0;
  1064. while ((Fref / div) > 13500000) {
  1065. div *= 2;
  1066. fll_div->fll_refclk_div++;
  1067. if (div > 4) {
  1068. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1069. Fref);
  1070. return -EINVAL;
  1071. }
  1072. }
  1073. pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
  1074. /* Apply the division for our remaining calculations */
  1075. Fref /= div;
  1076. /* Fvco should be 90-100MHz; don't check the upper bound */
  1077. div = 2;
  1078. while (Fout * div < 90000000) {
  1079. div++;
  1080. if (div > 64) {
  1081. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1082. Fout);
  1083. return -EINVAL;
  1084. }
  1085. }
  1086. target = Fout * div;
  1087. fll_div->fll_outdiv = div - 1;
  1088. pr_debug("FLL Fvco=%dHz\n", target);
  1089. /* Find an appropraite FLL_FRATIO and factor it out of the target */
  1090. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1091. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1092. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1093. fratio = fll_fratios[i].ratio;
  1094. break;
  1095. }
  1096. }
  1097. if (i == ARRAY_SIZE(fll_fratios)) {
  1098. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1099. return -EINVAL;
  1100. }
  1101. fll_div->n = target / (fratio * Fref);
  1102. if (target % Fref == 0) {
  1103. fll_div->theta = 0;
  1104. fll_div->lambda = 0;
  1105. } else {
  1106. gcd_fll = gcd(target, fratio * Fref);
  1107. fll_div->theta = (target - (fll_div->n * fratio * Fref))
  1108. / gcd_fll;
  1109. fll_div->lambda = (fratio * Fref) / gcd_fll;
  1110. }
  1111. pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
  1112. fll_div->n, fll_div->theta, fll_div->lambda);
  1113. pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
  1114. fll_div->fll_fratio, fll_div->fll_outdiv,
  1115. fll_div->fll_refclk_div);
  1116. return 0;
  1117. }
  1118. static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  1119. unsigned int Fref, unsigned int Fout)
  1120. {
  1121. struct snd_soc_codec *codec = dai->codec;
  1122. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1123. struct _fll_div fll_div;
  1124. int ret;
  1125. int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
  1126. /* Any change? */
  1127. if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
  1128. Fout == wm8962->fll_fout)
  1129. return 0;
  1130. if (Fout == 0) {
  1131. dev_dbg(codec->dev, "FLL disabled\n");
  1132. wm8962->fll_fref = 0;
  1133. wm8962->fll_fout = 0;
  1134. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1135. WM8962_FLL_ENA, 0);
  1136. return 0;
  1137. }
  1138. ret = fll_factors(&fll_div, Fref, Fout);
  1139. if (ret != 0)
  1140. return ret;
  1141. switch (fll_id) {
  1142. case WM8962_FLL_MCLK:
  1143. case WM8962_FLL_BCLK:
  1144. case WM8962_FLL_OSC:
  1145. fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
  1146. break;
  1147. case WM8962_FLL_INT:
  1148. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1149. WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
  1150. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
  1151. WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
  1152. break;
  1153. default:
  1154. dev_err(codec->dev, "Unknown FLL source %d\n", ret);
  1155. return -EINVAL;
  1156. }
  1157. if (fll_div.theta || fll_div.lambda)
  1158. fll1 |= WM8962_FLL_FRAC;
  1159. /* Stop the FLL while we reconfigure */
  1160. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
  1161. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
  1162. WM8962_FLL_OUTDIV_MASK |
  1163. WM8962_FLL_REFCLK_DIV_MASK,
  1164. (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
  1165. (fll_div.fll_refclk_div));
  1166. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
  1167. WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
  1168. snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
  1169. snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
  1170. snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
  1171. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1172. WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
  1173. WM8962_FLL_ENA, fll1);
  1174. dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1175. wm8962->fll_fref = Fref;
  1176. wm8962->fll_fout = Fout;
  1177. wm8962->fll_src = source;
  1178. return 0;
  1179. }
  1180. static int wm8962_mute(struct snd_soc_dai *dai, int mute)
  1181. {
  1182. struct snd_soc_codec *codec = dai->codec;
  1183. int val;
  1184. if (mute)
  1185. val = WM8962_DAC_MUTE;
  1186. else
  1187. val = 0;
  1188. return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
  1189. WM8962_DAC_MUTE, val);
  1190. }
  1191. #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
  1192. #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1193. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1194. static struct snd_soc_dai_ops wm8962_dai_ops = {
  1195. .hw_params = wm8962_hw_params,
  1196. .set_sysclk = wm8962_set_dai_sysclk,
  1197. .set_fmt = wm8962_set_dai_fmt,
  1198. .set_pll = wm8962_set_fll,
  1199. .digital_mute = wm8962_mute,
  1200. };
  1201. static struct snd_soc_dai_driver wm8962_dai = {
  1202. .name = "wm8962",
  1203. .playback = {
  1204. .stream_name = "Playback",
  1205. .channels_min = 2,
  1206. .channels_max = 2,
  1207. .rates = WM8962_RATES,
  1208. .formats = WM8962_FORMATS,
  1209. },
  1210. .capture = {
  1211. .stream_name = "Capture",
  1212. .channels_min = 2,
  1213. .channels_max = 2,
  1214. .rates = WM8962_RATES,
  1215. .formats = WM8962_FORMATS,
  1216. },
  1217. .ops = &wm8962_dai_ops,
  1218. .symmetric_rates = 1,
  1219. };
  1220. static void wm8962_mic_work(struct work_struct *work)
  1221. {
  1222. struct wm8962_priv *wm8962 = container_of(work,
  1223. struct wm8962_priv,
  1224. mic_work.work);
  1225. struct snd_soc_codec *codec = wm8962->codec;
  1226. int status = 0;
  1227. int irq_pol = 0;
  1228. int reg;
  1229. reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
  1230. if (reg & WM8962_MICDET_STS) {
  1231. status |= SND_JACK_MICROPHONE;
  1232. irq_pol |= WM8962_MICD_IRQ_POL;
  1233. }
  1234. if (reg & WM8962_MICSHORT_STS) {
  1235. status |= SND_JACK_BTN_0;
  1236. irq_pol |= WM8962_MICSCD_IRQ_POL;
  1237. }
  1238. snd_soc_jack_report(wm8962->jack, status,
  1239. SND_JACK_MICROPHONE | SND_JACK_BTN_0);
  1240. snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
  1241. WM8962_MICSCD_IRQ_POL |
  1242. WM8962_MICD_IRQ_POL, irq_pol);
  1243. }
  1244. static irqreturn_t wm8962_irq(int irq, void *data)
  1245. {
  1246. struct snd_soc_codec *codec = data;
  1247. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1248. int mask;
  1249. int active;
  1250. mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
  1251. active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
  1252. active &= ~mask;
  1253. if (active & WM8962_FIFOS_ERR_EINT)
  1254. dev_err(codec->dev, "FIFO error\n");
  1255. if (active & WM8962_TEMP_SHUT_EINT)
  1256. dev_crit(codec->dev, "Thermal shutdown\n");
  1257. if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
  1258. dev_dbg(codec->dev, "Microphone event detected\n");
  1259. schedule_delayed_work(&wm8962->mic_work,
  1260. msecs_to_jiffies(250));
  1261. }
  1262. /* Acknowledge the interrupts */
  1263. snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
  1264. return IRQ_HANDLED;
  1265. }
  1266. /**
  1267. * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
  1268. *
  1269. * @codec: WM8962 codec
  1270. * @jack: jack to report detection events on
  1271. *
  1272. * Enable microphone detection via IRQ on the WM8962. If GPIOs are
  1273. * being used to bring out signals to the processor then only platform
  1274. * data configuration is needed for WM8962 and processor GPIOs should
  1275. * be configured using snd_soc_jack_add_gpios() instead.
  1276. *
  1277. * If no jack is supplied detection will be disabled.
  1278. */
  1279. int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
  1280. {
  1281. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1282. int irq_mask, enable;
  1283. wm8962->jack = jack;
  1284. if (jack) {
  1285. irq_mask = 0;
  1286. enable = WM8962_MICDET_ENA;
  1287. } else {
  1288. irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
  1289. enable = 0;
  1290. }
  1291. snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
  1292. WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
  1293. snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
  1294. WM8962_MICDET_ENA, enable);
  1295. /* Send an initial empty report */
  1296. snd_soc_jack_report(wm8962->jack, 0,
  1297. SND_JACK_MICROPHONE | SND_JACK_BTN_0);
  1298. return 0;
  1299. }
  1300. EXPORT_SYMBOL_GPL(wm8962_mic_detect);
  1301. #ifdef CONFIG_PM
  1302. static int wm8962_resume(struct snd_soc_codec *codec)
  1303. {
  1304. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1305. u16 *reg_cache = codec->reg_cache;
  1306. int i;
  1307. /* Restore the registers */
  1308. for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
  1309. switch (i) {
  1310. case WM8962_SOFTWARE_RESET:
  1311. continue;
  1312. default:
  1313. break;
  1314. }
  1315. if (reg_cache[i] != wm8962_reg[i])
  1316. snd_soc_write(codec, i, reg_cache[i]);
  1317. }
  1318. return 0;
  1319. }
  1320. #else
  1321. #define wm8962_resume NULL
  1322. #endif
  1323. #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  1324. static int beep_rates[] = {
  1325. 500, 1000, 2000, 4000,
  1326. };
  1327. static void wm8962_beep_work(struct work_struct *work)
  1328. {
  1329. struct wm8962_priv *wm8962 =
  1330. container_of(work, struct wm8962_priv, beep_work);
  1331. struct snd_soc_codec *codec = wm8962->codec;
  1332. int i;
  1333. int reg = 0;
  1334. int best = 0;
  1335. if (wm8962->beep_rate) {
  1336. for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
  1337. if (abs(wm8962->beep_rate - beep_rates[i]) <
  1338. abs(wm8962->beep_rate - beep_rates[best]))
  1339. best = i;
  1340. }
  1341. dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
  1342. beep_rates[best], wm8962->beep_rate);
  1343. reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
  1344. snd_soc_dapm_enable_pin(codec, "Beep");
  1345. } else {
  1346. dev_dbg(codec->dev, "Disabling beep\n");
  1347. snd_soc_dapm_disable_pin(codec, "Beep");
  1348. }
  1349. snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
  1350. WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
  1351. snd_soc_dapm_sync(codec);
  1352. }
  1353. /* For usability define a way of injecting beep events for the device -
  1354. * many systems will not have a keyboard.
  1355. */
  1356. static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
  1357. unsigned int code, int hz)
  1358. {
  1359. struct snd_soc_codec *codec = input_get_drvdata(dev);
  1360. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1361. dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
  1362. switch (code) {
  1363. case SND_BELL:
  1364. if (hz)
  1365. hz = 1000;
  1366. case SND_TONE:
  1367. break;
  1368. default:
  1369. return -1;
  1370. }
  1371. /* Kick the beep from a workqueue */
  1372. wm8962->beep_rate = hz;
  1373. schedule_work(&wm8962->beep_work);
  1374. return 0;
  1375. }
  1376. static ssize_t wm8962_beep_set(struct device *dev,
  1377. struct device_attribute *attr,
  1378. const char *buf, size_t count)
  1379. {
  1380. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  1381. long int time;
  1382. strict_strtol(buf, 10, &time);
  1383. input_event(wm8962->beep, EV_SND, SND_TONE, time);
  1384. return count;
  1385. }
  1386. static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
  1387. static void wm8962_init_beep(struct snd_soc_codec *codec)
  1388. {
  1389. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1390. int ret;
  1391. wm8962->beep = input_allocate_device();
  1392. if (!wm8962->beep) {
  1393. dev_err(codec->dev, "Failed to allocate beep device\n");
  1394. return;
  1395. }
  1396. INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
  1397. wm8962->beep_rate = 0;
  1398. wm8962->beep->name = "WM8962 Beep Generator";
  1399. wm8962->beep->phys = dev_name(codec->dev);
  1400. wm8962->beep->id.bustype = BUS_I2C;
  1401. wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
  1402. wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
  1403. wm8962->beep->event = wm8962_beep_event;
  1404. wm8962->beep->dev.parent = codec->dev;
  1405. input_set_drvdata(wm8962->beep, codec);
  1406. ret = input_register_device(wm8962->beep);
  1407. if (ret != 0) {
  1408. input_free_device(wm8962->beep);
  1409. wm8962->beep = NULL;
  1410. dev_err(codec->dev, "Failed to register beep device\n");
  1411. }
  1412. ret = device_create_file(codec->dev, &dev_attr_beep);
  1413. if (ret != 0) {
  1414. dev_err(codec->dev, "Failed to create keyclick file: %d\n",
  1415. ret);
  1416. }
  1417. }
  1418. static void wm8962_free_beep(struct snd_soc_codec *codec)
  1419. {
  1420. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1421. device_remove_file(codec->dev, &dev_attr_beep);
  1422. input_unregister_device(wm8962->beep);
  1423. cancel_work_sync(&wm8962->beep_work);
  1424. wm8962->beep = NULL;
  1425. snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
  1426. }
  1427. #else
  1428. static void wm8962_init_beep(struct snd_soc_codec *codec)
  1429. {
  1430. }
  1431. static void wm8962_free_beep(struct snd_soc_codec *codec)
  1432. {
  1433. }
  1434. #endif
  1435. static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
  1436. {
  1437. int mask = 0;
  1438. int val = 0;
  1439. /* Some of the GPIOs are behind MFP configuration and need to
  1440. * be put into GPIO mode. */
  1441. switch (gpio) {
  1442. case 2:
  1443. mask = WM8962_CLKOUT2_SEL_MASK;
  1444. val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
  1445. break;
  1446. case 3:
  1447. mask = WM8962_CLKOUT3_SEL_MASK;
  1448. val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
  1449. break;
  1450. default:
  1451. break;
  1452. }
  1453. if (mask)
  1454. snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
  1455. mask, val);
  1456. }
  1457. #ifdef CONFIG_GPIOLIB
  1458. static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
  1459. {
  1460. return container_of(chip, struct wm8962_priv, gpio_chip);
  1461. }
  1462. static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
  1463. {
  1464. struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
  1465. struct snd_soc_codec *codec = wm8962->codec;
  1466. /* The WM8962 GPIOs aren't linearly numbered. For simplicity
  1467. * we export linear numbers and error out if the unsupported
  1468. * ones are requsted.
  1469. */
  1470. switch (offset + 1) {
  1471. case 2:
  1472. case 3:
  1473. case 5:
  1474. case 6:
  1475. break;
  1476. default:
  1477. return -EINVAL;
  1478. }
  1479. wm8962_set_gpio_mode(codec, offset + 1);
  1480. return 0;
  1481. }
  1482. static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  1483. {
  1484. struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
  1485. struct snd_soc_codec *codec = wm8962->codec;
  1486. snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
  1487. WM8962_GP2_LVL, value << WM8962_GP2_LVL_SHIFT);
  1488. }
  1489. static int wm8962_gpio_direction_out(struct gpio_chip *chip,
  1490. unsigned offset, int value)
  1491. {
  1492. struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
  1493. struct snd_soc_codec *codec = wm8962->codec;
  1494. int val;
  1495. /* Force function 1 (logic output) */
  1496. val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
  1497. return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
  1498. WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
  1499. }
  1500. static struct gpio_chip wm8962_template_chip = {
  1501. .label = "wm8962",
  1502. .owner = THIS_MODULE,
  1503. .request = wm8962_gpio_request,
  1504. .direction_output = wm8962_gpio_direction_out,
  1505. .set = wm8962_gpio_set,
  1506. .can_sleep = 1,
  1507. };
  1508. static void wm8962_init_gpio(struct snd_soc_codec *codec)
  1509. {
  1510. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1511. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  1512. int ret;
  1513. wm8962->gpio_chip = wm8962_template_chip;
  1514. wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
  1515. wm8962->gpio_chip.dev = codec->dev;
  1516. if (pdata && pdata->gpio_base)
  1517. wm8962->gpio_chip.base = pdata->gpio_base;
  1518. else
  1519. wm8962->gpio_chip.base = -1;
  1520. ret = gpiochip_add(&wm8962->gpio_chip);
  1521. if (ret != 0)
  1522. dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
  1523. }
  1524. static void wm8962_free_gpio(struct snd_soc_codec *codec)
  1525. {
  1526. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1527. int ret;
  1528. ret = gpiochip_remove(&wm8962->gpio_chip);
  1529. if (ret != 0)
  1530. dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
  1531. }
  1532. #else
  1533. static void wm8962_init_gpio(struct snd_soc_codec *codec)
  1534. {
  1535. }
  1536. static void wm8962_free_gpio(struct snd_soc_codec *codec)
  1537. {
  1538. }
  1539. #endif
  1540. static int wm8962_probe(struct snd_soc_codec *codec)
  1541. {
  1542. int ret;
  1543. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1544. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  1545. struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
  1546. dev);
  1547. int i, trigger, irq_pol;
  1548. wm8962->codec = codec;
  1549. INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
  1550. codec->cache_sync = 1;
  1551. codec->idle_bias_off = 1;
  1552. ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
  1553. if (ret != 0) {
  1554. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1555. goto err;
  1556. }
  1557. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  1558. wm8962->supplies[i].supply = wm8962_supply_names[i];
  1559. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
  1560. wm8962->supplies);
  1561. if (ret != 0) {
  1562. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1563. goto err;
  1564. }
  1565. wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
  1566. wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
  1567. wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
  1568. wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
  1569. wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
  1570. wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
  1571. wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
  1572. wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
  1573. /* This should really be moved into the regulator core */
  1574. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
  1575. ret = regulator_register_notifier(wm8962->supplies[i].consumer,
  1576. &wm8962->disable_nb[i]);
  1577. if (ret != 0) {
  1578. dev_err(codec->dev,
  1579. "Failed to register regulator notifier: %d\n",
  1580. ret);
  1581. }
  1582. }
  1583. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  1584. wm8962->supplies);
  1585. if (ret != 0) {
  1586. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  1587. goto err_get;
  1588. }
  1589. ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
  1590. if (ret < 0) {
  1591. dev_err(codec->dev, "Failed to read ID register\n");
  1592. goto err_enable;
  1593. }
  1594. if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
  1595. dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
  1596. ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
  1597. ret = -EINVAL;
  1598. goto err_enable;
  1599. }
  1600. ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
  1601. if (ret < 0) {
  1602. dev_err(codec->dev, "Failed to read device revision: %d\n",
  1603. ret);
  1604. goto err_enable;
  1605. }
  1606. dev_info(codec->dev, "customer id %x revision %c\n",
  1607. (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
  1608. ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
  1609. + 'A');
  1610. ret = wm8962_reset(codec);
  1611. if (ret < 0) {
  1612. dev_err(codec->dev, "Failed to issue reset\n");
  1613. goto err_enable;
  1614. }
  1615. /* SYSCLK defaults to on; make sure it is off so we can safely
  1616. * write to registers if the device is declocked.
  1617. */
  1618. snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
  1619. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1620. if (pdata) {
  1621. /* Apply static configuration for GPIOs */
  1622. for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
  1623. if (pdata->gpio_init[i]) {
  1624. wm8962_set_gpio_mode(codec, i + 1);
  1625. snd_soc_write(codec, 0x200 + i,
  1626. pdata->gpio_init[i] & 0xffff);
  1627. }
  1628. /* Put the speakers into mono mode? */
  1629. if (pdata->spk_mono)
  1630. wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
  1631. |= WM8962_SPK_MONO;
  1632. /* Micbias setup, detection enable and detection
  1633. * threasholds. */
  1634. if (pdata->mic_cfg)
  1635. snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
  1636. WM8962_MICDET_ENA |
  1637. WM8962_MICDET_THR_MASK |
  1638. WM8962_MICSHORT_THR_MASK |
  1639. WM8962_MICBIAS_LVL,
  1640. pdata->mic_cfg);
  1641. }
  1642. /* Latch volume update bits */
  1643. wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
  1644. wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
  1645. wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
  1646. wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
  1647. wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
  1648. wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
  1649. wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
  1650. wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
  1651. wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
  1652. wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
  1653. wm8962_add_widgets(codec);
  1654. wm8962_init_beep(codec);
  1655. wm8962_init_gpio(codec);
  1656. if (i2c->irq) {
  1657. if (pdata && pdata->irq_active_low) {
  1658. trigger = IRQF_TRIGGER_LOW;
  1659. irq_pol = WM8962_IRQ_POL;
  1660. } else {
  1661. trigger = IRQF_TRIGGER_HIGH;
  1662. irq_pol = 0;
  1663. }
  1664. snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
  1665. WM8962_IRQ_POL, irq_pol);
  1666. ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq,
  1667. trigger | IRQF_ONESHOT,
  1668. "wm8962", codec);
  1669. if (ret != 0) {
  1670. dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
  1671. i2c->irq, ret);
  1672. /* Non-fatal */
  1673. } else {
  1674. /* Enable error reporting IRQs by default */
  1675. snd_soc_update_bits(codec,
  1676. WM8962_INTERRUPT_STATUS_2_MASK,
  1677. WM8962_TEMP_SHUT_EINT |
  1678. WM8962_FIFOS_ERR_EINT, 0);
  1679. }
  1680. }
  1681. return 0;
  1682. err_enable:
  1683. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1684. err_get:
  1685. regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1686. err:
  1687. kfree(wm8962);
  1688. return ret;
  1689. }
  1690. static int wm8962_remove(struct snd_soc_codec *codec)
  1691. {
  1692. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1693. struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
  1694. dev);
  1695. int i;
  1696. if (i2c->irq)
  1697. free_irq(i2c->irq, codec);
  1698. cancel_delayed_work_sync(&wm8962->mic_work);
  1699. wm8962_free_gpio(codec);
  1700. wm8962_free_beep(codec);
  1701. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  1702. regulator_unregister_notifier(wm8962->supplies[i].consumer,
  1703. &wm8962->disable_nb[i]);
  1704. regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1705. return 0;
  1706. }
  1707. static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
  1708. .probe = wm8962_probe,
  1709. .remove = wm8962_remove,
  1710. .resume = wm8962_resume,
  1711. .set_bias_level = wm8962_set_bias_level,
  1712. .reg_cache_size = WM8962_MAX_REGISTER + 1,
  1713. .reg_word_size = sizeof(u16),
  1714. .reg_cache_default = wm8962_reg,
  1715. .volatile_register = wm8962_volatile_register,
  1716. .readable_register = wm8962_readable_register,
  1717. };
  1718. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1719. static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
  1720. const struct i2c_device_id *id)
  1721. {
  1722. struct wm8962_priv *wm8962;
  1723. int ret;
  1724. wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
  1725. if (wm8962 == NULL)
  1726. return -ENOMEM;
  1727. i2c_set_clientdata(i2c, wm8962);
  1728. ret = snd_soc_register_codec(&i2c->dev,
  1729. &soc_codec_dev_wm8962, &wm8962_dai, 1);
  1730. if (ret < 0)
  1731. kfree(wm8962);
  1732. return ret;
  1733. }
  1734. static __devexit int wm8962_i2c_remove(struct i2c_client *client)
  1735. {
  1736. snd_soc_unregister_codec(&client->dev);
  1737. kfree(i2c_get_clientdata(client));
  1738. return 0;
  1739. }
  1740. static const struct i2c_device_id wm8962_i2c_id[] = {
  1741. { "wm8962", 0 },
  1742. { }
  1743. };
  1744. MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
  1745. static struct i2c_driver wm8962_i2c_driver = {
  1746. .driver = {
  1747. .name = "wm8962",
  1748. .owner = THIS_MODULE,
  1749. },
  1750. .probe = wm8962_i2c_probe,
  1751. .remove = __devexit_p(wm8962_i2c_remove),
  1752. .id_table = wm8962_i2c_id,
  1753. };
  1754. #endif
  1755. static int __init wm8962_modinit(void)
  1756. {
  1757. int ret;
  1758. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1759. ret = i2c_add_driver(&wm8962_i2c_driver);
  1760. if (ret != 0) {
  1761. printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
  1762. ret);
  1763. }
  1764. #endif
  1765. return 0;
  1766. }
  1767. module_init(wm8962_modinit);
  1768. static void __exit wm8962_exit(void)
  1769. {
  1770. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1771. i2c_del_driver(&wm8962_i2c_driver);
  1772. #endif
  1773. }
  1774. module_exit(wm8962_exit);
  1775. MODULE_DESCRIPTION("ASoC WM8962 driver");
  1776. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  1777. MODULE_LICENSE("GPL");