tegra-cardhu.dts 3.2 KB

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  1. /dts-v1/;
  2. /include/ "tegra30.dtsi"
  3. / {
  4. model = "NVIDIA Tegra30 Cardhu evaluation board";
  5. compatible = "nvidia,cardhu", "nvidia,tegra30";
  6. memory {
  7. reg = < 0x80000000 0x40000000 >;
  8. };
  9. pinmux@70000000 {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. sdmmc1_clk_pz0 {
  14. nvidia,pins = "sdmmc1_clk_pz0";
  15. nvidia,function = "sdmmc1";
  16. nvidia,pull = <0>;
  17. nvidia,tristate = <0>;
  18. };
  19. sdmmc1_cmd_pz1 {
  20. nvidia,pins = "sdmmc1_cmd_pz1",
  21. "sdmmc1_dat0_py7",
  22. "sdmmc1_dat1_py6",
  23. "sdmmc1_dat2_py5",
  24. "sdmmc1_dat3_py4";
  25. nvidia,function = "sdmmc1";
  26. nvidia,pull = <2>;
  27. nvidia,tristate = <0>;
  28. };
  29. sdmmc4_clk_pcc4 {
  30. nvidia,pins = "sdmmc4_clk_pcc4",
  31. "sdmmc4_rst_n_pcc3";
  32. nvidia,function = "sdmmc4";
  33. nvidia,pull = <0>;
  34. nvidia,tristate = <0>;
  35. };
  36. sdmmc4_dat0_paa0 {
  37. nvidia,pins = "sdmmc4_dat0_paa0",
  38. "sdmmc4_dat1_paa1",
  39. "sdmmc4_dat2_paa2",
  40. "sdmmc4_dat3_paa3",
  41. "sdmmc4_dat4_paa4",
  42. "sdmmc4_dat5_paa5",
  43. "sdmmc4_dat6_paa6",
  44. "sdmmc4_dat7_paa7";
  45. nvidia,function = "sdmmc4";
  46. nvidia,pull = <2>;
  47. nvidia,tristate = <0>;
  48. };
  49. dap2_fs_pa2 {
  50. nvidia,pins = "dap2_fs_pa2",
  51. "dap2_sclk_pa3",
  52. "dap2_din_pa4",
  53. "dap2_dout_pa5";
  54. nvidia,function = "i2s1";
  55. nvidia,pull = <0>;
  56. nvidia,tristate = <0>;
  57. };
  58. };
  59. };
  60. serial@70006000 {
  61. clock-frequency = < 408000000 >;
  62. };
  63. serial@70006040 {
  64. status = "disable";
  65. };
  66. serial@70006200 {
  67. status = "disable";
  68. };
  69. serial@70006300 {
  70. status = "disable";
  71. };
  72. serial@70006400 {
  73. status = "disable";
  74. };
  75. i2c@7000c000 {
  76. clock-frequency = <100000>;
  77. };
  78. i2c@7000c400 {
  79. clock-frequency = <100000>;
  80. };
  81. i2c@7000c500 {
  82. clock-frequency = <100000>;
  83. };
  84. i2c@7000c700 {
  85. clock-frequency = <100000>;
  86. };
  87. i2c@7000d000 {
  88. clock-frequency = <100000>;
  89. wm8903: wm8903@1a {
  90. compatible = "wlf,wm8903";
  91. reg = <0x1a>;
  92. interrupt-parent = <&gpio>;
  93. interrupts = <179 0x04>; /* gpio PW3 */
  94. gpio-controller;
  95. #gpio-cells = <2>;
  96. micdet-cfg = <0>;
  97. micdet-delay = <100>;
  98. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  99. };
  100. };
  101. sdhci@78000000 {
  102. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  103. wp-gpios = <&gpio 155 0>; /* gpio PT3 */
  104. power-gpios = <&gpio 31 0>; /* gpio PD7 */
  105. };
  106. sdhci@78000200 {
  107. status = "disable";
  108. };
  109. sdhci@78000400 {
  110. status = "disable";
  111. };
  112. sdhci@78000400 {
  113. support-8bit;
  114. };
  115. ahub@70080000 {
  116. i2s@70080300 {
  117. status = "disable";
  118. };
  119. i2s@70080500 {
  120. status = "disable";
  121. };
  122. i2s@70080600 {
  123. status = "disable";
  124. };
  125. i2s@70080700 {
  126. status = "disable";
  127. };
  128. };
  129. sound {
  130. compatible = "nvidia,tegra-audio-wm8903-cardhu",
  131. "nvidia,tegra-audio-wm8903";
  132. nvidia,model = "NVIDIA Tegra Cardhu";
  133. nvidia,audio-routing =
  134. "Headphone Jack", "HPOUTR",
  135. "Headphone Jack", "HPOUTL",
  136. "Int Spk", "ROP",
  137. "Int Spk", "RON",
  138. "Int Spk", "LOP",
  139. "Int Spk", "LON",
  140. "Mic Jack", "MICBIAS",
  141. "IN1L", "Mic Jack";
  142. nvidia,i2s-controller = <&tegra_i2s1>;
  143. nvidia,audio-codec = <&wm8903>;
  144. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  145. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  146. };
  147. };