ymfpci_main.c 67 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * BUGS:
  6. * --
  7. *
  8. * TODO:
  9. * --
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/pci.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/vmalloc.h>
  34. #include <sound/core.h>
  35. #include <sound/control.h>
  36. #include <sound/info.h>
  37. #include <sound/ymfpci.h>
  38. #include <sound/asoundef.h>
  39. #include <sound/mpu401.h>
  40. #include <asm/io.h>
  41. /*
  42. * constants
  43. */
  44. /*
  45. * common I/O routines
  46. */
  47. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  48. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  49. {
  50. return readb(chip->reg_area_virt + offset);
  51. }
  52. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  53. {
  54. writeb(val, chip->reg_area_virt + offset);
  55. }
  56. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  57. {
  58. return readw(chip->reg_area_virt + offset);
  59. }
  60. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  61. {
  62. writew(val, chip->reg_area_virt + offset);
  63. }
  64. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  65. {
  66. return readl(chip->reg_area_virt + offset);
  67. }
  68. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  69. {
  70. writel(val, chip->reg_area_virt + offset);
  71. }
  72. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  73. {
  74. unsigned long end_time;
  75. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  76. end_time = jiffies + msecs_to_jiffies(750);
  77. do {
  78. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  79. return 0;
  80. set_current_state(TASK_UNINTERRUPTIBLE);
  81. schedule_timeout_uninterruptible(1);
  82. } while (time_before(jiffies, end_time));
  83. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  84. return -EBUSY;
  85. }
  86. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  87. {
  88. struct snd_ymfpci *chip = ac97->private_data;
  89. u32 cmd;
  90. snd_ymfpci_codec_ready(chip, 0);
  91. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  92. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  93. }
  94. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  95. {
  96. struct snd_ymfpci *chip = ac97->private_data;
  97. if (snd_ymfpci_codec_ready(chip, 0))
  98. return ~0;
  99. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  100. if (snd_ymfpci_codec_ready(chip, 0))
  101. return ~0;
  102. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  103. int i;
  104. for (i = 0; i < 600; i++)
  105. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  106. }
  107. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  108. }
  109. /*
  110. * Misc routines
  111. */
  112. static u32 snd_ymfpci_calc_delta(u32 rate)
  113. {
  114. switch (rate) {
  115. case 8000: return 0x02aaab00;
  116. case 11025: return 0x03accd00;
  117. case 16000: return 0x05555500;
  118. case 22050: return 0x07599a00;
  119. case 32000: return 0x0aaaab00;
  120. case 44100: return 0x0eb33300;
  121. default: return ((rate << 16) / 375) << 5;
  122. }
  123. }
  124. static u32 def_rate[8] = {
  125. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  126. };
  127. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  128. {
  129. u32 i;
  130. static u32 val[8] = {
  131. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  132. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  133. };
  134. if (rate == 44100)
  135. return 0x40000000; /* FIXME: What's the right value? */
  136. for (i = 0; i < 8; i++)
  137. if (rate <= def_rate[i])
  138. return val[i];
  139. return val[0];
  140. }
  141. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  142. {
  143. u32 i;
  144. static u32 val[8] = {
  145. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  146. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  147. };
  148. if (rate == 44100)
  149. return 0x370A0000;
  150. for (i = 0; i < 8; i++)
  151. if (rate <= def_rate[i])
  152. return val[i];
  153. return val[0];
  154. }
  155. /*
  156. * Hardware start management
  157. */
  158. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  159. {
  160. unsigned long flags;
  161. spin_lock_irqsave(&chip->reg_lock, flags);
  162. if (chip->start_count++ > 0)
  163. goto __end;
  164. snd_ymfpci_writel(chip, YDSXGR_MODE,
  165. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  166. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  167. __end:
  168. spin_unlock_irqrestore(&chip->reg_lock, flags);
  169. }
  170. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  171. {
  172. unsigned long flags;
  173. long timeout = 1000;
  174. spin_lock_irqsave(&chip->reg_lock, flags);
  175. if (--chip->start_count > 0)
  176. goto __end;
  177. snd_ymfpci_writel(chip, YDSXGR_MODE,
  178. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  179. while (timeout-- > 0) {
  180. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  181. break;
  182. }
  183. if (atomic_read(&chip->interrupt_sleep_count)) {
  184. atomic_set(&chip->interrupt_sleep_count, 0);
  185. wake_up(&chip->interrupt_sleep);
  186. }
  187. __end:
  188. spin_unlock_irqrestore(&chip->reg_lock, flags);
  189. }
  190. /*
  191. * Playback voice management
  192. */
  193. static int voice_alloc(struct snd_ymfpci *chip,
  194. enum snd_ymfpci_voice_type type, int pair,
  195. struct snd_ymfpci_voice **rvoice)
  196. {
  197. struct snd_ymfpci_voice *voice, *voice2;
  198. int idx;
  199. *rvoice = NULL;
  200. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  201. voice = &chip->voices[idx];
  202. voice2 = pair ? &chip->voices[idx+1] : NULL;
  203. if (voice->use || (voice2 && voice2->use))
  204. continue;
  205. voice->use = 1;
  206. if (voice2)
  207. voice2->use = 1;
  208. switch (type) {
  209. case YMFPCI_PCM:
  210. voice->pcm = 1;
  211. if (voice2)
  212. voice2->pcm = 1;
  213. break;
  214. case YMFPCI_SYNTH:
  215. voice->synth = 1;
  216. break;
  217. case YMFPCI_MIDI:
  218. voice->midi = 1;
  219. break;
  220. }
  221. snd_ymfpci_hw_start(chip);
  222. if (voice2)
  223. snd_ymfpci_hw_start(chip);
  224. *rvoice = voice;
  225. return 0;
  226. }
  227. return -ENOMEM;
  228. }
  229. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  230. enum snd_ymfpci_voice_type type, int pair,
  231. struct snd_ymfpci_voice **rvoice)
  232. {
  233. unsigned long flags;
  234. int result;
  235. snd_assert(rvoice != NULL, return -EINVAL);
  236. snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
  237. spin_lock_irqsave(&chip->voice_lock, flags);
  238. for (;;) {
  239. result = voice_alloc(chip, type, pair, rvoice);
  240. if (result == 0 || type != YMFPCI_PCM)
  241. break;
  242. /* TODO: synth/midi voice deallocation */
  243. break;
  244. }
  245. spin_unlock_irqrestore(&chip->voice_lock, flags);
  246. return result;
  247. }
  248. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  249. {
  250. unsigned long flags;
  251. snd_assert(pvoice != NULL, return -EINVAL);
  252. snd_ymfpci_hw_stop(chip);
  253. spin_lock_irqsave(&chip->voice_lock, flags);
  254. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  255. pvoice->ypcm = NULL;
  256. pvoice->interrupt = NULL;
  257. spin_unlock_irqrestore(&chip->voice_lock, flags);
  258. return 0;
  259. }
  260. /*
  261. * PCM part
  262. */
  263. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  264. {
  265. struct snd_ymfpci_pcm *ypcm;
  266. u32 pos, delta;
  267. if ((ypcm = voice->ypcm) == NULL)
  268. return;
  269. if (ypcm->substream == NULL)
  270. return;
  271. spin_lock(&chip->reg_lock);
  272. if (ypcm->running) {
  273. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  274. if (pos < ypcm->last_pos)
  275. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  276. else
  277. delta = pos - ypcm->last_pos;
  278. ypcm->period_pos += delta;
  279. ypcm->last_pos = pos;
  280. if (ypcm->period_pos >= ypcm->period_size) {
  281. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  282. ypcm->period_pos %= ypcm->period_size;
  283. spin_unlock(&chip->reg_lock);
  284. snd_pcm_period_elapsed(ypcm->substream);
  285. spin_lock(&chip->reg_lock);
  286. }
  287. if (unlikely(ypcm->update_pcm_vol)) {
  288. unsigned int subs = ypcm->substream->number;
  289. unsigned int next_bank = 1 - chip->active_bank;
  290. struct snd_ymfpci_playback_bank *bank;
  291. u32 volume;
  292. bank = &voice->bank[next_bank];
  293. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  294. bank->left_gain_end = volume;
  295. if (ypcm->output_rear)
  296. bank->eff2_gain_end = volume;
  297. if (ypcm->voices[1])
  298. bank = &ypcm->voices[1]->bank[next_bank];
  299. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  300. bank->right_gain_end = volume;
  301. if (ypcm->output_rear)
  302. bank->eff3_gain_end = volume;
  303. ypcm->update_pcm_vol--;
  304. }
  305. }
  306. spin_unlock(&chip->reg_lock);
  307. }
  308. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  309. {
  310. struct snd_pcm_runtime *runtime = substream->runtime;
  311. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  312. struct snd_ymfpci *chip = ypcm->chip;
  313. u32 pos, delta;
  314. spin_lock(&chip->reg_lock);
  315. if (ypcm->running) {
  316. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  317. if (pos < ypcm->last_pos)
  318. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  319. else
  320. delta = pos - ypcm->last_pos;
  321. ypcm->period_pos += delta;
  322. ypcm->last_pos = pos;
  323. if (ypcm->period_pos >= ypcm->period_size) {
  324. ypcm->period_pos %= ypcm->period_size;
  325. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  326. spin_unlock(&chip->reg_lock);
  327. snd_pcm_period_elapsed(substream);
  328. spin_lock(&chip->reg_lock);
  329. }
  330. }
  331. spin_unlock(&chip->reg_lock);
  332. }
  333. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  334. int cmd)
  335. {
  336. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  337. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  338. int result = 0;
  339. spin_lock(&chip->reg_lock);
  340. if (ypcm->voices[0] == NULL) {
  341. result = -EINVAL;
  342. goto __unlock;
  343. }
  344. switch (cmd) {
  345. case SNDRV_PCM_TRIGGER_START:
  346. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  347. case SNDRV_PCM_TRIGGER_RESUME:
  348. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  349. if (ypcm->voices[1] != NULL)
  350. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  351. ypcm->running = 1;
  352. break;
  353. case SNDRV_PCM_TRIGGER_STOP:
  354. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  355. case SNDRV_PCM_TRIGGER_SUSPEND:
  356. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  357. if (ypcm->voices[1] != NULL)
  358. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  359. ypcm->running = 0;
  360. break;
  361. default:
  362. result = -EINVAL;
  363. break;
  364. }
  365. __unlock:
  366. spin_unlock(&chip->reg_lock);
  367. return result;
  368. }
  369. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  370. int cmd)
  371. {
  372. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  373. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  374. int result = 0;
  375. u32 tmp;
  376. spin_lock(&chip->reg_lock);
  377. switch (cmd) {
  378. case SNDRV_PCM_TRIGGER_START:
  379. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  380. case SNDRV_PCM_TRIGGER_RESUME:
  381. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  382. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  383. ypcm->running = 1;
  384. break;
  385. case SNDRV_PCM_TRIGGER_STOP:
  386. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  387. case SNDRV_PCM_TRIGGER_SUSPEND:
  388. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  389. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  390. ypcm->running = 0;
  391. break;
  392. default:
  393. result = -EINVAL;
  394. break;
  395. }
  396. spin_unlock(&chip->reg_lock);
  397. return result;
  398. }
  399. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  400. {
  401. int err;
  402. if (ypcm->voices[1] != NULL && voices < 2) {
  403. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  404. ypcm->voices[1] = NULL;
  405. }
  406. if (voices == 1 && ypcm->voices[0] != NULL)
  407. return 0; /* already allocated */
  408. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  409. return 0; /* already allocated */
  410. if (voices > 1) {
  411. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  412. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  413. ypcm->voices[0] = NULL;
  414. }
  415. }
  416. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  417. if (err < 0)
  418. return err;
  419. ypcm->voices[0]->ypcm = ypcm;
  420. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  421. if (voices > 1) {
  422. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  423. ypcm->voices[1]->ypcm = ypcm;
  424. }
  425. return 0;
  426. }
  427. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  428. struct snd_pcm_runtime *runtime,
  429. int has_pcm_volume)
  430. {
  431. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  432. u32 format;
  433. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  434. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  435. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  436. struct snd_ymfpci_playback_bank *bank;
  437. unsigned int nbank;
  438. u32 vol_left, vol_right;
  439. u8 use_left, use_right;
  440. snd_assert(voice != NULL, return);
  441. if (runtime->channels == 1) {
  442. use_left = 1;
  443. use_right = 1;
  444. } else {
  445. use_left = (voiceidx & 1) == 0;
  446. use_right = !use_left;
  447. }
  448. if (has_pcm_volume) {
  449. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  450. [ypcm->substream->number].left << 15);
  451. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  452. [ypcm->substream->number].right << 15);
  453. } else {
  454. vol_left = cpu_to_le32(0x40000000);
  455. vol_right = cpu_to_le32(0x40000000);
  456. }
  457. format = runtime->channels == 2 ? 0x00010000 : 0;
  458. if (snd_pcm_format_width(runtime->format) == 8)
  459. format |= 0x80000000;
  460. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  461. format |= 1;
  462. for (nbank = 0; nbank < 2; nbank++) {
  463. bank = &voice->bank[nbank];
  464. memset(bank, 0, sizeof(*bank));
  465. bank->format = cpu_to_le32(format);
  466. bank->base = cpu_to_le32(runtime->dma_addr);
  467. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  468. bank->lpfQ = cpu_to_le32(lpfQ);
  469. bank->delta =
  470. bank->delta_end = cpu_to_le32(delta);
  471. bank->lpfK =
  472. bank->lpfK_end = cpu_to_le32(lpfK);
  473. bank->eg_gain =
  474. bank->eg_gain_end = cpu_to_le32(0x40000000);
  475. if (ypcm->output_front) {
  476. if (use_left) {
  477. bank->left_gain =
  478. bank->left_gain_end = vol_left;
  479. }
  480. if (use_right) {
  481. bank->right_gain =
  482. bank->right_gain_end = vol_right;
  483. }
  484. }
  485. if (ypcm->output_rear) {
  486. if (use_left) {
  487. bank->eff2_gain =
  488. bank->eff2_gain_end = vol_left;
  489. }
  490. if (use_right) {
  491. bank->eff3_gain =
  492. bank->eff3_gain_end = vol_right;
  493. }
  494. }
  495. }
  496. }
  497. static int __devinit snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  498. {
  499. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  500. 4096, &chip->ac3_tmp_base) < 0)
  501. return -ENOMEM;
  502. chip->bank_effect[3][0]->base =
  503. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  504. chip->bank_effect[3][0]->loop_end =
  505. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  506. chip->bank_effect[4][0]->base =
  507. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  508. chip->bank_effect[4][0]->loop_end =
  509. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  510. spin_lock_irq(&chip->reg_lock);
  511. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  512. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  513. spin_unlock_irq(&chip->reg_lock);
  514. return 0;
  515. }
  516. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  517. {
  518. spin_lock_irq(&chip->reg_lock);
  519. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  520. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  521. spin_unlock_irq(&chip->reg_lock);
  522. // snd_ymfpci_irq_wait(chip);
  523. if (chip->ac3_tmp_base.area) {
  524. snd_dma_free_pages(&chip->ac3_tmp_base);
  525. chip->ac3_tmp_base.area = NULL;
  526. }
  527. return 0;
  528. }
  529. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  530. struct snd_pcm_hw_params *hw_params)
  531. {
  532. struct snd_pcm_runtime *runtime = substream->runtime;
  533. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  534. int err;
  535. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  536. return err;
  537. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  538. return err;
  539. return 0;
  540. }
  541. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  542. {
  543. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  544. struct snd_pcm_runtime *runtime = substream->runtime;
  545. struct snd_ymfpci_pcm *ypcm;
  546. if (runtime->private_data == NULL)
  547. return 0;
  548. ypcm = runtime->private_data;
  549. /* wait, until the PCI operations are not finished */
  550. snd_ymfpci_irq_wait(chip);
  551. snd_pcm_lib_free_pages(substream);
  552. if (ypcm->voices[1]) {
  553. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  554. ypcm->voices[1] = NULL;
  555. }
  556. if (ypcm->voices[0]) {
  557. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  558. ypcm->voices[0] = NULL;
  559. }
  560. return 0;
  561. }
  562. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  563. {
  564. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  565. struct snd_pcm_runtime *runtime = substream->runtime;
  566. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  567. unsigned int nvoice;
  568. ypcm->period_size = runtime->period_size;
  569. ypcm->buffer_size = runtime->buffer_size;
  570. ypcm->period_pos = 0;
  571. ypcm->last_pos = 0;
  572. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  573. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  574. substream->pcm == chip->pcm);
  575. return 0;
  576. }
  577. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  578. struct snd_pcm_hw_params *hw_params)
  579. {
  580. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  581. }
  582. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  583. {
  584. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  585. /* wait, until the PCI operations are not finished */
  586. snd_ymfpci_irq_wait(chip);
  587. return snd_pcm_lib_free_pages(substream);
  588. }
  589. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  590. {
  591. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  592. struct snd_pcm_runtime *runtime = substream->runtime;
  593. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  594. struct snd_ymfpci_capture_bank * bank;
  595. int nbank;
  596. u32 rate, format;
  597. ypcm->period_size = runtime->period_size;
  598. ypcm->buffer_size = runtime->buffer_size;
  599. ypcm->period_pos = 0;
  600. ypcm->last_pos = 0;
  601. ypcm->shift = 0;
  602. rate = ((48000 * 4096) / runtime->rate) - 1;
  603. format = 0;
  604. if (runtime->channels == 2) {
  605. format |= 2;
  606. ypcm->shift++;
  607. }
  608. if (snd_pcm_format_width(runtime->format) == 8)
  609. format |= 1;
  610. else
  611. ypcm->shift++;
  612. switch (ypcm->capture_bank_number) {
  613. case 0:
  614. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  615. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  616. break;
  617. case 1:
  618. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  619. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  620. break;
  621. }
  622. for (nbank = 0; nbank < 2; nbank++) {
  623. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  624. bank->base = cpu_to_le32(runtime->dma_addr);
  625. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  626. bank->start = 0;
  627. bank->num_of_loops = 0;
  628. }
  629. return 0;
  630. }
  631. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  632. {
  633. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  634. struct snd_pcm_runtime *runtime = substream->runtime;
  635. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  636. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  637. if (!(ypcm->running && voice))
  638. return 0;
  639. return le32_to_cpu(voice->bank[chip->active_bank].start);
  640. }
  641. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  642. {
  643. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  644. struct snd_pcm_runtime *runtime = substream->runtime;
  645. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  646. if (!ypcm->running)
  647. return 0;
  648. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  649. }
  650. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  651. {
  652. wait_queue_t wait;
  653. int loops = 4;
  654. while (loops-- > 0) {
  655. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  656. continue;
  657. init_waitqueue_entry(&wait, current);
  658. add_wait_queue(&chip->interrupt_sleep, &wait);
  659. atomic_inc(&chip->interrupt_sleep_count);
  660. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  661. remove_wait_queue(&chip->interrupt_sleep, &wait);
  662. }
  663. }
  664. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  665. {
  666. struct snd_ymfpci *chip = dev_id;
  667. u32 status, nvoice, mode;
  668. struct snd_ymfpci_voice *voice;
  669. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  670. if (status & 0x80000000) {
  671. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  672. spin_lock(&chip->voice_lock);
  673. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  674. voice = &chip->voices[nvoice];
  675. if (voice->interrupt)
  676. voice->interrupt(chip, voice);
  677. }
  678. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  679. if (chip->capture_substream[nvoice])
  680. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  681. }
  682. #if 0
  683. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  684. if (chip->effect_substream[nvoice])
  685. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  686. }
  687. #endif
  688. spin_unlock(&chip->voice_lock);
  689. spin_lock(&chip->reg_lock);
  690. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  691. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  692. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  693. spin_unlock(&chip->reg_lock);
  694. if (atomic_read(&chip->interrupt_sleep_count)) {
  695. atomic_set(&chip->interrupt_sleep_count, 0);
  696. wake_up(&chip->interrupt_sleep);
  697. }
  698. }
  699. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  700. if (status & 1) {
  701. if (chip->timer)
  702. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  703. }
  704. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  705. if (chip->rawmidi)
  706. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data, regs);
  707. return IRQ_HANDLED;
  708. }
  709. static struct snd_pcm_hardware snd_ymfpci_playback =
  710. {
  711. .info = (SNDRV_PCM_INFO_MMAP |
  712. SNDRV_PCM_INFO_MMAP_VALID |
  713. SNDRV_PCM_INFO_INTERLEAVED |
  714. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  715. SNDRV_PCM_INFO_PAUSE |
  716. SNDRV_PCM_INFO_RESUME),
  717. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  718. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  719. .rate_min = 8000,
  720. .rate_max = 48000,
  721. .channels_min = 1,
  722. .channels_max = 2,
  723. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  724. .period_bytes_min = 64,
  725. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  726. .periods_min = 3,
  727. .periods_max = 1024,
  728. .fifo_size = 0,
  729. };
  730. static struct snd_pcm_hardware snd_ymfpci_capture =
  731. {
  732. .info = (SNDRV_PCM_INFO_MMAP |
  733. SNDRV_PCM_INFO_MMAP_VALID |
  734. SNDRV_PCM_INFO_INTERLEAVED |
  735. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  736. SNDRV_PCM_INFO_PAUSE |
  737. SNDRV_PCM_INFO_RESUME),
  738. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  739. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  740. .rate_min = 8000,
  741. .rate_max = 48000,
  742. .channels_min = 1,
  743. .channels_max = 2,
  744. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  745. .period_bytes_min = 64,
  746. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  747. .periods_min = 3,
  748. .periods_max = 1024,
  749. .fifo_size = 0,
  750. };
  751. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  752. {
  753. kfree(runtime->private_data);
  754. }
  755. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  756. {
  757. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  758. struct snd_pcm_runtime *runtime = substream->runtime;
  759. struct snd_ymfpci_pcm *ypcm;
  760. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  761. if (ypcm == NULL)
  762. return -ENOMEM;
  763. ypcm->chip = chip;
  764. ypcm->type = PLAYBACK_VOICE;
  765. ypcm->substream = substream;
  766. runtime->hw = snd_ymfpci_playback;
  767. runtime->private_data = ypcm;
  768. runtime->private_free = snd_ymfpci_pcm_free_substream;
  769. /* FIXME? True value is 256/48 = 5.33333 ms */
  770. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  771. return 0;
  772. }
  773. /* call with spinlock held */
  774. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  775. {
  776. if (! chip->rear_opened) {
  777. if (! chip->spdif_opened) /* set AC3 */
  778. snd_ymfpci_writel(chip, YDSXGR_MODE,
  779. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  780. /* enable second codec (4CHEN) */
  781. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  782. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  783. }
  784. }
  785. /* call with spinlock held */
  786. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  787. {
  788. if (! chip->rear_opened) {
  789. if (! chip->spdif_opened)
  790. snd_ymfpci_writel(chip, YDSXGR_MODE,
  791. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  792. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  793. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  794. }
  795. }
  796. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  797. {
  798. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  799. struct snd_pcm_runtime *runtime = substream->runtime;
  800. struct snd_ymfpci_pcm *ypcm;
  801. struct snd_kcontrol *kctl;
  802. int err;
  803. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  804. return err;
  805. ypcm = runtime->private_data;
  806. ypcm->output_front = 1;
  807. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  808. spin_lock_irq(&chip->reg_lock);
  809. if (ypcm->output_rear) {
  810. ymfpci_open_extension(chip);
  811. chip->rear_opened++;
  812. }
  813. spin_unlock_irq(&chip->reg_lock);
  814. kctl = chip->pcm_mixer[substream->number].ctl;
  815. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  816. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  817. return 0;
  818. }
  819. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  820. {
  821. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  822. struct snd_pcm_runtime *runtime = substream->runtime;
  823. struct snd_ymfpci_pcm *ypcm;
  824. int err;
  825. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  826. return err;
  827. ypcm = runtime->private_data;
  828. ypcm->output_front = 0;
  829. ypcm->output_rear = 1;
  830. spin_lock_irq(&chip->reg_lock);
  831. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  832. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  833. ymfpci_open_extension(chip);
  834. chip->spdif_pcm_bits = chip->spdif_bits;
  835. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  836. chip->spdif_opened++;
  837. spin_unlock_irq(&chip->reg_lock);
  838. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  839. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  840. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  841. return 0;
  842. }
  843. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  844. {
  845. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  846. struct snd_pcm_runtime *runtime = substream->runtime;
  847. struct snd_ymfpci_pcm *ypcm;
  848. int err;
  849. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  850. return err;
  851. ypcm = runtime->private_data;
  852. ypcm->output_front = 0;
  853. ypcm->output_rear = 1;
  854. spin_lock_irq(&chip->reg_lock);
  855. ymfpci_open_extension(chip);
  856. chip->rear_opened++;
  857. spin_unlock_irq(&chip->reg_lock);
  858. return 0;
  859. }
  860. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  861. u32 capture_bank_number)
  862. {
  863. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  864. struct snd_pcm_runtime *runtime = substream->runtime;
  865. struct snd_ymfpci_pcm *ypcm;
  866. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  867. if (ypcm == NULL)
  868. return -ENOMEM;
  869. ypcm->chip = chip;
  870. ypcm->type = capture_bank_number + CAPTURE_REC;
  871. ypcm->substream = substream;
  872. ypcm->capture_bank_number = capture_bank_number;
  873. chip->capture_substream[capture_bank_number] = substream;
  874. runtime->hw = snd_ymfpci_capture;
  875. /* FIXME? True value is 256/48 = 5.33333 ms */
  876. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  877. runtime->private_data = ypcm;
  878. runtime->private_free = snd_ymfpci_pcm_free_substream;
  879. snd_ymfpci_hw_start(chip);
  880. return 0;
  881. }
  882. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  883. {
  884. return snd_ymfpci_capture_open(substream, 0);
  885. }
  886. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  887. {
  888. return snd_ymfpci_capture_open(substream, 1);
  889. }
  890. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  891. {
  892. return 0;
  893. }
  894. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  895. {
  896. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  897. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  898. struct snd_kcontrol *kctl;
  899. spin_lock_irq(&chip->reg_lock);
  900. if (ypcm->output_rear && chip->rear_opened > 0) {
  901. chip->rear_opened--;
  902. ymfpci_close_extension(chip);
  903. }
  904. spin_unlock_irq(&chip->reg_lock);
  905. kctl = chip->pcm_mixer[substream->number].ctl;
  906. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  907. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  908. return snd_ymfpci_playback_close_1(substream);
  909. }
  910. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  911. {
  912. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  913. spin_lock_irq(&chip->reg_lock);
  914. chip->spdif_opened = 0;
  915. ymfpci_close_extension(chip);
  916. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  917. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  918. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  919. spin_unlock_irq(&chip->reg_lock);
  920. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  921. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  922. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  923. return snd_ymfpci_playback_close_1(substream);
  924. }
  925. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  926. {
  927. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  928. spin_lock_irq(&chip->reg_lock);
  929. if (chip->rear_opened > 0) {
  930. chip->rear_opened--;
  931. ymfpci_close_extension(chip);
  932. }
  933. spin_unlock_irq(&chip->reg_lock);
  934. return snd_ymfpci_playback_close_1(substream);
  935. }
  936. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  937. {
  938. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  939. struct snd_pcm_runtime *runtime = substream->runtime;
  940. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  941. if (ypcm != NULL) {
  942. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  943. snd_ymfpci_hw_stop(chip);
  944. }
  945. return 0;
  946. }
  947. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  948. .open = snd_ymfpci_playback_open,
  949. .close = snd_ymfpci_playback_close,
  950. .ioctl = snd_pcm_lib_ioctl,
  951. .hw_params = snd_ymfpci_playback_hw_params,
  952. .hw_free = snd_ymfpci_playback_hw_free,
  953. .prepare = snd_ymfpci_playback_prepare,
  954. .trigger = snd_ymfpci_playback_trigger,
  955. .pointer = snd_ymfpci_playback_pointer,
  956. };
  957. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  958. .open = snd_ymfpci_capture_rec_open,
  959. .close = snd_ymfpci_capture_close,
  960. .ioctl = snd_pcm_lib_ioctl,
  961. .hw_params = snd_ymfpci_capture_hw_params,
  962. .hw_free = snd_ymfpci_capture_hw_free,
  963. .prepare = snd_ymfpci_capture_prepare,
  964. .trigger = snd_ymfpci_capture_trigger,
  965. .pointer = snd_ymfpci_capture_pointer,
  966. };
  967. int __devinit snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  968. {
  969. struct snd_pcm *pcm;
  970. int err;
  971. if (rpcm)
  972. *rpcm = NULL;
  973. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  974. return err;
  975. pcm->private_data = chip;
  976. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  977. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  978. /* global setup */
  979. pcm->info_flags = 0;
  980. strcpy(pcm->name, "YMFPCI");
  981. chip->pcm = pcm;
  982. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  983. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  984. if (rpcm)
  985. *rpcm = pcm;
  986. return 0;
  987. }
  988. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  989. .open = snd_ymfpci_capture_ac97_open,
  990. .close = snd_ymfpci_capture_close,
  991. .ioctl = snd_pcm_lib_ioctl,
  992. .hw_params = snd_ymfpci_capture_hw_params,
  993. .hw_free = snd_ymfpci_capture_hw_free,
  994. .prepare = snd_ymfpci_capture_prepare,
  995. .trigger = snd_ymfpci_capture_trigger,
  996. .pointer = snd_ymfpci_capture_pointer,
  997. };
  998. int __devinit snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  999. {
  1000. struct snd_pcm *pcm;
  1001. int err;
  1002. if (rpcm)
  1003. *rpcm = NULL;
  1004. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1005. return err;
  1006. pcm->private_data = chip;
  1007. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1008. /* global setup */
  1009. pcm->info_flags = 0;
  1010. sprintf(pcm->name, "YMFPCI - %s",
  1011. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1012. chip->pcm2 = pcm;
  1013. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1014. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1015. if (rpcm)
  1016. *rpcm = pcm;
  1017. return 0;
  1018. }
  1019. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1020. .open = snd_ymfpci_playback_spdif_open,
  1021. .close = snd_ymfpci_playback_spdif_close,
  1022. .ioctl = snd_pcm_lib_ioctl,
  1023. .hw_params = snd_ymfpci_playback_hw_params,
  1024. .hw_free = snd_ymfpci_playback_hw_free,
  1025. .prepare = snd_ymfpci_playback_prepare,
  1026. .trigger = snd_ymfpci_playback_trigger,
  1027. .pointer = snd_ymfpci_playback_pointer,
  1028. };
  1029. int __devinit snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1030. {
  1031. struct snd_pcm *pcm;
  1032. int err;
  1033. if (rpcm)
  1034. *rpcm = NULL;
  1035. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1036. return err;
  1037. pcm->private_data = chip;
  1038. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1039. /* global setup */
  1040. pcm->info_flags = 0;
  1041. strcpy(pcm->name, "YMFPCI - IEC958");
  1042. chip->pcm_spdif = pcm;
  1043. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1044. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1045. if (rpcm)
  1046. *rpcm = pcm;
  1047. return 0;
  1048. }
  1049. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1050. .open = snd_ymfpci_playback_4ch_open,
  1051. .close = snd_ymfpci_playback_4ch_close,
  1052. .ioctl = snd_pcm_lib_ioctl,
  1053. .hw_params = snd_ymfpci_playback_hw_params,
  1054. .hw_free = snd_ymfpci_playback_hw_free,
  1055. .prepare = snd_ymfpci_playback_prepare,
  1056. .trigger = snd_ymfpci_playback_trigger,
  1057. .pointer = snd_ymfpci_playback_pointer,
  1058. };
  1059. int __devinit snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1060. {
  1061. struct snd_pcm *pcm;
  1062. int err;
  1063. if (rpcm)
  1064. *rpcm = NULL;
  1065. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1066. return err;
  1067. pcm->private_data = chip;
  1068. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1069. /* global setup */
  1070. pcm->info_flags = 0;
  1071. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1072. chip->pcm_4ch = pcm;
  1073. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1074. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1075. if (rpcm)
  1076. *rpcm = pcm;
  1077. return 0;
  1078. }
  1079. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1080. {
  1081. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1082. uinfo->count = 1;
  1083. return 0;
  1084. }
  1085. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1086. struct snd_ctl_elem_value *ucontrol)
  1087. {
  1088. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1089. spin_lock_irq(&chip->reg_lock);
  1090. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1091. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1092. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1093. spin_unlock_irq(&chip->reg_lock);
  1094. return 0;
  1095. }
  1096. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1097. struct snd_ctl_elem_value *ucontrol)
  1098. {
  1099. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1100. unsigned int val;
  1101. int change;
  1102. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1103. (ucontrol->value.iec958.status[1] << 8);
  1104. spin_lock_irq(&chip->reg_lock);
  1105. change = chip->spdif_bits != val;
  1106. chip->spdif_bits = val;
  1107. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1108. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1109. spin_unlock_irq(&chip->reg_lock);
  1110. return change;
  1111. }
  1112. static struct snd_kcontrol_new snd_ymfpci_spdif_default __devinitdata =
  1113. {
  1114. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1115. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1116. .info = snd_ymfpci_spdif_default_info,
  1117. .get = snd_ymfpci_spdif_default_get,
  1118. .put = snd_ymfpci_spdif_default_put
  1119. };
  1120. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1121. {
  1122. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1123. uinfo->count = 1;
  1124. return 0;
  1125. }
  1126. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1127. struct snd_ctl_elem_value *ucontrol)
  1128. {
  1129. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1130. spin_lock_irq(&chip->reg_lock);
  1131. ucontrol->value.iec958.status[0] = 0x3e;
  1132. ucontrol->value.iec958.status[1] = 0xff;
  1133. spin_unlock_irq(&chip->reg_lock);
  1134. return 0;
  1135. }
  1136. static struct snd_kcontrol_new snd_ymfpci_spdif_mask __devinitdata =
  1137. {
  1138. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1139. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1140. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1141. .info = snd_ymfpci_spdif_mask_info,
  1142. .get = snd_ymfpci_spdif_mask_get,
  1143. };
  1144. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1145. {
  1146. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1147. uinfo->count = 1;
  1148. return 0;
  1149. }
  1150. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1151. struct snd_ctl_elem_value *ucontrol)
  1152. {
  1153. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1154. spin_lock_irq(&chip->reg_lock);
  1155. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1156. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1157. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1158. spin_unlock_irq(&chip->reg_lock);
  1159. return 0;
  1160. }
  1161. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1162. struct snd_ctl_elem_value *ucontrol)
  1163. {
  1164. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1165. unsigned int val;
  1166. int change;
  1167. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1168. (ucontrol->value.iec958.status[1] << 8);
  1169. spin_lock_irq(&chip->reg_lock);
  1170. change = chip->spdif_pcm_bits != val;
  1171. chip->spdif_pcm_bits = val;
  1172. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1173. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1174. spin_unlock_irq(&chip->reg_lock);
  1175. return change;
  1176. }
  1177. static struct snd_kcontrol_new snd_ymfpci_spdif_stream __devinitdata =
  1178. {
  1179. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1180. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1181. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1182. .info = snd_ymfpci_spdif_stream_info,
  1183. .get = snd_ymfpci_spdif_stream_get,
  1184. .put = snd_ymfpci_spdif_stream_put
  1185. };
  1186. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1187. {
  1188. static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1189. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1190. info->count = 1;
  1191. info->value.enumerated.items = 3;
  1192. if (info->value.enumerated.item > 2)
  1193. info->value.enumerated.item = 2;
  1194. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  1195. return 0;
  1196. }
  1197. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1198. {
  1199. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1200. u16 reg;
  1201. spin_lock_irq(&chip->reg_lock);
  1202. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1203. spin_unlock_irq(&chip->reg_lock);
  1204. if (!(reg & 0x100))
  1205. value->value.enumerated.item[0] = 0;
  1206. else
  1207. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1208. return 0;
  1209. }
  1210. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1211. {
  1212. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1213. u16 reg, old_reg;
  1214. spin_lock_irq(&chip->reg_lock);
  1215. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1216. if (value->value.enumerated.item[0] == 0)
  1217. reg = old_reg & ~0x100;
  1218. else
  1219. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1220. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1221. spin_unlock_irq(&chip->reg_lock);
  1222. return reg != old_reg;
  1223. }
  1224. static struct snd_kcontrol_new snd_ymfpci_drec_source __devinitdata = {
  1225. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1226. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1227. .name = "Direct Recording Source",
  1228. .info = snd_ymfpci_drec_source_info,
  1229. .get = snd_ymfpci_drec_source_get,
  1230. .put = snd_ymfpci_drec_source_put
  1231. };
  1232. /*
  1233. * Mixer controls
  1234. */
  1235. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1236. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1237. .info = snd_ymfpci_info_single, \
  1238. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1239. .private_value = ((reg) | ((shift) << 16)) }
  1240. static int snd_ymfpci_info_single(struct snd_kcontrol *kcontrol,
  1241. struct snd_ctl_elem_info *uinfo)
  1242. {
  1243. int reg = kcontrol->private_value & 0xffff;
  1244. switch (reg) {
  1245. case YDSXGR_SPDIFOUTCTRL: break;
  1246. case YDSXGR_SPDIFINCTRL: break;
  1247. default: return -EINVAL;
  1248. }
  1249. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1250. uinfo->count = 1;
  1251. uinfo->value.integer.min = 0;
  1252. uinfo->value.integer.max = 1;
  1253. return 0;
  1254. }
  1255. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1256. struct snd_ctl_elem_value *ucontrol)
  1257. {
  1258. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1259. int reg = kcontrol->private_value & 0xffff;
  1260. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1261. unsigned int mask = 1;
  1262. switch (reg) {
  1263. case YDSXGR_SPDIFOUTCTRL: break;
  1264. case YDSXGR_SPDIFINCTRL: break;
  1265. default: return -EINVAL;
  1266. }
  1267. ucontrol->value.integer.value[0] =
  1268. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1269. return 0;
  1270. }
  1271. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1272. struct snd_ctl_elem_value *ucontrol)
  1273. {
  1274. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1275. int reg = kcontrol->private_value & 0xffff;
  1276. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1277. unsigned int mask = 1;
  1278. int change;
  1279. unsigned int val, oval;
  1280. switch (reg) {
  1281. case YDSXGR_SPDIFOUTCTRL: break;
  1282. case YDSXGR_SPDIFINCTRL: break;
  1283. default: return -EINVAL;
  1284. }
  1285. val = (ucontrol->value.integer.value[0] & mask);
  1286. val <<= shift;
  1287. spin_lock_irq(&chip->reg_lock);
  1288. oval = snd_ymfpci_readl(chip, reg);
  1289. val = (oval & ~(mask << shift)) | val;
  1290. change = val != oval;
  1291. snd_ymfpci_writel(chip, reg, val);
  1292. spin_unlock_irq(&chip->reg_lock);
  1293. return change;
  1294. }
  1295. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1296. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1297. .info = snd_ymfpci_info_double, \
  1298. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1299. .private_value = reg }
  1300. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1301. {
  1302. unsigned int reg = kcontrol->private_value;
  1303. if (reg < 0x80 || reg >= 0xc0)
  1304. return -EINVAL;
  1305. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1306. uinfo->count = 2;
  1307. uinfo->value.integer.min = 0;
  1308. uinfo->value.integer.max = 16383;
  1309. return 0;
  1310. }
  1311. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1312. {
  1313. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1314. unsigned int reg = kcontrol->private_value;
  1315. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1316. unsigned int val;
  1317. if (reg < 0x80 || reg >= 0xc0)
  1318. return -EINVAL;
  1319. spin_lock_irq(&chip->reg_lock);
  1320. val = snd_ymfpci_readl(chip, reg);
  1321. spin_unlock_irq(&chip->reg_lock);
  1322. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1323. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1324. return 0;
  1325. }
  1326. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1327. {
  1328. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1329. unsigned int reg = kcontrol->private_value;
  1330. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1331. int change;
  1332. unsigned int val1, val2, oval;
  1333. if (reg < 0x80 || reg >= 0xc0)
  1334. return -EINVAL;
  1335. val1 = ucontrol->value.integer.value[0] & mask;
  1336. val2 = ucontrol->value.integer.value[1] & mask;
  1337. val1 <<= shift_left;
  1338. val2 <<= shift_right;
  1339. spin_lock_irq(&chip->reg_lock);
  1340. oval = snd_ymfpci_readl(chip, reg);
  1341. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1342. change = val1 != oval;
  1343. snd_ymfpci_writel(chip, reg, val1);
  1344. spin_unlock_irq(&chip->reg_lock);
  1345. return change;
  1346. }
  1347. /*
  1348. * 4ch duplication
  1349. */
  1350. static int snd_ymfpci_info_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1351. {
  1352. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1353. uinfo->count = 1;
  1354. uinfo->value.integer.min = 0;
  1355. uinfo->value.integer.max = 1;
  1356. return 0;
  1357. }
  1358. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1359. {
  1360. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1361. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1362. return 0;
  1363. }
  1364. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1365. {
  1366. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1367. int change;
  1368. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1369. if (change)
  1370. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1371. return change;
  1372. }
  1373. static struct snd_kcontrol_new snd_ymfpci_controls[] __devinitdata = {
  1374. YMFPCI_DOUBLE("Wave Playback Volume", 0, YDSXGR_NATIVEDACOUTVOL),
  1375. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1376. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1377. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1378. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1379. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1380. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1381. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1382. YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
  1383. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1384. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1385. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1386. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1387. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1388. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1389. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1390. {
  1391. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1392. .name = "4ch Duplication",
  1393. .info = snd_ymfpci_info_dup4ch,
  1394. .get = snd_ymfpci_get_dup4ch,
  1395. .put = snd_ymfpci_put_dup4ch,
  1396. },
  1397. };
  1398. /*
  1399. * GPIO
  1400. */
  1401. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1402. {
  1403. u16 reg, mode;
  1404. unsigned long flags;
  1405. spin_lock_irqsave(&chip->reg_lock, flags);
  1406. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1407. reg &= ~(1 << (pin + 8));
  1408. reg |= (1 << pin);
  1409. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1410. /* set the level mode for input line */
  1411. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1412. mode &= ~(3 << (pin * 2));
  1413. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1414. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1415. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1416. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1417. return (mode >> pin) & 1;
  1418. }
  1419. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1420. {
  1421. u16 reg;
  1422. unsigned long flags;
  1423. spin_lock_irqsave(&chip->reg_lock, flags);
  1424. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1425. reg &= ~(1 << pin);
  1426. reg &= ~(1 << (pin + 8));
  1427. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1428. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1429. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1430. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1431. return 0;
  1432. }
  1433. static int snd_ymfpci_gpio_sw_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1434. {
  1435. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1436. uinfo->count = 1;
  1437. uinfo->value.integer.min = 0;
  1438. uinfo->value.integer.max = 1;
  1439. return 0;
  1440. }
  1441. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1442. {
  1443. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1444. int pin = (int)kcontrol->private_value;
  1445. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1446. return 0;
  1447. }
  1448. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1449. {
  1450. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1451. int pin = (int)kcontrol->private_value;
  1452. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1453. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1454. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1455. return 1;
  1456. }
  1457. return 0;
  1458. }
  1459. static struct snd_kcontrol_new snd_ymfpci_rear_shared __devinitdata = {
  1460. .name = "Shared Rear/Line-In Switch",
  1461. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1462. .info = snd_ymfpci_gpio_sw_info,
  1463. .get = snd_ymfpci_gpio_sw_get,
  1464. .put = snd_ymfpci_gpio_sw_put,
  1465. .private_value = 2,
  1466. };
  1467. /*
  1468. * PCM voice volume
  1469. */
  1470. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1471. struct snd_ctl_elem_info *uinfo)
  1472. {
  1473. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1474. uinfo->count = 2;
  1475. uinfo->value.integer.min = 0;
  1476. uinfo->value.integer.max = 0x8000;
  1477. return 0;
  1478. }
  1479. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1480. struct snd_ctl_elem_value *ucontrol)
  1481. {
  1482. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1483. unsigned int subs = kcontrol->id.subdevice;
  1484. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1485. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1486. return 0;
  1487. }
  1488. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1489. struct snd_ctl_elem_value *ucontrol)
  1490. {
  1491. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1492. unsigned int subs = kcontrol->id.subdevice;
  1493. struct snd_pcm_substream *substream;
  1494. unsigned long flags;
  1495. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1496. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1497. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1498. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1499. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1500. spin_lock_irqsave(&chip->voice_lock, flags);
  1501. if (substream->runtime && substream->runtime->private_data) {
  1502. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1503. ypcm->update_pcm_vol = 2;
  1504. }
  1505. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1506. return 1;
  1507. }
  1508. return 0;
  1509. }
  1510. static struct snd_kcontrol_new snd_ymfpci_pcm_volume __devinitdata = {
  1511. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1512. .name = "PCM Playback Volume",
  1513. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1514. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1515. .info = snd_ymfpci_pcm_vol_info,
  1516. .get = snd_ymfpci_pcm_vol_get,
  1517. .put = snd_ymfpci_pcm_vol_put,
  1518. };
  1519. /*
  1520. * Mixer routines
  1521. */
  1522. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1523. {
  1524. struct snd_ymfpci *chip = bus->private_data;
  1525. chip->ac97_bus = NULL;
  1526. }
  1527. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1528. {
  1529. struct snd_ymfpci *chip = ac97->private_data;
  1530. chip->ac97 = NULL;
  1531. }
  1532. int __devinit snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1533. {
  1534. struct snd_ac97_template ac97;
  1535. struct snd_kcontrol *kctl;
  1536. struct snd_pcm_substream *substream;
  1537. unsigned int idx;
  1538. int err;
  1539. static struct snd_ac97_bus_ops ops = {
  1540. .write = snd_ymfpci_codec_write,
  1541. .read = snd_ymfpci_codec_read,
  1542. };
  1543. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1544. return err;
  1545. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1546. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1547. memset(&ac97, 0, sizeof(ac97));
  1548. ac97.private_data = chip;
  1549. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1550. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1551. return err;
  1552. /* to be sure */
  1553. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1554. AC97_EA_VRA|AC97_EA_VRM, 0);
  1555. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1556. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1557. return err;
  1558. }
  1559. /* add S/PDIF control */
  1560. snd_assert(chip->pcm_spdif != NULL, return -EIO);
  1561. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1562. return err;
  1563. kctl->id.device = chip->pcm_spdif->device;
  1564. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1565. return err;
  1566. kctl->id.device = chip->pcm_spdif->device;
  1567. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1568. return err;
  1569. kctl->id.device = chip->pcm_spdif->device;
  1570. chip->spdif_pcm_ctl = kctl;
  1571. /* direct recording source */
  1572. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1573. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1574. return err;
  1575. /*
  1576. * shared rear/line-in
  1577. */
  1578. if (rear_switch) {
  1579. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1580. return err;
  1581. }
  1582. /* per-voice volume */
  1583. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1584. for (idx = 0; idx < 32; ++idx) {
  1585. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1586. if (!kctl)
  1587. return -ENOMEM;
  1588. kctl->id.device = chip->pcm->device;
  1589. kctl->id.subdevice = idx;
  1590. kctl->private_value = (unsigned long)substream;
  1591. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1592. return err;
  1593. chip->pcm_mixer[idx].left = 0x8000;
  1594. chip->pcm_mixer[idx].right = 0x8000;
  1595. chip->pcm_mixer[idx].ctl = kctl;
  1596. substream = substream->next;
  1597. }
  1598. return 0;
  1599. }
  1600. /*
  1601. * timer
  1602. */
  1603. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1604. {
  1605. struct snd_ymfpci *chip;
  1606. unsigned long flags;
  1607. unsigned int count;
  1608. chip = snd_timer_chip(timer);
  1609. count = (timer->sticks << 1) - 1;
  1610. spin_lock_irqsave(&chip->reg_lock, flags);
  1611. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1612. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1613. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1614. return 0;
  1615. }
  1616. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1617. {
  1618. struct snd_ymfpci *chip;
  1619. unsigned long flags;
  1620. chip = snd_timer_chip(timer);
  1621. spin_lock_irqsave(&chip->reg_lock, flags);
  1622. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1623. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1624. return 0;
  1625. }
  1626. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1627. unsigned long *num, unsigned long *den)
  1628. {
  1629. *num = 1;
  1630. *den = 48000;
  1631. return 0;
  1632. }
  1633. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1634. .flags = SNDRV_TIMER_HW_AUTO,
  1635. .resolution = 20833, /* 1/fs = 20.8333...us */
  1636. .ticks = 0x8000,
  1637. .start = snd_ymfpci_timer_start,
  1638. .stop = snd_ymfpci_timer_stop,
  1639. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1640. };
  1641. int __devinit snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1642. {
  1643. struct snd_timer *timer = NULL;
  1644. struct snd_timer_id tid;
  1645. int err;
  1646. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1647. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1648. tid.card = chip->card->number;
  1649. tid.device = device;
  1650. tid.subdevice = 0;
  1651. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1652. strcpy(timer->name, "YMFPCI timer");
  1653. timer->private_data = chip;
  1654. timer->hw = snd_ymfpci_timer_hw;
  1655. }
  1656. chip->timer = timer;
  1657. return err;
  1658. }
  1659. /*
  1660. * proc interface
  1661. */
  1662. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1663. struct snd_info_buffer *buffer)
  1664. {
  1665. struct snd_ymfpci *chip = entry->private_data;
  1666. int i;
  1667. snd_iprintf(buffer, "YMFPCI\n\n");
  1668. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1669. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1670. }
  1671. static int __devinit snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1672. {
  1673. struct snd_info_entry *entry;
  1674. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1675. snd_info_set_text_ops(entry, chip, 1024, snd_ymfpci_proc_read);
  1676. return 0;
  1677. }
  1678. /*
  1679. * initialization routines
  1680. */
  1681. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1682. {
  1683. u8 cmd;
  1684. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1685. #if 0 // force to reset
  1686. if (cmd & 0x03) {
  1687. #endif
  1688. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1689. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1690. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1691. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1692. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1693. #if 0
  1694. }
  1695. #endif
  1696. }
  1697. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1698. {
  1699. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1700. }
  1701. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1702. {
  1703. u32 val;
  1704. int timeout = 1000;
  1705. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1706. if (val)
  1707. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1708. while (timeout-- > 0) {
  1709. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1710. if ((val & 0x00000002) == 0)
  1711. break;
  1712. }
  1713. }
  1714. #include "ymfpci_image.h"
  1715. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1716. {
  1717. int i;
  1718. u16 ctrl;
  1719. unsigned long *inst;
  1720. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1721. snd_ymfpci_disable_dsp(chip);
  1722. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1723. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1724. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1725. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1726. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1727. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1728. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1729. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1730. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1731. /* setup DSP instruction code */
  1732. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1733. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), DspInst[i]);
  1734. /* setup control instruction code */
  1735. switch (chip->device_id) {
  1736. case PCI_DEVICE_ID_YAMAHA_724F:
  1737. case PCI_DEVICE_ID_YAMAHA_740C:
  1738. case PCI_DEVICE_ID_YAMAHA_744:
  1739. case PCI_DEVICE_ID_YAMAHA_754:
  1740. inst = CntrlInst1E;
  1741. break;
  1742. default:
  1743. inst = CntrlInst;
  1744. break;
  1745. }
  1746. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1747. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
  1748. snd_ymfpci_enable_dsp(chip);
  1749. }
  1750. static int __devinit snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1751. {
  1752. long size, playback_ctrl_size;
  1753. int voice, bank, reg;
  1754. u8 *ptr;
  1755. dma_addr_t ptr_addr;
  1756. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1757. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1758. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1759. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1760. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1761. size = ((playback_ctrl_size + 0x00ff) & ~0x00ff) +
  1762. ((chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES + 0x00ff) & ~0x00ff) +
  1763. ((chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES + 0x00ff) & ~0x00ff) +
  1764. ((chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES + 0x00ff) & ~0x00ff) +
  1765. chip->work_size;
  1766. /* work_ptr must be aligned to 256 bytes, but it's already
  1767. covered with the kernel page allocation mechanism */
  1768. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1769. size, &chip->work_ptr) < 0)
  1770. return -ENOMEM;
  1771. ptr = chip->work_ptr.area;
  1772. ptr_addr = chip->work_ptr.addr;
  1773. memset(ptr, 0, size); /* for sure */
  1774. chip->bank_base_playback = ptr;
  1775. chip->bank_base_playback_addr = ptr_addr;
  1776. chip->ctrl_playback = (u32 *)ptr;
  1777. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1778. ptr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1779. ptr_addr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1780. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1781. chip->voices[voice].number = voice;
  1782. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1783. chip->voices[voice].bank_addr = ptr_addr;
  1784. for (bank = 0; bank < 2; bank++) {
  1785. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1786. ptr += chip->bank_size_playback;
  1787. ptr_addr += chip->bank_size_playback;
  1788. }
  1789. }
  1790. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1791. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1792. chip->bank_base_capture = ptr;
  1793. chip->bank_base_capture_addr = ptr_addr;
  1794. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1795. for (bank = 0; bank < 2; bank++) {
  1796. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1797. ptr += chip->bank_size_capture;
  1798. ptr_addr += chip->bank_size_capture;
  1799. }
  1800. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1801. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1802. chip->bank_base_effect = ptr;
  1803. chip->bank_base_effect_addr = ptr_addr;
  1804. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1805. for (bank = 0; bank < 2; bank++) {
  1806. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1807. ptr += chip->bank_size_effect;
  1808. ptr_addr += chip->bank_size_effect;
  1809. }
  1810. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1811. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1812. chip->work_base = ptr;
  1813. chip->work_base_addr = ptr_addr;
  1814. snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
  1815. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1816. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1817. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1818. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1819. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1820. /* S/PDIF output initialization */
  1821. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1822. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1823. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1824. /* S/PDIF input initialization */
  1825. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1826. /* digital mixer setup */
  1827. for (reg = 0x80; reg < 0xc0; reg += 4)
  1828. snd_ymfpci_writel(chip, reg, 0);
  1829. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1830. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1831. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1832. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1833. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1834. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1835. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1836. return 0;
  1837. }
  1838. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1839. {
  1840. u16 ctrl;
  1841. snd_assert(chip != NULL, return -EINVAL);
  1842. if (chip->res_reg_area) { /* don't touch busy hardware */
  1843. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1844. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1845. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1846. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1847. snd_ymfpci_disable_dsp(chip);
  1848. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1849. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1850. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1851. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1852. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1853. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1854. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1855. }
  1856. snd_ymfpci_ac3_done(chip);
  1857. /* Set PCI device to D3 state */
  1858. #if 0
  1859. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1860. * the chip again unless reboot. ACPI bug?
  1861. */
  1862. pci_set_power_state(chip->pci, 3);
  1863. #endif
  1864. #ifdef CONFIG_PM
  1865. vfree(chip->saved_regs);
  1866. #endif
  1867. release_and_free_resource(chip->mpu_res);
  1868. release_and_free_resource(chip->fm_res);
  1869. snd_ymfpci_free_gameport(chip);
  1870. if (chip->reg_area_virt)
  1871. iounmap(chip->reg_area_virt);
  1872. if (chip->work_ptr.area)
  1873. snd_dma_free_pages(&chip->work_ptr);
  1874. if (chip->irq >= 0)
  1875. free_irq(chip->irq, (void *)chip);
  1876. release_and_free_resource(chip->res_reg_area);
  1877. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1878. pci_disable_device(chip->pci);
  1879. kfree(chip);
  1880. return 0;
  1881. }
  1882. static int snd_ymfpci_dev_free(struct snd_device *device)
  1883. {
  1884. struct snd_ymfpci *chip = device->device_data;
  1885. return snd_ymfpci_free(chip);
  1886. }
  1887. #ifdef CONFIG_PM
  1888. static int saved_regs_index[] = {
  1889. /* spdif */
  1890. YDSXGR_SPDIFOUTCTRL,
  1891. YDSXGR_SPDIFOUTSTATUS,
  1892. YDSXGR_SPDIFINCTRL,
  1893. /* volumes */
  1894. YDSXGR_PRIADCLOOPVOL,
  1895. YDSXGR_NATIVEDACINVOL,
  1896. YDSXGR_NATIVEDACOUTVOL,
  1897. // YDSXGR_BUF441OUTVOL,
  1898. YDSXGR_NATIVEADCINVOL,
  1899. YDSXGR_SPDIFLOOPVOL,
  1900. YDSXGR_SPDIFOUTVOL,
  1901. YDSXGR_ZVOUTVOL,
  1902. YDSXGR_LEGACYOUTVOL,
  1903. /* address bases */
  1904. YDSXGR_PLAYCTRLBASE,
  1905. YDSXGR_RECCTRLBASE,
  1906. YDSXGR_EFFCTRLBASE,
  1907. YDSXGR_WORKBASE,
  1908. /* capture set up */
  1909. YDSXGR_MAPOFREC,
  1910. YDSXGR_RECFORMAT,
  1911. YDSXGR_RECSLOTSR,
  1912. YDSXGR_ADCFORMAT,
  1913. YDSXGR_ADCSLOTSR,
  1914. };
  1915. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  1916. int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state)
  1917. {
  1918. struct snd_card *card = pci_get_drvdata(pci);
  1919. struct snd_ymfpci *chip = card->private_data;
  1920. unsigned int i;
  1921. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1922. snd_pcm_suspend_all(chip->pcm);
  1923. snd_pcm_suspend_all(chip->pcm2);
  1924. snd_pcm_suspend_all(chip->pcm_spdif);
  1925. snd_pcm_suspend_all(chip->pcm_4ch);
  1926. snd_ac97_suspend(chip->ac97);
  1927. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1928. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  1929. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  1930. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1931. snd_ymfpci_disable_dsp(chip);
  1932. pci_disable_device(pci);
  1933. pci_save_state(pci);
  1934. return 0;
  1935. }
  1936. int snd_ymfpci_resume(struct pci_dev *pci)
  1937. {
  1938. struct snd_card *card = pci_get_drvdata(pci);
  1939. struct snd_ymfpci *chip = card->private_data;
  1940. unsigned int i;
  1941. pci_restore_state(pci);
  1942. pci_enable_device(pci);
  1943. pci_set_master(pci);
  1944. snd_ymfpci_aclink_reset(pci);
  1945. snd_ymfpci_codec_ready(chip, 0);
  1946. snd_ymfpci_download_image(chip);
  1947. udelay(100);
  1948. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1949. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  1950. snd_ac97_resume(chip->ac97);
  1951. /* start hw again */
  1952. if (chip->start_count > 0) {
  1953. spin_lock_irq(&chip->reg_lock);
  1954. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  1955. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  1956. spin_unlock_irq(&chip->reg_lock);
  1957. }
  1958. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1959. return 0;
  1960. }
  1961. #endif /* CONFIG_PM */
  1962. int __devinit snd_ymfpci_create(struct snd_card *card,
  1963. struct pci_dev * pci,
  1964. unsigned short old_legacy_ctrl,
  1965. struct snd_ymfpci ** rchip)
  1966. {
  1967. struct snd_ymfpci *chip;
  1968. int err;
  1969. static struct snd_device_ops ops = {
  1970. .dev_free = snd_ymfpci_dev_free,
  1971. };
  1972. *rchip = NULL;
  1973. /* enable PCI device */
  1974. if ((err = pci_enable_device(pci)) < 0)
  1975. return err;
  1976. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1977. if (chip == NULL) {
  1978. pci_disable_device(pci);
  1979. return -ENOMEM;
  1980. }
  1981. chip->old_legacy_ctrl = old_legacy_ctrl;
  1982. spin_lock_init(&chip->reg_lock);
  1983. spin_lock_init(&chip->voice_lock);
  1984. init_waitqueue_head(&chip->interrupt_sleep);
  1985. atomic_set(&chip->interrupt_sleep_count, 0);
  1986. chip->card = card;
  1987. chip->pci = pci;
  1988. chip->irq = -1;
  1989. chip->device_id = pci->device;
  1990. pci_read_config_byte(pci, PCI_REVISION_ID, (u8 *)&chip->rev);
  1991. chip->reg_area_phys = pci_resource_start(pci, 0);
  1992. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  1993. pci_set_master(pci);
  1994. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  1995. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  1996. snd_ymfpci_free(chip);
  1997. return -EBUSY;
  1998. }
  1999. if (request_irq(pci->irq, snd_ymfpci_interrupt, SA_INTERRUPT|SA_SHIRQ, "YMFPCI", (void *) chip)) {
  2000. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2001. snd_ymfpci_free(chip);
  2002. return -EBUSY;
  2003. }
  2004. chip->irq = pci->irq;
  2005. snd_ymfpci_aclink_reset(pci);
  2006. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2007. snd_ymfpci_free(chip);
  2008. return -EIO;
  2009. }
  2010. snd_ymfpci_download_image(chip);
  2011. udelay(100); /* seems we need a delay after downloading image.. */
  2012. if (snd_ymfpci_memalloc(chip) < 0) {
  2013. snd_ymfpci_free(chip);
  2014. return -EIO;
  2015. }
  2016. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2017. snd_ymfpci_free(chip);
  2018. return err;
  2019. }
  2020. #ifdef CONFIG_PM
  2021. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2022. if (chip->saved_regs == NULL) {
  2023. snd_ymfpci_free(chip);
  2024. return -ENOMEM;
  2025. }
  2026. #endif
  2027. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2028. snd_ymfpci_free(chip);
  2029. return err;
  2030. }
  2031. snd_ymfpci_proc_init(card, chip);
  2032. snd_card_set_dev(card, &pci->dev);
  2033. *rchip = chip;
  2034. return 0;
  2035. }