irq.c 6.4 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Creative Labs, Inc.
  4. * Routines for IRQ control of EMU10K1 chips
  5. *
  6. * BUGS:
  7. * --
  8. *
  9. * TODO:
  10. * --
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <sound/driver.h>
  28. #include <linux/time.h>
  29. #include <sound/core.h>
  30. #include <sound/emu10k1.h>
  31. irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  32. {
  33. struct snd_emu10k1 *emu = dev_id;
  34. unsigned int status, status2, orig_status, orig_status2;
  35. int handled = 0;
  36. while ((status = inl(emu->port + IPR)) != 0) {
  37. //printk("emu10k1 irq - status = 0x%x\n", status);
  38. orig_status = status;
  39. handled = 1;
  40. if (status & IPR_PCIERROR) {
  41. snd_printk(KERN_ERR "interrupt: PCI error\n");
  42. snd_emu10k1_intr_disable(emu, INTE_PCIERRORENABLE);
  43. status &= ~IPR_PCIERROR;
  44. }
  45. if (status & (IPR_VOLINCR|IPR_VOLDECR|IPR_MUTE)) {
  46. if (emu->hwvol_interrupt)
  47. emu->hwvol_interrupt(emu, status);
  48. else
  49. snd_emu10k1_intr_disable(emu, INTE_VOLINCRENABLE|INTE_VOLDECRENABLE|INTE_MUTEENABLE);
  50. status &= ~(IPR_VOLINCR|IPR_VOLDECR|IPR_MUTE);
  51. }
  52. if (status & IPR_CHANNELLOOP) {
  53. int voice;
  54. int voice_max = status & IPR_CHANNELNUMBERMASK;
  55. u32 val;
  56. struct snd_emu10k1_voice *pvoice = emu->voices;
  57. val = snd_emu10k1_ptr_read(emu, CLIPL, 0);
  58. for (voice = 0; voice <= voice_max; voice++) {
  59. if (voice == 0x20)
  60. val = snd_emu10k1_ptr_read(emu, CLIPH, 0);
  61. if (val & 1) {
  62. if (pvoice->use && pvoice->interrupt != NULL) {
  63. pvoice->interrupt(emu, pvoice);
  64. snd_emu10k1_voice_intr_ack(emu, voice);
  65. } else {
  66. snd_emu10k1_voice_intr_disable(emu, voice);
  67. }
  68. }
  69. val >>= 1;
  70. pvoice++;
  71. }
  72. val = snd_emu10k1_ptr_read(emu, HLIPL, 0);
  73. for (voice = 0; voice <= voice_max; voice++) {
  74. if (voice == 0x20)
  75. val = snd_emu10k1_ptr_read(emu, HLIPH, 0);
  76. if (val & 1) {
  77. if (pvoice->use && pvoice->interrupt != NULL) {
  78. pvoice->interrupt(emu, pvoice);
  79. snd_emu10k1_voice_half_loop_intr_ack(emu, voice);
  80. } else {
  81. snd_emu10k1_voice_half_loop_intr_disable(emu, voice);
  82. }
  83. }
  84. val >>= 1;
  85. pvoice++;
  86. }
  87. status &= ~IPR_CHANNELLOOP;
  88. }
  89. status &= ~IPR_CHANNELNUMBERMASK;
  90. if (status & (IPR_ADCBUFFULL|IPR_ADCBUFHALFFULL)) {
  91. if (emu->capture_interrupt)
  92. emu->capture_interrupt(emu, status);
  93. else
  94. snd_emu10k1_intr_disable(emu, INTE_ADCBUFENABLE);
  95. status &= ~(IPR_ADCBUFFULL|IPR_ADCBUFHALFFULL);
  96. }
  97. if (status & (IPR_MICBUFFULL|IPR_MICBUFHALFFULL)) {
  98. if (emu->capture_mic_interrupt)
  99. emu->capture_mic_interrupt(emu, status);
  100. else
  101. snd_emu10k1_intr_disable(emu, INTE_MICBUFENABLE);
  102. status &= ~(IPR_MICBUFFULL|IPR_MICBUFHALFFULL);
  103. }
  104. if (status & (IPR_EFXBUFFULL|IPR_EFXBUFHALFFULL)) {
  105. if (emu->capture_efx_interrupt)
  106. emu->capture_efx_interrupt(emu, status);
  107. else
  108. snd_emu10k1_intr_disable(emu, INTE_EFXBUFENABLE);
  109. status &= ~(IPR_EFXBUFFULL|IPR_EFXBUFHALFFULL);
  110. }
  111. if (status & (IPR_MIDITRANSBUFEMPTY|IPR_MIDIRECVBUFEMPTY)) {
  112. if (emu->midi.interrupt)
  113. emu->midi.interrupt(emu, status);
  114. else
  115. snd_emu10k1_intr_disable(emu, INTE_MIDITXENABLE|INTE_MIDIRXENABLE);
  116. status &= ~(IPR_MIDITRANSBUFEMPTY|IPR_MIDIRECVBUFEMPTY);
  117. }
  118. if (status & (IPR_A_MIDITRANSBUFEMPTY2|IPR_A_MIDIRECVBUFEMPTY2)) {
  119. if (emu->midi2.interrupt)
  120. emu->midi2.interrupt(emu, status);
  121. else
  122. snd_emu10k1_intr_disable(emu, INTE_A_MIDITXENABLE2|INTE_A_MIDIRXENABLE2);
  123. status &= ~(IPR_A_MIDITRANSBUFEMPTY2|IPR_A_MIDIRECVBUFEMPTY2);
  124. }
  125. if (status & IPR_INTERVALTIMER) {
  126. if (emu->timer)
  127. snd_timer_interrupt(emu->timer, emu->timer->sticks);
  128. else
  129. snd_emu10k1_intr_disable(emu, INTE_INTERVALTIMERENB);
  130. status &= ~IPR_INTERVALTIMER;
  131. }
  132. if (status & (IPR_GPSPDIFSTATUSCHANGE|IPR_CDROMSTATUSCHANGE)) {
  133. if (emu->spdif_interrupt)
  134. emu->spdif_interrupt(emu, status);
  135. else
  136. snd_emu10k1_intr_disable(emu, INTE_GPSPDIFENABLE|INTE_CDSPDIFENABLE);
  137. status &= ~(IPR_GPSPDIFSTATUSCHANGE|IPR_CDROMSTATUSCHANGE);
  138. }
  139. if (status & IPR_FXDSP) {
  140. if (emu->dsp_interrupt)
  141. emu->dsp_interrupt(emu);
  142. else
  143. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  144. status &= ~IPR_FXDSP;
  145. }
  146. if (status & IPR_P16V) {
  147. while ((status2 = inl(emu->port + IPR2)) != 0) {
  148. u32 mask = INTE2_PLAYBACK_CH_0_LOOP; /* Full Loop */
  149. struct snd_emu10k1_voice *pvoice = &(emu->p16v_voices[0]);
  150. struct snd_emu10k1_voice *cvoice = &(emu->p16v_capture_voice);
  151. //printk(KERN_INFO "status2=0x%x\n", status2);
  152. orig_status2 = status2;
  153. if(status2 & mask) {
  154. if(pvoice->use) {
  155. snd_pcm_period_elapsed(pvoice->epcm->substream);
  156. } else {
  157. snd_printk(KERN_ERR "p16v: status: 0x%08x, mask=0x%08x, pvoice=%p, use=%d\n", status2, mask, pvoice, pvoice->use);
  158. }
  159. }
  160. if(status2 & 0x110000) {
  161. //printk(KERN_INFO "capture int found\n");
  162. if(cvoice->use) {
  163. //printk(KERN_INFO "capture period_elapsed\n");
  164. snd_pcm_period_elapsed(cvoice->epcm->substream);
  165. }
  166. }
  167. outl(orig_status2, emu->port + IPR2); /* ack all */
  168. }
  169. status &= ~IPR_P16V;
  170. }
  171. if (status) {
  172. unsigned int bits;
  173. snd_printk(KERN_ERR "emu10k1: unhandled interrupt: 0x%08x\n", status);
  174. //make sure any interrupts we don't handle are disabled:
  175. bits = INTE_FXDSPENABLE |
  176. INTE_PCIERRORENABLE |
  177. INTE_VOLINCRENABLE |
  178. INTE_VOLDECRENABLE |
  179. INTE_MUTEENABLE |
  180. INTE_MICBUFENABLE |
  181. INTE_ADCBUFENABLE |
  182. INTE_EFXBUFENABLE |
  183. INTE_GPSPDIFENABLE |
  184. INTE_CDSPDIFENABLE |
  185. INTE_INTERVALTIMERENB |
  186. INTE_MIDITXENABLE |
  187. INTE_MIDIRXENABLE;
  188. if (emu->audigy)
  189. bits |= INTE_A_MIDITXENABLE2 | INTE_A_MIDIRXENABLE2;
  190. snd_emu10k1_intr_disable(emu, bits);
  191. }
  192. outl(orig_status, emu->port + IPR); /* ack all */
  193. }
  194. return IRQ_RETVAL(handled);
  195. }