sonicvibes.c 80 KB

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  1. /*****************************************************************************/
  2. /*
  3. * sonicvibes.c -- S3 Sonic Vibes audio driver.
  4. *
  5. * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. * Special thanks to David C. Niemi
  22. *
  23. *
  24. * Module command line parameters:
  25. * none so far
  26. *
  27. *
  28. * Supported devices:
  29. * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
  30. * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
  31. * /dev/midi simple MIDI UART interface, no ioctl
  32. *
  33. * The card has both an FM and a Wavetable synth, but I have to figure
  34. * out first how to drive them...
  35. *
  36. * Revision history
  37. * 06.05.1998 0.1 Initial release
  38. * 10.05.1998 0.2 Fixed many bugs, esp. ADC rate calculation
  39. * First stab at a simple midi interface (no bells&whistles)
  40. * 13.05.1998 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
  41. * set_dac_rate in the FMODE_WRITE case in sv_open
  42. * Fix hwptr out of bounds (now mpg123 works)
  43. * 14.05.1998 0.4 Don't allow excessive interrupt rates
  44. * 08.06.1998 0.5 First release using Alan Cox' soundcore instead of miscdevice
  45. * 03.08.1998 0.6 Do not include modversions.h
  46. * Now mixer behaviour can basically be selected between
  47. * "OSS documented" and "OSS actual" behaviour
  48. * 31.08.1998 0.7 Fix realplayer problems - dac.count issues
  49. * 10.12.1998 0.8 Fix drain_dac trying to wait on not yet initialized DMA
  50. * 16.12.1998 0.9 Fix a few f_file & FMODE_ bugs
  51. * 06.01.1999 0.10 remove the silly SA_INTERRUPT flag.
  52. * hopefully killed the egcs section type conflict
  53. * 12.03.1999 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
  54. * reported by Johan Maes <joma@telindus.be>
  55. * 22.03.1999 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
  56. * read/write cannot be executed
  57. * 05.04.1999 0.13 added code to sv_read and sv_write which should detect
  58. * lockups of the sound chip and revive it. This is basically
  59. * an ugly hack, but at least applications using this driver
  60. * won't hang forever. I don't know why these lockups happen,
  61. * it might well be the motherboard chipset (an early 486 PCI
  62. * board with ALI chipset), since every busmastering 100MB
  63. * ethernet card I've tried (Realtek 8139 and Macronix tulip clone)
  64. * exhibit similar behaviour (they work for a couple of packets
  65. * and then lock up and can be revived by ifconfig down/up).
  66. * 07.04.1999 0.14 implemented the following ioctl's: SOUND_PCM_READ_RATE,
  67. * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
  68. * Alpha fixes reported by Peter Jones <pjones@redhat.com>
  69. * Note: dmaio hack might still be wrong on archs other than i386
  70. * 15.06.1999 0.15 Fix bad allocation bug.
  71. * Thanks to Deti Fliegl <fliegl@in.tum.de>
  72. * 28.06.1999 0.16 Add pci_set_master
  73. * 03.08.1999 0.17 adapt to Linus' new __setup/__initcall
  74. * added kernel command line options "sonicvibes=reverb" and "sonicvibesdmaio=dmaioaddr"
  75. * 12.08.1999 0.18 module_init/__setup fixes
  76. * 24.08.1999 0.19 get rid of the dmaio kludge, replace with allocate_resource
  77. * 31.08.1999 0.20 add spin_lock_init
  78. * use new resource allocation to allocate DDMA IO space
  79. * replaced current->state = x with set_current_state(x)
  80. * 03.09.1999 0.21 change read semantics for MIDI to match
  81. * OSS more closely; remove possible wakeup race
  82. * 28.10.1999 0.22 More waitqueue races fixed
  83. * 01.12.1999 0.23 New argument to allocate_resource
  84. * 07.12.1999 0.24 More allocate_resource semantics change
  85. * 08.01.2000 0.25 Prevent some ioctl's from returning bad count values on underrun/overrun;
  86. * Tim Janik's BSE (Bedevilled Sound Engine) found this
  87. * use Martin Mares' pci_assign_resource
  88. * 07.02.2000 0.26 Use pci_alloc_consistent and pci_register_driver
  89. * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
  90. * 12.12.2000 0.28 More dma buffer initializations, patch from
  91. * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
  92. * 31.01.2001 0.29 Register/Unregister gameport
  93. * Fix SETTRIGGER non OSS API conformity
  94. * 18.05.2001 0.30 PCI probing and error values cleaned up by Marcus
  95. * Meissner <mm@caldera.de>
  96. * 03.01.2003 0.31 open_mode fixes from Georg Acher <acher@in.tum.de>
  97. *
  98. */
  99. /*****************************************************************************/
  100. #include <linux/module.h>
  101. #include <linux/string.h>
  102. #include <linux/ioport.h>
  103. #include <linux/interrupt.h>
  104. #include <linux/wait.h>
  105. #include <linux/mm.h>
  106. #include <linux/delay.h>
  107. #include <linux/sound.h>
  108. #include <linux/slab.h>
  109. #include <linux/soundcard.h>
  110. #include <linux/pci.h>
  111. #include <linux/init.h>
  112. #include <linux/poll.h>
  113. #include <linux/spinlock.h>
  114. #include <linux/smp_lock.h>
  115. #include <linux/gameport.h>
  116. #include <asm/io.h>
  117. #include <asm/uaccess.h>
  118. #include "dm.h"
  119. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  120. #define SUPPORT_JOYSTICK 1
  121. #endif
  122. /* --------------------------------------------------------------------- */
  123. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  124. /* --------------------------------------------------------------------- */
  125. #ifndef PCI_VENDOR_ID_S3
  126. #define PCI_VENDOR_ID_S3 0x5333
  127. #endif
  128. #ifndef PCI_DEVICE_ID_S3_SONICVIBES
  129. #define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
  130. #endif
  131. #define SV_MAGIC ((PCI_VENDOR_ID_S3<<16)|PCI_DEVICE_ID_S3_SONICVIBES)
  132. #define SV_EXTENT_SB 0x10
  133. #define SV_EXTENT_ENH 0x10
  134. #define SV_EXTENT_SYNTH 0x4
  135. #define SV_EXTENT_MIDI 0x4
  136. #define SV_EXTENT_GAME 0x8
  137. #define SV_EXTENT_DMA 0x10
  138. /*
  139. * we are not a bridge and thus use a resource for DDMA that is used for bridges but
  140. * left empty for normal devices
  141. */
  142. #define RESOURCE_SB 0
  143. #define RESOURCE_ENH 1
  144. #define RESOURCE_SYNTH 2
  145. #define RESOURCE_MIDI 3
  146. #define RESOURCE_GAME 4
  147. #define RESOURCE_DDMA 7
  148. #define SV_MIDI_DATA 0
  149. #define SV_MIDI_COMMAND 1
  150. #define SV_MIDI_STATUS 1
  151. #define SV_DMA_ADDR0 0
  152. #define SV_DMA_ADDR1 1
  153. #define SV_DMA_ADDR2 2
  154. #define SV_DMA_ADDR3 3
  155. #define SV_DMA_COUNT0 4
  156. #define SV_DMA_COUNT1 5
  157. #define SV_DMA_COUNT2 6
  158. #define SV_DMA_MODE 0xb
  159. #define SV_DMA_RESET 0xd
  160. #define SV_DMA_MASK 0xf
  161. /*
  162. * DONT reset the DMA controllers unless you understand
  163. * the reset semantics. Assuming reset semantics as in
  164. * the 8237 does not work.
  165. */
  166. #define DMA_MODE_AUTOINIT 0x10
  167. #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
  168. #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
  169. #define SV_CODEC_CONTROL 0
  170. #define SV_CODEC_INTMASK 1
  171. #define SV_CODEC_STATUS 2
  172. #define SV_CODEC_IADDR 4
  173. #define SV_CODEC_IDATA 5
  174. #define SV_CCTRL_RESET 0x80
  175. #define SV_CCTRL_INTADRIVE 0x20
  176. #define SV_CCTRL_WAVETABLE 0x08
  177. #define SV_CCTRL_REVERB 0x04
  178. #define SV_CCTRL_ENHANCED 0x01
  179. #define SV_CINTMASK_DMAA 0x01
  180. #define SV_CINTMASK_DMAC 0x04
  181. #define SV_CINTMASK_SPECIAL 0x08
  182. #define SV_CINTMASK_UPDOWN 0x40
  183. #define SV_CINTMASK_MIDI 0x80
  184. #define SV_CSTAT_DMAA 0x01
  185. #define SV_CSTAT_DMAC 0x04
  186. #define SV_CSTAT_SPECIAL 0x08
  187. #define SV_CSTAT_UPDOWN 0x40
  188. #define SV_CSTAT_MIDI 0x80
  189. #define SV_CIADDR_TRD 0x80
  190. #define SV_CIADDR_MCE 0x40
  191. /* codec indirect registers */
  192. #define SV_CIMIX_ADCINL 0x00
  193. #define SV_CIMIX_ADCINR 0x01
  194. #define SV_CIMIX_AUX1INL 0x02
  195. #define SV_CIMIX_AUX1INR 0x03
  196. #define SV_CIMIX_CDINL 0x04
  197. #define SV_CIMIX_CDINR 0x05
  198. #define SV_CIMIX_LINEINL 0x06
  199. #define SV_CIMIX_LINEINR 0x07
  200. #define SV_CIMIX_MICIN 0x08
  201. #define SV_CIMIX_SYNTHINL 0x0A
  202. #define SV_CIMIX_SYNTHINR 0x0B
  203. #define SV_CIMIX_AUX2INL 0x0C
  204. #define SV_CIMIX_AUX2INR 0x0D
  205. #define SV_CIMIX_ANALOGINL 0x0E
  206. #define SV_CIMIX_ANALOGINR 0x0F
  207. #define SV_CIMIX_PCMINL 0x10
  208. #define SV_CIMIX_PCMINR 0x11
  209. #define SV_CIGAMECONTROL 0x09
  210. #define SV_CIDATAFMT 0x12
  211. #define SV_CIENABLE 0x13
  212. #define SV_CIUPDOWN 0x14
  213. #define SV_CIREVISION 0x15
  214. #define SV_CIADCOUTPUT 0x16
  215. #define SV_CIDMAABASECOUNT1 0x18
  216. #define SV_CIDMAABASECOUNT0 0x19
  217. #define SV_CIDMACBASECOUNT1 0x1c
  218. #define SV_CIDMACBASECOUNT0 0x1d
  219. #define SV_CIPCMSR0 0x1e
  220. #define SV_CIPCMSR1 0x1f
  221. #define SV_CISYNTHSR0 0x20
  222. #define SV_CISYNTHSR1 0x21
  223. #define SV_CIADCCLKSOURCE 0x22
  224. #define SV_CIADCALTSR 0x23
  225. #define SV_CIADCPLLM 0x24
  226. #define SV_CIADCPLLN 0x25
  227. #define SV_CISYNTHPLLM 0x26
  228. #define SV_CISYNTHPLLN 0x27
  229. #define SV_CIUARTCONTROL 0x2a
  230. #define SV_CIDRIVECONTROL 0x2b
  231. #define SV_CISRSSPACE 0x2c
  232. #define SV_CISRSCENTER 0x2d
  233. #define SV_CIWAVETABLESRC 0x2e
  234. #define SV_CIANALOGPWRDOWN 0x30
  235. #define SV_CIDIGITALPWRDOWN 0x31
  236. #define SV_CIMIX_ADCSRC_CD 0x20
  237. #define SV_CIMIX_ADCSRC_DAC 0x40
  238. #define SV_CIMIX_ADCSRC_AUX2 0x60
  239. #define SV_CIMIX_ADCSRC_LINE 0x80
  240. #define SV_CIMIX_ADCSRC_AUX1 0xa0
  241. #define SV_CIMIX_ADCSRC_MIC 0xc0
  242. #define SV_CIMIX_ADCSRC_MIXOUT 0xe0
  243. #define SV_CIMIX_ADCSRC_MASK 0xe0
  244. #define SV_CFMT_STEREO 0x01
  245. #define SV_CFMT_16BIT 0x02
  246. #define SV_CFMT_MASK 0x03
  247. #define SV_CFMT_ASHIFT 0
  248. #define SV_CFMT_CSHIFT 4
  249. static const unsigned sample_size[] = { 1, 2, 2, 4 };
  250. static const unsigned sample_shift[] = { 0, 1, 1, 2 };
  251. #define SV_CENABLE_PPE 0x4
  252. #define SV_CENABLE_RE 0x2
  253. #define SV_CENABLE_PE 0x1
  254. /* MIDI buffer sizes */
  255. #define MIDIINBUF 256
  256. #define MIDIOUTBUF 256
  257. #define FMODE_MIDI_SHIFT 2
  258. #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
  259. #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
  260. #define FMODE_DMFM 0x10
  261. /* --------------------------------------------------------------------- */
  262. struct sv_state {
  263. /* magic */
  264. unsigned int magic;
  265. /* list of sonicvibes devices */
  266. struct list_head devs;
  267. /* the corresponding pci_dev structure */
  268. struct pci_dev *dev;
  269. /* soundcore stuff */
  270. int dev_audio;
  271. int dev_mixer;
  272. int dev_midi;
  273. int dev_dmfm;
  274. /* hardware resources */
  275. unsigned long iosb, ioenh, iosynth, iomidi; /* long for SPARC */
  276. unsigned int iodmaa, iodmac, irq;
  277. /* mixer stuff */
  278. struct {
  279. unsigned int modcnt;
  280. #ifndef OSS_DOCUMENTED_MIXER_SEMANTICS
  281. unsigned short vol[13];
  282. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  283. } mix;
  284. /* wave stuff */
  285. unsigned int rateadc, ratedac;
  286. unsigned char fmt, enable;
  287. spinlock_t lock;
  288. struct semaphore open_sem;
  289. mode_t open_mode;
  290. wait_queue_head_t open_wait;
  291. struct dmabuf {
  292. void *rawbuf;
  293. dma_addr_t dmaaddr;
  294. unsigned buforder;
  295. unsigned numfrag;
  296. unsigned fragshift;
  297. unsigned hwptr, swptr;
  298. unsigned total_bytes;
  299. int count;
  300. unsigned error; /* over/underrun */
  301. wait_queue_head_t wait;
  302. /* redundant, but makes calculations easier */
  303. unsigned fragsize;
  304. unsigned dmasize;
  305. unsigned fragsamples;
  306. /* OSS stuff */
  307. unsigned mapped:1;
  308. unsigned ready:1;
  309. unsigned endcleared:1;
  310. unsigned enabled:1;
  311. unsigned ossfragshift;
  312. int ossmaxfrags;
  313. unsigned subdivision;
  314. } dma_dac, dma_adc;
  315. /* midi stuff */
  316. struct {
  317. unsigned ird, iwr, icnt;
  318. unsigned ord, owr, ocnt;
  319. wait_queue_head_t iwait;
  320. wait_queue_head_t owait;
  321. struct timer_list timer;
  322. unsigned char ibuf[MIDIINBUF];
  323. unsigned char obuf[MIDIOUTBUF];
  324. } midi;
  325. #if SUPPORT_JOYSTICK
  326. struct gameport *gameport;
  327. #endif
  328. };
  329. /* --------------------------------------------------------------------- */
  330. static LIST_HEAD(devs);
  331. static unsigned long wavetable_mem;
  332. /* --------------------------------------------------------------------- */
  333. static inline unsigned ld2(unsigned int x)
  334. {
  335. unsigned r = 0;
  336. if (x >= 0x10000) {
  337. x >>= 16;
  338. r += 16;
  339. }
  340. if (x >= 0x100) {
  341. x >>= 8;
  342. r += 8;
  343. }
  344. if (x >= 0x10) {
  345. x >>= 4;
  346. r += 4;
  347. }
  348. if (x >= 4) {
  349. x >>= 2;
  350. r += 2;
  351. }
  352. if (x >= 2)
  353. r++;
  354. return r;
  355. }
  356. /*
  357. * hweightN: returns the hamming weight (i.e. the number
  358. * of bits set) of a N-bit word
  359. */
  360. #ifdef hweight32
  361. #undef hweight32
  362. #endif
  363. static inline unsigned int hweight32(unsigned int w)
  364. {
  365. unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
  366. res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
  367. res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F);
  368. res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF);
  369. return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF);
  370. }
  371. /* --------------------------------------------------------------------- */
  372. /*
  373. * Why use byte IO? Nobody knows, but S3 does it also in their Windows driver.
  374. */
  375. #undef DMABYTEIO
  376. static void set_dmaa(struct sv_state *s, unsigned int addr, unsigned int count)
  377. {
  378. #ifdef DMABYTEIO
  379. unsigned io = s->iodmaa, u;
  380. count--;
  381. for (u = 4; u > 0; u--, addr >>= 8, io++)
  382. outb(addr & 0xff, io);
  383. for (u = 3; u > 0; u--, count >>= 8, io++)
  384. outb(count & 0xff, io);
  385. #else /* DMABYTEIO */
  386. count--;
  387. outl(addr, s->iodmaa + SV_DMA_ADDR0);
  388. outl(count, s->iodmaa + SV_DMA_COUNT0);
  389. #endif /* DMABYTEIO */
  390. outb(0x18, s->iodmaa + SV_DMA_MODE);
  391. }
  392. static void set_dmac(struct sv_state *s, unsigned int addr, unsigned int count)
  393. {
  394. #ifdef DMABYTEIO
  395. unsigned io = s->iodmac, u;
  396. count >>= 1;
  397. count--;
  398. for (u = 4; u > 0; u--, addr >>= 8, io++)
  399. outb(addr & 0xff, io);
  400. for (u = 3; u > 0; u--, count >>= 8, io++)
  401. outb(count & 0xff, io);
  402. #else /* DMABYTEIO */
  403. count >>= 1;
  404. count--;
  405. outl(addr, s->iodmac + SV_DMA_ADDR0);
  406. outl(count, s->iodmac + SV_DMA_COUNT0);
  407. #endif /* DMABYTEIO */
  408. outb(0x14, s->iodmac + SV_DMA_MODE);
  409. }
  410. static inline unsigned get_dmaa(struct sv_state *s)
  411. {
  412. #ifdef DMABYTEIO
  413. unsigned io = s->iodmaa+6, v = 0, u;
  414. for (u = 3; u > 0; u--, io--) {
  415. v <<= 8;
  416. v |= inb(io);
  417. }
  418. return v + 1;
  419. #else /* DMABYTEIO */
  420. return (inl(s->iodmaa + SV_DMA_COUNT0) & 0xffffff) + 1;
  421. #endif /* DMABYTEIO */
  422. }
  423. static inline unsigned get_dmac(struct sv_state *s)
  424. {
  425. #ifdef DMABYTEIO
  426. unsigned io = s->iodmac+6, v = 0, u;
  427. for (u = 3; u > 0; u--, io--) {
  428. v <<= 8;
  429. v |= inb(io);
  430. }
  431. return (v + 1) << 1;
  432. #else /* DMABYTEIO */
  433. return ((inl(s->iodmac + SV_DMA_COUNT0) & 0xffffff) + 1) << 1;
  434. #endif /* DMABYTEIO */
  435. }
  436. static void wrindir(struct sv_state *s, unsigned char idx, unsigned char data)
  437. {
  438. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  439. udelay(10);
  440. outb(data, s->ioenh + SV_CODEC_IDATA);
  441. udelay(10);
  442. }
  443. static unsigned char rdindir(struct sv_state *s, unsigned char idx)
  444. {
  445. unsigned char v;
  446. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  447. udelay(10);
  448. v = inb(s->ioenh + SV_CODEC_IDATA);
  449. udelay(10);
  450. return v;
  451. }
  452. static void set_fmt(struct sv_state *s, unsigned char mask, unsigned char data)
  453. {
  454. unsigned long flags;
  455. spin_lock_irqsave(&s->lock, flags);
  456. outb(SV_CIDATAFMT | SV_CIADDR_MCE, s->ioenh + SV_CODEC_IADDR);
  457. if (mask) {
  458. s->fmt = inb(s->ioenh + SV_CODEC_IDATA);
  459. udelay(10);
  460. }
  461. s->fmt = (s->fmt & mask) | data;
  462. outb(s->fmt, s->ioenh + SV_CODEC_IDATA);
  463. udelay(10);
  464. outb(0, s->ioenh + SV_CODEC_IADDR);
  465. spin_unlock_irqrestore(&s->lock, flags);
  466. udelay(10);
  467. }
  468. static void frobindir(struct sv_state *s, unsigned char idx, unsigned char mask, unsigned char data)
  469. {
  470. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  471. udelay(10);
  472. outb((inb(s->ioenh + SV_CODEC_IDATA) & mask) ^ data, s->ioenh + SV_CODEC_IDATA);
  473. udelay(10);
  474. }
  475. #define REFFREQUENCY 24576000
  476. #define ADCMULT 512
  477. #define FULLRATE 48000
  478. static unsigned setpll(struct sv_state *s, unsigned char reg, unsigned rate)
  479. {
  480. unsigned long flags;
  481. unsigned char r, m=0, n=0;
  482. unsigned xm, xn, xr, xd, metric = ~0U;
  483. /* the warnings about m and n used uninitialized are bogus and may safely be ignored */
  484. if (rate < 625000/ADCMULT)
  485. rate = 625000/ADCMULT;
  486. if (rate > 150000000/ADCMULT)
  487. rate = 150000000/ADCMULT;
  488. /* slight violation of specs, needed for continuous sampling rates */
  489. for (r = 0; rate < 75000000/ADCMULT; r += 0x20, rate <<= 1);
  490. for (xn = 3; xn < 35; xn++)
  491. for (xm = 3; xm < 130; xm++) {
  492. xr = REFFREQUENCY/ADCMULT * xm / xn;
  493. xd = abs((signed)(xr - rate));
  494. if (xd < metric) {
  495. metric = xd;
  496. m = xm - 2;
  497. n = xn - 2;
  498. }
  499. }
  500. reg &= 0x3f;
  501. spin_lock_irqsave(&s->lock, flags);
  502. outb(reg, s->ioenh + SV_CODEC_IADDR);
  503. udelay(10);
  504. outb(m, s->ioenh + SV_CODEC_IDATA);
  505. udelay(10);
  506. outb(reg+1, s->ioenh + SV_CODEC_IADDR);
  507. udelay(10);
  508. outb(r | n, s->ioenh + SV_CODEC_IDATA);
  509. spin_unlock_irqrestore(&s->lock, flags);
  510. udelay(10);
  511. return (REFFREQUENCY/ADCMULT * (m + 2) / (n + 2)) >> ((r >> 5) & 7);
  512. }
  513. #if 0
  514. static unsigned getpll(struct sv_state *s, unsigned char reg)
  515. {
  516. unsigned long flags;
  517. unsigned char m, n;
  518. reg &= 0x3f;
  519. spin_lock_irqsave(&s->lock, flags);
  520. outb(reg, s->ioenh + SV_CODEC_IADDR);
  521. udelay(10);
  522. m = inb(s->ioenh + SV_CODEC_IDATA);
  523. udelay(10);
  524. outb(reg+1, s->ioenh + SV_CODEC_IADDR);
  525. udelay(10);
  526. n = inb(s->ioenh + SV_CODEC_IDATA);
  527. spin_unlock_irqrestore(&s->lock, flags);
  528. udelay(10);
  529. return (REFFREQUENCY/ADCMULT * (m + 2) / ((n & 0x1f) + 2)) >> ((n >> 5) & 7);
  530. }
  531. #endif
  532. static void set_dac_rate(struct sv_state *s, unsigned rate)
  533. {
  534. unsigned div;
  535. unsigned long flags;
  536. if (rate > 48000)
  537. rate = 48000;
  538. if (rate < 4000)
  539. rate = 4000;
  540. div = (rate * 65536 + FULLRATE/2) / FULLRATE;
  541. if (div > 65535)
  542. div = 65535;
  543. spin_lock_irqsave(&s->lock, flags);
  544. wrindir(s, SV_CIPCMSR1, div >> 8);
  545. wrindir(s, SV_CIPCMSR0, div);
  546. spin_unlock_irqrestore(&s->lock, flags);
  547. s->ratedac = (div * FULLRATE + 32768) / 65536;
  548. }
  549. static void set_adc_rate(struct sv_state *s, unsigned rate)
  550. {
  551. unsigned long flags;
  552. unsigned rate1, rate2, div;
  553. if (rate > 48000)
  554. rate = 48000;
  555. if (rate < 4000)
  556. rate = 4000;
  557. rate1 = setpll(s, SV_CIADCPLLM, rate);
  558. div = (48000 + rate/2) / rate;
  559. if (div > 8)
  560. div = 8;
  561. rate2 = (48000 + div/2) / div;
  562. spin_lock_irqsave(&s->lock, flags);
  563. wrindir(s, SV_CIADCALTSR, (div-1) << 4);
  564. if (abs((signed)(rate-rate2)) <= abs((signed)(rate-rate1))) {
  565. wrindir(s, SV_CIADCCLKSOURCE, 0x10);
  566. s->rateadc = rate2;
  567. } else {
  568. wrindir(s, SV_CIADCCLKSOURCE, 0x00);
  569. s->rateadc = rate1;
  570. }
  571. spin_unlock_irqrestore(&s->lock, flags);
  572. }
  573. /* --------------------------------------------------------------------- */
  574. static inline void stop_adc(struct sv_state *s)
  575. {
  576. unsigned long flags;
  577. spin_lock_irqsave(&s->lock, flags);
  578. s->enable &= ~SV_CENABLE_RE;
  579. wrindir(s, SV_CIENABLE, s->enable);
  580. spin_unlock_irqrestore(&s->lock, flags);
  581. }
  582. static inline void stop_dac(struct sv_state *s)
  583. {
  584. unsigned long flags;
  585. spin_lock_irqsave(&s->lock, flags);
  586. s->enable &= ~(SV_CENABLE_PPE | SV_CENABLE_PE);
  587. wrindir(s, SV_CIENABLE, s->enable);
  588. spin_unlock_irqrestore(&s->lock, flags);
  589. }
  590. static void start_dac(struct sv_state *s)
  591. {
  592. unsigned long flags;
  593. spin_lock_irqsave(&s->lock, flags);
  594. if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
  595. s->enable = (s->enable & ~SV_CENABLE_PPE) | SV_CENABLE_PE;
  596. wrindir(s, SV_CIENABLE, s->enable);
  597. }
  598. spin_unlock_irqrestore(&s->lock, flags);
  599. }
  600. static void start_adc(struct sv_state *s)
  601. {
  602. unsigned long flags;
  603. spin_lock_irqsave(&s->lock, flags);
  604. if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
  605. && s->dma_adc.ready) {
  606. s->enable |= SV_CENABLE_RE;
  607. wrindir(s, SV_CIENABLE, s->enable);
  608. }
  609. spin_unlock_irqrestore(&s->lock, flags);
  610. }
  611. /* --------------------------------------------------------------------- */
  612. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  613. #define DMABUF_MINORDER 1
  614. static void dealloc_dmabuf(struct sv_state *s, struct dmabuf *db)
  615. {
  616. struct page *page, *pend;
  617. if (db->rawbuf) {
  618. /* undo marking the pages as reserved */
  619. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  620. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  621. ClearPageReserved(page);
  622. pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
  623. }
  624. db->rawbuf = NULL;
  625. db->mapped = db->ready = 0;
  626. }
  627. /* DMAA is used for playback, DMAC is used for recording */
  628. static int prog_dmabuf(struct sv_state *s, unsigned rec)
  629. {
  630. struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
  631. unsigned rate = rec ? s->rateadc : s->ratedac;
  632. int order;
  633. unsigned bytepersec;
  634. unsigned bufs;
  635. struct page *page, *pend;
  636. unsigned char fmt;
  637. unsigned long flags;
  638. spin_lock_irqsave(&s->lock, flags);
  639. fmt = s->fmt;
  640. if (rec) {
  641. s->enable &= ~SV_CENABLE_RE;
  642. fmt >>= SV_CFMT_CSHIFT;
  643. } else {
  644. s->enable &= ~SV_CENABLE_PE;
  645. fmt >>= SV_CFMT_ASHIFT;
  646. }
  647. wrindir(s, SV_CIENABLE, s->enable);
  648. spin_unlock_irqrestore(&s->lock, flags);
  649. fmt &= SV_CFMT_MASK;
  650. db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
  651. if (!db->rawbuf) {
  652. db->ready = db->mapped = 0;
  653. for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
  654. if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
  655. break;
  656. if (!db->rawbuf)
  657. return -ENOMEM;
  658. db->buforder = order;
  659. if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
  660. printk(KERN_DEBUG "sv: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
  661. virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
  662. if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
  663. printk(KERN_DEBUG "sv: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
  664. virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
  665. /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
  666. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  667. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  668. SetPageReserved(page);
  669. }
  670. bytepersec = rate << sample_shift[fmt];
  671. bufs = PAGE_SIZE << db->buforder;
  672. if (db->ossfragshift) {
  673. if ((1000 << db->ossfragshift) < bytepersec)
  674. db->fragshift = ld2(bytepersec/1000);
  675. else
  676. db->fragshift = db->ossfragshift;
  677. } else {
  678. db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
  679. if (db->fragshift < 3)
  680. db->fragshift = 3;
  681. }
  682. db->numfrag = bufs >> db->fragshift;
  683. while (db->numfrag < 4 && db->fragshift > 3) {
  684. db->fragshift--;
  685. db->numfrag = bufs >> db->fragshift;
  686. }
  687. db->fragsize = 1 << db->fragshift;
  688. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  689. db->numfrag = db->ossmaxfrags;
  690. db->fragsamples = db->fragsize >> sample_shift[fmt];
  691. db->dmasize = db->numfrag << db->fragshift;
  692. memset(db->rawbuf, (fmt & SV_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
  693. spin_lock_irqsave(&s->lock, flags);
  694. if (rec) {
  695. set_dmac(s, db->dmaaddr, db->numfrag << db->fragshift);
  696. /* program enhanced mode registers */
  697. wrindir(s, SV_CIDMACBASECOUNT1, (db->fragsamples-1) >> 8);
  698. wrindir(s, SV_CIDMACBASECOUNT0, db->fragsamples-1);
  699. } else {
  700. set_dmaa(s, db->dmaaddr, db->numfrag << db->fragshift);
  701. /* program enhanced mode registers */
  702. wrindir(s, SV_CIDMAABASECOUNT1, (db->fragsamples-1) >> 8);
  703. wrindir(s, SV_CIDMAABASECOUNT0, db->fragsamples-1);
  704. }
  705. spin_unlock_irqrestore(&s->lock, flags);
  706. db->enabled = 1;
  707. db->ready = 1;
  708. return 0;
  709. }
  710. static inline void clear_advance(struct sv_state *s)
  711. {
  712. unsigned char c = (s->fmt & (SV_CFMT_16BIT << SV_CFMT_ASHIFT)) ? 0 : 0x80;
  713. unsigned char *buf = s->dma_dac.rawbuf;
  714. unsigned bsize = s->dma_dac.dmasize;
  715. unsigned bptr = s->dma_dac.swptr;
  716. unsigned len = s->dma_dac.fragsize;
  717. if (bptr + len > bsize) {
  718. unsigned x = bsize - bptr;
  719. memset(buf + bptr, c, x);
  720. bptr = 0;
  721. len -= x;
  722. }
  723. memset(buf + bptr, c, len);
  724. }
  725. /* call with spinlock held! */
  726. static void sv_update_ptr(struct sv_state *s)
  727. {
  728. unsigned hwptr;
  729. int diff;
  730. /* update ADC pointer */
  731. if (s->dma_adc.ready) {
  732. hwptr = (s->dma_adc.dmasize - get_dmac(s)) % s->dma_adc.dmasize;
  733. diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
  734. s->dma_adc.hwptr = hwptr;
  735. s->dma_adc.total_bytes += diff;
  736. s->dma_adc.count += diff;
  737. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  738. wake_up(&s->dma_adc.wait);
  739. if (!s->dma_adc.mapped) {
  740. if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
  741. s->enable &= ~SV_CENABLE_RE;
  742. wrindir(s, SV_CIENABLE, s->enable);
  743. s->dma_adc.error++;
  744. }
  745. }
  746. }
  747. /* update DAC pointer */
  748. if (s->dma_dac.ready) {
  749. hwptr = (s->dma_dac.dmasize - get_dmaa(s)) % s->dma_dac.dmasize;
  750. diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
  751. s->dma_dac.hwptr = hwptr;
  752. s->dma_dac.total_bytes += diff;
  753. if (s->dma_dac.mapped) {
  754. s->dma_dac.count += diff;
  755. if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
  756. wake_up(&s->dma_dac.wait);
  757. } else {
  758. s->dma_dac.count -= diff;
  759. if (s->dma_dac.count <= 0) {
  760. s->enable &= ~SV_CENABLE_PE;
  761. wrindir(s, SV_CIENABLE, s->enable);
  762. s->dma_dac.error++;
  763. } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
  764. clear_advance(s);
  765. s->dma_dac.endcleared = 1;
  766. }
  767. if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
  768. wake_up(&s->dma_dac.wait);
  769. }
  770. }
  771. }
  772. /* hold spinlock for the following! */
  773. static void sv_handle_midi(struct sv_state *s)
  774. {
  775. unsigned char ch;
  776. int wake;
  777. wake = 0;
  778. while (!(inb(s->iomidi+1) & 0x80)) {
  779. ch = inb(s->iomidi);
  780. if (s->midi.icnt < MIDIINBUF) {
  781. s->midi.ibuf[s->midi.iwr] = ch;
  782. s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
  783. s->midi.icnt++;
  784. }
  785. wake = 1;
  786. }
  787. if (wake)
  788. wake_up(&s->midi.iwait);
  789. wake = 0;
  790. while (!(inb(s->iomidi+1) & 0x40) && s->midi.ocnt > 0) {
  791. outb(s->midi.obuf[s->midi.ord], s->iomidi);
  792. s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
  793. s->midi.ocnt--;
  794. if (s->midi.ocnt < MIDIOUTBUF-16)
  795. wake = 1;
  796. }
  797. if (wake)
  798. wake_up(&s->midi.owait);
  799. }
  800. static irqreturn_t sv_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  801. {
  802. struct sv_state *s = (struct sv_state *)dev_id;
  803. unsigned int intsrc;
  804. /* fastpath out, to ease interrupt sharing */
  805. intsrc = inb(s->ioenh + SV_CODEC_STATUS);
  806. if (!(intsrc & (SV_CSTAT_DMAA | SV_CSTAT_DMAC | SV_CSTAT_MIDI)))
  807. return IRQ_NONE;
  808. spin_lock(&s->lock);
  809. sv_update_ptr(s);
  810. sv_handle_midi(s);
  811. spin_unlock(&s->lock);
  812. return IRQ_HANDLED;
  813. }
  814. static void sv_midi_timer(unsigned long data)
  815. {
  816. struct sv_state *s = (struct sv_state *)data;
  817. unsigned long flags;
  818. spin_lock_irqsave(&s->lock, flags);
  819. sv_handle_midi(s);
  820. spin_unlock_irqrestore(&s->lock, flags);
  821. s->midi.timer.expires = jiffies+1;
  822. add_timer(&s->midi.timer);
  823. }
  824. /* --------------------------------------------------------------------- */
  825. static const char invalid_magic[] = KERN_CRIT "sv: invalid magic value\n";
  826. #define VALIDATE_STATE(s) \
  827. ({ \
  828. if (!(s) || (s)->magic != SV_MAGIC) { \
  829. printk(invalid_magic); \
  830. return -ENXIO; \
  831. } \
  832. })
  833. /* --------------------------------------------------------------------- */
  834. #define MT_4 1
  835. #define MT_5MUTE 2
  836. #define MT_4MUTEMONO 3
  837. #define MT_6MUTE 4
  838. static const struct {
  839. unsigned left:5;
  840. unsigned right:5;
  841. unsigned type:3;
  842. unsigned rec:3;
  843. } mixtable[SOUND_MIXER_NRDEVICES] = {
  844. [SOUND_MIXER_RECLEV] = { SV_CIMIX_ADCINL, SV_CIMIX_ADCINR, MT_4, 0 },
  845. [SOUND_MIXER_LINE1] = { SV_CIMIX_AUX1INL, SV_CIMIX_AUX1INR, MT_5MUTE, 5 },
  846. [SOUND_MIXER_CD] = { SV_CIMIX_CDINL, SV_CIMIX_CDINR, MT_5MUTE, 1 },
  847. [SOUND_MIXER_LINE] = { SV_CIMIX_LINEINL, SV_CIMIX_LINEINR, MT_5MUTE, 4 },
  848. [SOUND_MIXER_MIC] = { SV_CIMIX_MICIN, SV_CIMIX_ADCINL, MT_4MUTEMONO, 6 },
  849. [SOUND_MIXER_SYNTH] = { SV_CIMIX_SYNTHINL, SV_CIMIX_SYNTHINR, MT_5MUTE, 2 },
  850. [SOUND_MIXER_LINE2] = { SV_CIMIX_AUX2INL, SV_CIMIX_AUX2INR, MT_5MUTE, 3 },
  851. [SOUND_MIXER_VOLUME] = { SV_CIMIX_ANALOGINL, SV_CIMIX_ANALOGINR, MT_5MUTE, 7 },
  852. [SOUND_MIXER_PCM] = { SV_CIMIX_PCMINL, SV_CIMIX_PCMINR, MT_6MUTE, 0 }
  853. };
  854. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  855. static int return_mixval(struct sv_state *s, unsigned i, int *arg)
  856. {
  857. unsigned long flags;
  858. unsigned char l, r, rl, rr;
  859. spin_lock_irqsave(&s->lock, flags);
  860. l = rdindir(s, mixtable[i].left);
  861. r = rdindir(s, mixtable[i].right);
  862. spin_unlock_irqrestore(&s->lock, flags);
  863. switch (mixtable[i].type) {
  864. case MT_4:
  865. r &= 0xf;
  866. l &= 0xf;
  867. rl = 10 + 6 * (l & 15);
  868. rr = 10 + 6 * (r & 15);
  869. break;
  870. case MT_4MUTEMONO:
  871. rl = 55 - 3 * (l & 15);
  872. if (r & 0x10)
  873. rl += 45;
  874. rr = rl;
  875. r = l;
  876. break;
  877. case MT_5MUTE:
  878. default:
  879. rl = 100 - 3 * (l & 31);
  880. rr = 100 - 3 * (r & 31);
  881. break;
  882. case MT_6MUTE:
  883. rl = 100 - 3 * (l & 63) / 2;
  884. rr = 100 - 3 * (r & 63) / 2;
  885. break;
  886. }
  887. if (l & 0x80)
  888. rl = 0;
  889. if (r & 0x80)
  890. rr = 0;
  891. return put_user((rr << 8) | rl, arg);
  892. }
  893. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  894. static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
  895. {
  896. [SOUND_MIXER_RECLEV] = 1,
  897. [SOUND_MIXER_LINE1] = 2,
  898. [SOUND_MIXER_CD] = 3,
  899. [SOUND_MIXER_LINE] = 4,
  900. [SOUND_MIXER_MIC] = 5,
  901. [SOUND_MIXER_SYNTH] = 6,
  902. [SOUND_MIXER_LINE2] = 7,
  903. [SOUND_MIXER_VOLUME] = 8,
  904. [SOUND_MIXER_PCM] = 9
  905. };
  906. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  907. static unsigned mixer_recmask(struct sv_state *s)
  908. {
  909. unsigned long flags;
  910. int i, j;
  911. spin_lock_irqsave(&s->lock, flags);
  912. j = rdindir(s, SV_CIMIX_ADCINL) >> 5;
  913. spin_unlock_irqrestore(&s->lock, flags);
  914. j &= 7;
  915. for (i = 0; i < SOUND_MIXER_NRDEVICES && mixtable[i].rec != j; i++);
  916. return 1 << i;
  917. }
  918. static int mixer_ioctl(struct sv_state *s, unsigned int cmd, unsigned long arg)
  919. {
  920. unsigned long flags;
  921. int i, val;
  922. unsigned char l, r, rl, rr;
  923. int __user *p = (int __user *)arg;
  924. VALIDATE_STATE(s);
  925. if (cmd == SOUND_MIXER_INFO) {
  926. mixer_info info;
  927. memset(&info, 0, sizeof(info));
  928. strlcpy(info.id, "SonicVibes", sizeof(info.id));
  929. strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
  930. info.modify_counter = s->mix.modcnt;
  931. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  932. return -EFAULT;
  933. return 0;
  934. }
  935. if (cmd == SOUND_OLD_MIXER_INFO) {
  936. _old_mixer_info info;
  937. memset(&info, 0, sizeof(info));
  938. strlcpy(info.id, "SonicVibes", sizeof(info.id));
  939. strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
  940. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  941. return -EFAULT;
  942. return 0;
  943. }
  944. if (cmd == OSS_GETVERSION)
  945. return put_user(SOUND_VERSION, p);
  946. if (cmd == SOUND_MIXER_PRIVATE1) { /* SRS settings */
  947. if (get_user(val, p))
  948. return -EFAULT;
  949. spin_lock_irqsave(&s->lock, flags);
  950. if (val & 1) {
  951. if (val & 2) {
  952. l = 4 - ((val >> 2) & 7);
  953. if (l & ~3)
  954. l = 4;
  955. r = 4 - ((val >> 5) & 7);
  956. if (r & ~3)
  957. r = 4;
  958. wrindir(s, SV_CISRSSPACE, l);
  959. wrindir(s, SV_CISRSCENTER, r);
  960. } else
  961. wrindir(s, SV_CISRSSPACE, 0x80);
  962. }
  963. l = rdindir(s, SV_CISRSSPACE);
  964. r = rdindir(s, SV_CISRSCENTER);
  965. spin_unlock_irqrestore(&s->lock, flags);
  966. if (l & 0x80)
  967. return put_user(0, p);
  968. return put_user(((4 - (l & 7)) << 2) | ((4 - (r & 7)) << 5) | 2, p);
  969. }
  970. if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
  971. return -EINVAL;
  972. if (_SIOC_DIR(cmd) == _SIOC_READ) {
  973. switch (_IOC_NR(cmd)) {
  974. case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
  975. return put_user(mixer_recmask(s), p);
  976. case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
  977. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  978. if (mixtable[i].type)
  979. val |= 1 << i;
  980. return put_user(val, p);
  981. case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
  982. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  983. if (mixtable[i].rec)
  984. val |= 1 << i;
  985. return put_user(val, p);
  986. case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
  987. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  988. if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
  989. val |= 1 << i;
  990. return put_user(val, p);
  991. case SOUND_MIXER_CAPS:
  992. return put_user(SOUND_CAP_EXCL_INPUT, p);
  993. default:
  994. i = _IOC_NR(cmd);
  995. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
  996. return -EINVAL;
  997. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  998. return return_mixval(s, i, p);
  999. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1000. if (!volidx[i])
  1001. return -EINVAL;
  1002. return put_user(s->mix.vol[volidx[i]-1], p);
  1003. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1004. }
  1005. }
  1006. if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
  1007. return -EINVAL;
  1008. s->mix.modcnt++;
  1009. switch (_IOC_NR(cmd)) {
  1010. case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
  1011. if (get_user(val, p))
  1012. return -EFAULT;
  1013. i = hweight32(val);
  1014. if (i == 0)
  1015. return 0; /*val = mixer_recmask(s);*/
  1016. else if (i > 1)
  1017. val &= ~mixer_recmask(s);
  1018. for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
  1019. if (!(val & (1 << i)))
  1020. continue;
  1021. if (mixtable[i].rec)
  1022. break;
  1023. }
  1024. if (i == SOUND_MIXER_NRDEVICES)
  1025. return 0;
  1026. spin_lock_irqsave(&s->lock, flags);
  1027. frobindir(s, SV_CIMIX_ADCINL, 0x1f, mixtable[i].rec << 5);
  1028. frobindir(s, SV_CIMIX_ADCINR, 0x1f, mixtable[i].rec << 5);
  1029. spin_unlock_irqrestore(&s->lock, flags);
  1030. return 0;
  1031. default:
  1032. i = _IOC_NR(cmd);
  1033. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
  1034. return -EINVAL;
  1035. if (get_user(val, p))
  1036. return -EFAULT;
  1037. l = val & 0xff;
  1038. r = (val >> 8) & 0xff;
  1039. if (mixtable[i].type == MT_4MUTEMONO)
  1040. l = (r + l) / 2;
  1041. if (l > 100)
  1042. l = 100;
  1043. if (r > 100)
  1044. r = 100;
  1045. spin_lock_irqsave(&s->lock, flags);
  1046. switch (mixtable[i].type) {
  1047. case MT_4:
  1048. if (l >= 10)
  1049. l -= 10;
  1050. if (r >= 10)
  1051. r -= 10;
  1052. frobindir(s, mixtable[i].left, 0xf0, l / 6);
  1053. frobindir(s, mixtable[i].right, 0xf0, l / 6);
  1054. break;
  1055. case MT_4MUTEMONO:
  1056. rr = 0;
  1057. if (l < 10)
  1058. rl = 0x80;
  1059. else {
  1060. if (l >= 55) {
  1061. rr = 0x10;
  1062. l -= 45;
  1063. }
  1064. rl = (55 - l) / 3;
  1065. }
  1066. wrindir(s, mixtable[i].left, rl);
  1067. frobindir(s, mixtable[i].right, ~0x10, rr);
  1068. break;
  1069. case MT_5MUTE:
  1070. if (l < 7)
  1071. rl = 0x80;
  1072. else
  1073. rl = (100 - l) / 3;
  1074. if (r < 7)
  1075. rr = 0x80;
  1076. else
  1077. rr = (100 - r) / 3;
  1078. wrindir(s, mixtable[i].left, rl);
  1079. wrindir(s, mixtable[i].right, rr);
  1080. break;
  1081. case MT_6MUTE:
  1082. if (l < 6)
  1083. rl = 0x80;
  1084. else
  1085. rl = (100 - l) * 2 / 3;
  1086. if (r < 6)
  1087. rr = 0x80;
  1088. else
  1089. rr = (100 - r) * 2 / 3;
  1090. wrindir(s, mixtable[i].left, rl);
  1091. wrindir(s, mixtable[i].right, rr);
  1092. break;
  1093. }
  1094. spin_unlock_irqrestore(&s->lock, flags);
  1095. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1096. return return_mixval(s, i, p);
  1097. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1098. if (!volidx[i])
  1099. return -EINVAL;
  1100. s->mix.vol[volidx[i]-1] = val;
  1101. return put_user(s->mix.vol[volidx[i]-1], p);
  1102. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1103. }
  1104. }
  1105. /* --------------------------------------------------------------------- */
  1106. static int sv_open_mixdev(struct inode *inode, struct file *file)
  1107. {
  1108. int minor = iminor(inode);
  1109. struct list_head *list;
  1110. struct sv_state *s;
  1111. for (list = devs.next; ; list = list->next) {
  1112. if (list == &devs)
  1113. return -ENODEV;
  1114. s = list_entry(list, struct sv_state, devs);
  1115. if (s->dev_mixer == minor)
  1116. break;
  1117. }
  1118. VALIDATE_STATE(s);
  1119. file->private_data = s;
  1120. return nonseekable_open(inode, file);
  1121. }
  1122. static int sv_release_mixdev(struct inode *inode, struct file *file)
  1123. {
  1124. struct sv_state *s = (struct sv_state *)file->private_data;
  1125. VALIDATE_STATE(s);
  1126. return 0;
  1127. }
  1128. static int sv_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1129. {
  1130. return mixer_ioctl((struct sv_state *)file->private_data, cmd, arg);
  1131. }
  1132. static /*const*/ struct file_operations sv_mixer_fops = {
  1133. .owner = THIS_MODULE,
  1134. .llseek = no_llseek,
  1135. .ioctl = sv_ioctl_mixdev,
  1136. .open = sv_open_mixdev,
  1137. .release = sv_release_mixdev,
  1138. };
  1139. /* --------------------------------------------------------------------- */
  1140. static int drain_dac(struct sv_state *s, int nonblock)
  1141. {
  1142. DECLARE_WAITQUEUE(wait, current);
  1143. unsigned long flags;
  1144. int count, tmo;
  1145. if (s->dma_dac.mapped || !s->dma_dac.ready)
  1146. return 0;
  1147. add_wait_queue(&s->dma_dac.wait, &wait);
  1148. for (;;) {
  1149. __set_current_state(TASK_INTERRUPTIBLE);
  1150. spin_lock_irqsave(&s->lock, flags);
  1151. count = s->dma_dac.count;
  1152. spin_unlock_irqrestore(&s->lock, flags);
  1153. if (count <= 0)
  1154. break;
  1155. if (signal_pending(current))
  1156. break;
  1157. if (nonblock) {
  1158. remove_wait_queue(&s->dma_dac.wait, &wait);
  1159. set_current_state(TASK_RUNNING);
  1160. return -EBUSY;
  1161. }
  1162. tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
  1163. tmo >>= sample_shift[(s->fmt >> SV_CFMT_ASHIFT) & SV_CFMT_MASK];
  1164. if (!schedule_timeout(tmo + 1))
  1165. printk(KERN_DEBUG "sv: dma timed out??\n");
  1166. }
  1167. remove_wait_queue(&s->dma_dac.wait, &wait);
  1168. set_current_state(TASK_RUNNING);
  1169. if (signal_pending(current))
  1170. return -ERESTARTSYS;
  1171. return 0;
  1172. }
  1173. /* --------------------------------------------------------------------- */
  1174. static ssize_t sv_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1175. {
  1176. struct sv_state *s = (struct sv_state *)file->private_data;
  1177. DECLARE_WAITQUEUE(wait, current);
  1178. ssize_t ret;
  1179. unsigned long flags;
  1180. unsigned swptr;
  1181. int cnt;
  1182. VALIDATE_STATE(s);
  1183. if (s->dma_adc.mapped)
  1184. return -ENXIO;
  1185. if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
  1186. return ret;
  1187. if (!access_ok(VERIFY_WRITE, buffer, count))
  1188. return -EFAULT;
  1189. ret = 0;
  1190. #if 0
  1191. spin_lock_irqsave(&s->lock, flags);
  1192. sv_update_ptr(s);
  1193. spin_unlock_irqrestore(&s->lock, flags);
  1194. #endif
  1195. add_wait_queue(&s->dma_adc.wait, &wait);
  1196. while (count > 0) {
  1197. spin_lock_irqsave(&s->lock, flags);
  1198. swptr = s->dma_adc.swptr;
  1199. cnt = s->dma_adc.dmasize-swptr;
  1200. if (s->dma_adc.count < cnt)
  1201. cnt = s->dma_adc.count;
  1202. if (cnt <= 0)
  1203. __set_current_state(TASK_INTERRUPTIBLE);
  1204. spin_unlock_irqrestore(&s->lock, flags);
  1205. if (cnt > count)
  1206. cnt = count;
  1207. if (cnt <= 0) {
  1208. if (s->dma_adc.enabled)
  1209. start_adc(s);
  1210. if (file->f_flags & O_NONBLOCK) {
  1211. if (!ret)
  1212. ret = -EAGAIN;
  1213. break;
  1214. }
  1215. if (!schedule_timeout(HZ)) {
  1216. printk(KERN_DEBUG "sv: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
  1217. s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
  1218. s->dma_adc.hwptr, s->dma_adc.swptr);
  1219. stop_adc(s);
  1220. spin_lock_irqsave(&s->lock, flags);
  1221. set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
  1222. /* program enhanced mode registers */
  1223. wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
  1224. wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
  1225. s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
  1226. spin_unlock_irqrestore(&s->lock, flags);
  1227. }
  1228. if (signal_pending(current)) {
  1229. if (!ret)
  1230. ret = -ERESTARTSYS;
  1231. break;
  1232. }
  1233. continue;
  1234. }
  1235. if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
  1236. if (!ret)
  1237. ret = -EFAULT;
  1238. break;
  1239. }
  1240. swptr = (swptr + cnt) % s->dma_adc.dmasize;
  1241. spin_lock_irqsave(&s->lock, flags);
  1242. s->dma_adc.swptr = swptr;
  1243. s->dma_adc.count -= cnt;
  1244. spin_unlock_irqrestore(&s->lock, flags);
  1245. count -= cnt;
  1246. buffer += cnt;
  1247. ret += cnt;
  1248. if (s->dma_adc.enabled)
  1249. start_adc(s);
  1250. }
  1251. remove_wait_queue(&s->dma_adc.wait, &wait);
  1252. set_current_state(TASK_RUNNING);
  1253. return ret;
  1254. }
  1255. static ssize_t sv_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1256. {
  1257. struct sv_state *s = (struct sv_state *)file->private_data;
  1258. DECLARE_WAITQUEUE(wait, current);
  1259. ssize_t ret;
  1260. unsigned long flags;
  1261. unsigned swptr;
  1262. int cnt;
  1263. VALIDATE_STATE(s);
  1264. if (s->dma_dac.mapped)
  1265. return -ENXIO;
  1266. if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
  1267. return ret;
  1268. if (!access_ok(VERIFY_READ, buffer, count))
  1269. return -EFAULT;
  1270. ret = 0;
  1271. #if 0
  1272. spin_lock_irqsave(&s->lock, flags);
  1273. sv_update_ptr(s);
  1274. spin_unlock_irqrestore(&s->lock, flags);
  1275. #endif
  1276. add_wait_queue(&s->dma_dac.wait, &wait);
  1277. while (count > 0) {
  1278. spin_lock_irqsave(&s->lock, flags);
  1279. if (s->dma_dac.count < 0) {
  1280. s->dma_dac.count = 0;
  1281. s->dma_dac.swptr = s->dma_dac.hwptr;
  1282. }
  1283. swptr = s->dma_dac.swptr;
  1284. cnt = s->dma_dac.dmasize-swptr;
  1285. if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
  1286. cnt = s->dma_dac.dmasize - s->dma_dac.count;
  1287. if (cnt <= 0)
  1288. __set_current_state(TASK_INTERRUPTIBLE);
  1289. spin_unlock_irqrestore(&s->lock, flags);
  1290. if (cnt > count)
  1291. cnt = count;
  1292. if (cnt <= 0) {
  1293. if (s->dma_dac.enabled)
  1294. start_dac(s);
  1295. if (file->f_flags & O_NONBLOCK) {
  1296. if (!ret)
  1297. ret = -EAGAIN;
  1298. break;
  1299. }
  1300. if (!schedule_timeout(HZ)) {
  1301. printk(KERN_DEBUG "sv: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
  1302. s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
  1303. s->dma_dac.hwptr, s->dma_dac.swptr);
  1304. stop_dac(s);
  1305. spin_lock_irqsave(&s->lock, flags);
  1306. set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
  1307. /* program enhanced mode registers */
  1308. wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
  1309. wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
  1310. s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
  1311. spin_unlock_irqrestore(&s->lock, flags);
  1312. }
  1313. if (signal_pending(current)) {
  1314. if (!ret)
  1315. ret = -ERESTARTSYS;
  1316. break;
  1317. }
  1318. continue;
  1319. }
  1320. if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
  1321. if (!ret)
  1322. ret = -EFAULT;
  1323. break;
  1324. }
  1325. swptr = (swptr + cnt) % s->dma_dac.dmasize;
  1326. spin_lock_irqsave(&s->lock, flags);
  1327. s->dma_dac.swptr = swptr;
  1328. s->dma_dac.count += cnt;
  1329. s->dma_dac.endcleared = 0;
  1330. spin_unlock_irqrestore(&s->lock, flags);
  1331. count -= cnt;
  1332. buffer += cnt;
  1333. ret += cnt;
  1334. if (s->dma_dac.enabled)
  1335. start_dac(s);
  1336. }
  1337. remove_wait_queue(&s->dma_dac.wait, &wait);
  1338. set_current_state(TASK_RUNNING);
  1339. return ret;
  1340. }
  1341. /* No kernel lock - we have our own spinlock */
  1342. static unsigned int sv_poll(struct file *file, struct poll_table_struct *wait)
  1343. {
  1344. struct sv_state *s = (struct sv_state *)file->private_data;
  1345. unsigned long flags;
  1346. unsigned int mask = 0;
  1347. VALIDATE_STATE(s);
  1348. if (file->f_mode & FMODE_WRITE) {
  1349. if (!s->dma_dac.ready && prog_dmabuf(s, 1))
  1350. return 0;
  1351. poll_wait(file, &s->dma_dac.wait, wait);
  1352. }
  1353. if (file->f_mode & FMODE_READ) {
  1354. if (!s->dma_adc.ready && prog_dmabuf(s, 0))
  1355. return 0;
  1356. poll_wait(file, &s->dma_adc.wait, wait);
  1357. }
  1358. spin_lock_irqsave(&s->lock, flags);
  1359. sv_update_ptr(s);
  1360. if (file->f_mode & FMODE_READ) {
  1361. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  1362. mask |= POLLIN | POLLRDNORM;
  1363. }
  1364. if (file->f_mode & FMODE_WRITE) {
  1365. if (s->dma_dac.mapped) {
  1366. if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
  1367. mask |= POLLOUT | POLLWRNORM;
  1368. } else {
  1369. if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
  1370. mask |= POLLOUT | POLLWRNORM;
  1371. }
  1372. }
  1373. spin_unlock_irqrestore(&s->lock, flags);
  1374. return mask;
  1375. }
  1376. static int sv_mmap(struct file *file, struct vm_area_struct *vma)
  1377. {
  1378. struct sv_state *s = (struct sv_state *)file->private_data;
  1379. struct dmabuf *db;
  1380. int ret = -EINVAL;
  1381. unsigned long size;
  1382. VALIDATE_STATE(s);
  1383. lock_kernel();
  1384. if (vma->vm_flags & VM_WRITE) {
  1385. if ((ret = prog_dmabuf(s, 1)) != 0)
  1386. goto out;
  1387. db = &s->dma_dac;
  1388. } else if (vma->vm_flags & VM_READ) {
  1389. if ((ret = prog_dmabuf(s, 0)) != 0)
  1390. goto out;
  1391. db = &s->dma_adc;
  1392. } else
  1393. goto out;
  1394. ret = -EINVAL;
  1395. if (vma->vm_pgoff != 0)
  1396. goto out;
  1397. size = vma->vm_end - vma->vm_start;
  1398. if (size > (PAGE_SIZE << db->buforder))
  1399. goto out;
  1400. ret = -EAGAIN;
  1401. if (remap_pfn_range(vma, vma->vm_start,
  1402. virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
  1403. size, vma->vm_page_prot))
  1404. goto out;
  1405. db->mapped = 1;
  1406. ret = 0;
  1407. out:
  1408. unlock_kernel();
  1409. return ret;
  1410. }
  1411. static int sv_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1412. {
  1413. struct sv_state *s = (struct sv_state *)file->private_data;
  1414. unsigned long flags;
  1415. audio_buf_info abinfo;
  1416. count_info cinfo;
  1417. int count;
  1418. int val, mapped, ret;
  1419. unsigned char fmtm, fmtd;
  1420. void __user *argp = (void __user *)arg;
  1421. int __user *p = argp;
  1422. VALIDATE_STATE(s);
  1423. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1424. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1425. switch (cmd) {
  1426. case OSS_GETVERSION:
  1427. return put_user(SOUND_VERSION, p);
  1428. case SNDCTL_DSP_SYNC:
  1429. if (file->f_mode & FMODE_WRITE)
  1430. return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
  1431. return 0;
  1432. case SNDCTL_DSP_SETDUPLEX:
  1433. return 0;
  1434. case SNDCTL_DSP_GETCAPS:
  1435. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1436. case SNDCTL_DSP_RESET:
  1437. if (file->f_mode & FMODE_WRITE) {
  1438. stop_dac(s);
  1439. synchronize_irq(s->irq);
  1440. s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1441. }
  1442. if (file->f_mode & FMODE_READ) {
  1443. stop_adc(s);
  1444. synchronize_irq(s->irq);
  1445. s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1446. }
  1447. return 0;
  1448. case SNDCTL_DSP_SPEED:
  1449. if (get_user(val, p))
  1450. return -EFAULT;
  1451. if (val >= 0) {
  1452. if (file->f_mode & FMODE_READ) {
  1453. stop_adc(s);
  1454. s->dma_adc.ready = 0;
  1455. set_adc_rate(s, val);
  1456. }
  1457. if (file->f_mode & FMODE_WRITE) {
  1458. stop_dac(s);
  1459. s->dma_dac.ready = 0;
  1460. set_dac_rate(s, val);
  1461. }
  1462. }
  1463. return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
  1464. case SNDCTL_DSP_STEREO:
  1465. if (get_user(val, p))
  1466. return -EFAULT;
  1467. fmtd = 0;
  1468. fmtm = ~0;
  1469. if (file->f_mode & FMODE_READ) {
  1470. stop_adc(s);
  1471. s->dma_adc.ready = 0;
  1472. if (val)
  1473. fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
  1474. else
  1475. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
  1476. }
  1477. if (file->f_mode & FMODE_WRITE) {
  1478. stop_dac(s);
  1479. s->dma_dac.ready = 0;
  1480. if (val)
  1481. fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
  1482. else
  1483. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
  1484. }
  1485. set_fmt(s, fmtm, fmtd);
  1486. return 0;
  1487. case SNDCTL_DSP_CHANNELS:
  1488. if (get_user(val, p))
  1489. return -EFAULT;
  1490. if (val != 0) {
  1491. fmtd = 0;
  1492. fmtm = ~0;
  1493. if (file->f_mode & FMODE_READ) {
  1494. stop_adc(s);
  1495. s->dma_adc.ready = 0;
  1496. if (val >= 2)
  1497. fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
  1498. else
  1499. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
  1500. }
  1501. if (file->f_mode & FMODE_WRITE) {
  1502. stop_dac(s);
  1503. s->dma_dac.ready = 0;
  1504. if (val >= 2)
  1505. fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
  1506. else
  1507. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
  1508. }
  1509. set_fmt(s, fmtm, fmtd);
  1510. }
  1511. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
  1512. : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
  1513. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1514. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1515. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1516. if (get_user(val, p))
  1517. return -EFAULT;
  1518. if (val != AFMT_QUERY) {
  1519. fmtd = 0;
  1520. fmtm = ~0;
  1521. if (file->f_mode & FMODE_READ) {
  1522. stop_adc(s);
  1523. s->dma_adc.ready = 0;
  1524. if (val == AFMT_S16_LE)
  1525. fmtd |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
  1526. else
  1527. fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_CSHIFT);
  1528. }
  1529. if (file->f_mode & FMODE_WRITE) {
  1530. stop_dac(s);
  1531. s->dma_dac.ready = 0;
  1532. if (val == AFMT_S16_LE)
  1533. fmtd |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
  1534. else
  1535. fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_ASHIFT);
  1536. }
  1537. set_fmt(s, fmtm, fmtd);
  1538. }
  1539. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
  1540. : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? AFMT_S16_LE : AFMT_U8, p);
  1541. case SNDCTL_DSP_POST:
  1542. return 0;
  1543. case SNDCTL_DSP_GETTRIGGER:
  1544. val = 0;
  1545. if (file->f_mode & FMODE_READ && s->enable & SV_CENABLE_RE)
  1546. val |= PCM_ENABLE_INPUT;
  1547. if (file->f_mode & FMODE_WRITE && s->enable & SV_CENABLE_PE)
  1548. val |= PCM_ENABLE_OUTPUT;
  1549. return put_user(val, p);
  1550. case SNDCTL_DSP_SETTRIGGER:
  1551. if (get_user(val, p))
  1552. return -EFAULT;
  1553. if (file->f_mode & FMODE_READ) {
  1554. if (val & PCM_ENABLE_INPUT) {
  1555. if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
  1556. return ret;
  1557. s->dma_adc.enabled = 1;
  1558. start_adc(s);
  1559. } else {
  1560. s->dma_adc.enabled = 0;
  1561. stop_adc(s);
  1562. }
  1563. }
  1564. if (file->f_mode & FMODE_WRITE) {
  1565. if (val & PCM_ENABLE_OUTPUT) {
  1566. if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
  1567. return ret;
  1568. s->dma_dac.enabled = 1;
  1569. start_dac(s);
  1570. } else {
  1571. s->dma_dac.enabled = 0;
  1572. stop_dac(s);
  1573. }
  1574. }
  1575. return 0;
  1576. case SNDCTL_DSP_GETOSPACE:
  1577. if (!(file->f_mode & FMODE_WRITE))
  1578. return -EINVAL;
  1579. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1580. return val;
  1581. spin_lock_irqsave(&s->lock, flags);
  1582. sv_update_ptr(s);
  1583. abinfo.fragsize = s->dma_dac.fragsize;
  1584. count = s->dma_dac.count;
  1585. if (count < 0)
  1586. count = 0;
  1587. abinfo.bytes = s->dma_dac.dmasize - count;
  1588. abinfo.fragstotal = s->dma_dac.numfrag;
  1589. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1590. spin_unlock_irqrestore(&s->lock, flags);
  1591. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1592. case SNDCTL_DSP_GETISPACE:
  1593. if (!(file->f_mode & FMODE_READ))
  1594. return -EINVAL;
  1595. if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
  1596. return val;
  1597. spin_lock_irqsave(&s->lock, flags);
  1598. sv_update_ptr(s);
  1599. abinfo.fragsize = s->dma_adc.fragsize;
  1600. count = s->dma_adc.count;
  1601. if (count < 0)
  1602. count = 0;
  1603. abinfo.bytes = count;
  1604. abinfo.fragstotal = s->dma_adc.numfrag;
  1605. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1606. spin_unlock_irqrestore(&s->lock, flags);
  1607. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1608. case SNDCTL_DSP_NONBLOCK:
  1609. file->f_flags |= O_NONBLOCK;
  1610. return 0;
  1611. case SNDCTL_DSP_GETODELAY:
  1612. if (!(file->f_mode & FMODE_WRITE))
  1613. return -EINVAL;
  1614. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1615. return val;
  1616. spin_lock_irqsave(&s->lock, flags);
  1617. sv_update_ptr(s);
  1618. count = s->dma_dac.count;
  1619. spin_unlock_irqrestore(&s->lock, flags);
  1620. if (count < 0)
  1621. count = 0;
  1622. return put_user(count, p);
  1623. case SNDCTL_DSP_GETIPTR:
  1624. if (!(file->f_mode & FMODE_READ))
  1625. return -EINVAL;
  1626. if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
  1627. return val;
  1628. spin_lock_irqsave(&s->lock, flags);
  1629. sv_update_ptr(s);
  1630. cinfo.bytes = s->dma_adc.total_bytes;
  1631. count = s->dma_adc.count;
  1632. if (count < 0)
  1633. count = 0;
  1634. cinfo.blocks = count >> s->dma_adc.fragshift;
  1635. cinfo.ptr = s->dma_adc.hwptr;
  1636. if (s->dma_adc.mapped)
  1637. s->dma_adc.count &= s->dma_adc.fragsize-1;
  1638. spin_unlock_irqrestore(&s->lock, flags);
  1639. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1640. return -EFAULT;
  1641. return 0;
  1642. case SNDCTL_DSP_GETOPTR:
  1643. if (!(file->f_mode & FMODE_WRITE))
  1644. return -EINVAL;
  1645. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1646. return val;
  1647. spin_lock_irqsave(&s->lock, flags);
  1648. sv_update_ptr(s);
  1649. cinfo.bytes = s->dma_dac.total_bytes;
  1650. count = s->dma_dac.count;
  1651. if (count < 0)
  1652. count = 0;
  1653. cinfo.blocks = count >> s->dma_dac.fragshift;
  1654. cinfo.ptr = s->dma_dac.hwptr;
  1655. if (s->dma_dac.mapped)
  1656. s->dma_dac.count &= s->dma_dac.fragsize-1;
  1657. spin_unlock_irqrestore(&s->lock, flags);
  1658. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1659. return -EFAULT;
  1660. return 0;
  1661. case SNDCTL_DSP_GETBLKSIZE:
  1662. if (file->f_mode & FMODE_WRITE) {
  1663. if ((val = prog_dmabuf(s, 0)))
  1664. return val;
  1665. return put_user(s->dma_dac.fragsize, p);
  1666. }
  1667. if ((val = prog_dmabuf(s, 1)))
  1668. return val;
  1669. return put_user(s->dma_adc.fragsize, p);
  1670. case SNDCTL_DSP_SETFRAGMENT:
  1671. if (get_user(val, p))
  1672. return -EFAULT;
  1673. if (file->f_mode & FMODE_READ) {
  1674. s->dma_adc.ossfragshift = val & 0xffff;
  1675. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1676. if (s->dma_adc.ossfragshift < 4)
  1677. s->dma_adc.ossfragshift = 4;
  1678. if (s->dma_adc.ossfragshift > 15)
  1679. s->dma_adc.ossfragshift = 15;
  1680. if (s->dma_adc.ossmaxfrags < 4)
  1681. s->dma_adc.ossmaxfrags = 4;
  1682. }
  1683. if (file->f_mode & FMODE_WRITE) {
  1684. s->dma_dac.ossfragshift = val & 0xffff;
  1685. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1686. if (s->dma_dac.ossfragshift < 4)
  1687. s->dma_dac.ossfragshift = 4;
  1688. if (s->dma_dac.ossfragshift > 15)
  1689. s->dma_dac.ossfragshift = 15;
  1690. if (s->dma_dac.ossmaxfrags < 4)
  1691. s->dma_dac.ossmaxfrags = 4;
  1692. }
  1693. return 0;
  1694. case SNDCTL_DSP_SUBDIVIDE:
  1695. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1696. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1697. return -EINVAL;
  1698. if (get_user(val, p))
  1699. return -EFAULT;
  1700. if (val != 1 && val != 2 && val != 4)
  1701. return -EINVAL;
  1702. if (file->f_mode & FMODE_READ)
  1703. s->dma_adc.subdivision = val;
  1704. if (file->f_mode & FMODE_WRITE)
  1705. s->dma_dac.subdivision = val;
  1706. return 0;
  1707. case SOUND_PCM_READ_RATE:
  1708. return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
  1709. case SOUND_PCM_READ_CHANNELS:
  1710. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
  1711. : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
  1712. case SOUND_PCM_READ_BITS:
  1713. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
  1714. : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? 16 : 8, p);
  1715. case SOUND_PCM_WRITE_FILTER:
  1716. case SNDCTL_DSP_SETSYNCRO:
  1717. case SOUND_PCM_READ_FILTER:
  1718. return -EINVAL;
  1719. }
  1720. return mixer_ioctl(s, cmd, arg);
  1721. }
  1722. static int sv_open(struct inode *inode, struct file *file)
  1723. {
  1724. int minor = iminor(inode);
  1725. DECLARE_WAITQUEUE(wait, current);
  1726. unsigned char fmtm = ~0, fmts = 0;
  1727. struct list_head *list;
  1728. struct sv_state *s;
  1729. for (list = devs.next; ; list = list->next) {
  1730. if (list == &devs)
  1731. return -ENODEV;
  1732. s = list_entry(list, struct sv_state, devs);
  1733. if (!((s->dev_audio ^ minor) & ~0xf))
  1734. break;
  1735. }
  1736. VALIDATE_STATE(s);
  1737. file->private_data = s;
  1738. /* wait for device to become free */
  1739. down(&s->open_sem);
  1740. while (s->open_mode & file->f_mode) {
  1741. if (file->f_flags & O_NONBLOCK) {
  1742. up(&s->open_sem);
  1743. return -EBUSY;
  1744. }
  1745. add_wait_queue(&s->open_wait, &wait);
  1746. __set_current_state(TASK_INTERRUPTIBLE);
  1747. up(&s->open_sem);
  1748. schedule();
  1749. remove_wait_queue(&s->open_wait, &wait);
  1750. set_current_state(TASK_RUNNING);
  1751. if (signal_pending(current))
  1752. return -ERESTARTSYS;
  1753. down(&s->open_sem);
  1754. }
  1755. if (file->f_mode & FMODE_READ) {
  1756. fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_CSHIFT);
  1757. if ((minor & 0xf) == SND_DEV_DSP16)
  1758. fmts |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
  1759. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
  1760. s->dma_adc.enabled = 1;
  1761. set_adc_rate(s, 8000);
  1762. }
  1763. if (file->f_mode & FMODE_WRITE) {
  1764. fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_ASHIFT);
  1765. if ((minor & 0xf) == SND_DEV_DSP16)
  1766. fmts |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
  1767. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
  1768. s->dma_dac.enabled = 1;
  1769. set_dac_rate(s, 8000);
  1770. }
  1771. set_fmt(s, fmtm, fmts);
  1772. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1773. up(&s->open_sem);
  1774. return nonseekable_open(inode, file);
  1775. }
  1776. static int sv_release(struct inode *inode, struct file *file)
  1777. {
  1778. struct sv_state *s = (struct sv_state *)file->private_data;
  1779. VALIDATE_STATE(s);
  1780. lock_kernel();
  1781. if (file->f_mode & FMODE_WRITE)
  1782. drain_dac(s, file->f_flags & O_NONBLOCK);
  1783. down(&s->open_sem);
  1784. if (file->f_mode & FMODE_WRITE) {
  1785. stop_dac(s);
  1786. dealloc_dmabuf(s, &s->dma_dac);
  1787. }
  1788. if (file->f_mode & FMODE_READ) {
  1789. stop_adc(s);
  1790. dealloc_dmabuf(s, &s->dma_adc);
  1791. }
  1792. s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
  1793. wake_up(&s->open_wait);
  1794. up(&s->open_sem);
  1795. unlock_kernel();
  1796. return 0;
  1797. }
  1798. static /*const*/ struct file_operations sv_audio_fops = {
  1799. .owner = THIS_MODULE,
  1800. .llseek = no_llseek,
  1801. .read = sv_read,
  1802. .write = sv_write,
  1803. .poll = sv_poll,
  1804. .ioctl = sv_ioctl,
  1805. .mmap = sv_mmap,
  1806. .open = sv_open,
  1807. .release = sv_release,
  1808. };
  1809. /* --------------------------------------------------------------------- */
  1810. static ssize_t sv_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1811. {
  1812. struct sv_state *s = (struct sv_state *)file->private_data;
  1813. DECLARE_WAITQUEUE(wait, current);
  1814. ssize_t ret;
  1815. unsigned long flags;
  1816. unsigned ptr;
  1817. int cnt;
  1818. VALIDATE_STATE(s);
  1819. if (!access_ok(VERIFY_WRITE, buffer, count))
  1820. return -EFAULT;
  1821. if (count == 0)
  1822. return 0;
  1823. ret = 0;
  1824. add_wait_queue(&s->midi.iwait, &wait);
  1825. while (count > 0) {
  1826. spin_lock_irqsave(&s->lock, flags);
  1827. ptr = s->midi.ird;
  1828. cnt = MIDIINBUF - ptr;
  1829. if (s->midi.icnt < cnt)
  1830. cnt = s->midi.icnt;
  1831. if (cnt <= 0)
  1832. __set_current_state(TASK_INTERRUPTIBLE);
  1833. spin_unlock_irqrestore(&s->lock, flags);
  1834. if (cnt > count)
  1835. cnt = count;
  1836. if (cnt <= 0) {
  1837. if (file->f_flags & O_NONBLOCK) {
  1838. if (!ret)
  1839. ret = -EAGAIN;
  1840. break;
  1841. }
  1842. schedule();
  1843. if (signal_pending(current)) {
  1844. if (!ret)
  1845. ret = -ERESTARTSYS;
  1846. break;
  1847. }
  1848. continue;
  1849. }
  1850. if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
  1851. if (!ret)
  1852. ret = -EFAULT;
  1853. break;
  1854. }
  1855. ptr = (ptr + cnt) % MIDIINBUF;
  1856. spin_lock_irqsave(&s->lock, flags);
  1857. s->midi.ird = ptr;
  1858. s->midi.icnt -= cnt;
  1859. spin_unlock_irqrestore(&s->lock, flags);
  1860. count -= cnt;
  1861. buffer += cnt;
  1862. ret += cnt;
  1863. break;
  1864. }
  1865. __set_current_state(TASK_RUNNING);
  1866. remove_wait_queue(&s->midi.iwait, &wait);
  1867. return ret;
  1868. }
  1869. static ssize_t sv_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1870. {
  1871. struct sv_state *s = (struct sv_state *)file->private_data;
  1872. DECLARE_WAITQUEUE(wait, current);
  1873. ssize_t ret;
  1874. unsigned long flags;
  1875. unsigned ptr;
  1876. int cnt;
  1877. VALIDATE_STATE(s);
  1878. if (!access_ok(VERIFY_READ, buffer, count))
  1879. return -EFAULT;
  1880. if (count == 0)
  1881. return 0;
  1882. ret = 0;
  1883. add_wait_queue(&s->midi.owait, &wait);
  1884. while (count > 0) {
  1885. spin_lock_irqsave(&s->lock, flags);
  1886. ptr = s->midi.owr;
  1887. cnt = MIDIOUTBUF - ptr;
  1888. if (s->midi.ocnt + cnt > MIDIOUTBUF)
  1889. cnt = MIDIOUTBUF - s->midi.ocnt;
  1890. if (cnt <= 0) {
  1891. __set_current_state(TASK_INTERRUPTIBLE);
  1892. sv_handle_midi(s);
  1893. }
  1894. spin_unlock_irqrestore(&s->lock, flags);
  1895. if (cnt > count)
  1896. cnt = count;
  1897. if (cnt <= 0) {
  1898. if (file->f_flags & O_NONBLOCK) {
  1899. if (!ret)
  1900. ret = -EAGAIN;
  1901. break;
  1902. }
  1903. schedule();
  1904. if (signal_pending(current)) {
  1905. if (!ret)
  1906. ret = -ERESTARTSYS;
  1907. break;
  1908. }
  1909. continue;
  1910. }
  1911. if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
  1912. if (!ret)
  1913. ret = -EFAULT;
  1914. break;
  1915. }
  1916. ptr = (ptr + cnt) % MIDIOUTBUF;
  1917. spin_lock_irqsave(&s->lock, flags);
  1918. s->midi.owr = ptr;
  1919. s->midi.ocnt += cnt;
  1920. spin_unlock_irqrestore(&s->lock, flags);
  1921. count -= cnt;
  1922. buffer += cnt;
  1923. ret += cnt;
  1924. spin_lock_irqsave(&s->lock, flags);
  1925. sv_handle_midi(s);
  1926. spin_unlock_irqrestore(&s->lock, flags);
  1927. }
  1928. __set_current_state(TASK_RUNNING);
  1929. remove_wait_queue(&s->midi.owait, &wait);
  1930. return ret;
  1931. }
  1932. /* No kernel lock - we have our own spinlock */
  1933. static unsigned int sv_midi_poll(struct file *file, struct poll_table_struct *wait)
  1934. {
  1935. struct sv_state *s = (struct sv_state *)file->private_data;
  1936. unsigned long flags;
  1937. unsigned int mask = 0;
  1938. VALIDATE_STATE(s);
  1939. if (file->f_mode & FMODE_WRITE)
  1940. poll_wait(file, &s->midi.owait, wait);
  1941. if (file->f_mode & FMODE_READ)
  1942. poll_wait(file, &s->midi.iwait, wait);
  1943. spin_lock_irqsave(&s->lock, flags);
  1944. if (file->f_mode & FMODE_READ) {
  1945. if (s->midi.icnt > 0)
  1946. mask |= POLLIN | POLLRDNORM;
  1947. }
  1948. if (file->f_mode & FMODE_WRITE) {
  1949. if (s->midi.ocnt < MIDIOUTBUF)
  1950. mask |= POLLOUT | POLLWRNORM;
  1951. }
  1952. spin_unlock_irqrestore(&s->lock, flags);
  1953. return mask;
  1954. }
  1955. static int sv_midi_open(struct inode *inode, struct file *file)
  1956. {
  1957. int minor = iminor(inode);
  1958. DECLARE_WAITQUEUE(wait, current);
  1959. unsigned long flags;
  1960. struct list_head *list;
  1961. struct sv_state *s;
  1962. for (list = devs.next; ; list = list->next) {
  1963. if (list == &devs)
  1964. return -ENODEV;
  1965. s = list_entry(list, struct sv_state, devs);
  1966. if (s->dev_midi == minor)
  1967. break;
  1968. }
  1969. VALIDATE_STATE(s);
  1970. file->private_data = s;
  1971. /* wait for device to become free */
  1972. down(&s->open_sem);
  1973. while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
  1974. if (file->f_flags & O_NONBLOCK) {
  1975. up(&s->open_sem);
  1976. return -EBUSY;
  1977. }
  1978. add_wait_queue(&s->open_wait, &wait);
  1979. __set_current_state(TASK_INTERRUPTIBLE);
  1980. up(&s->open_sem);
  1981. schedule();
  1982. remove_wait_queue(&s->open_wait, &wait);
  1983. set_current_state(TASK_RUNNING);
  1984. if (signal_pending(current))
  1985. return -ERESTARTSYS;
  1986. down(&s->open_sem);
  1987. }
  1988. spin_lock_irqsave(&s->lock, flags);
  1989. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  1990. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  1991. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  1992. //outb(inb(s->ioenh + SV_CODEC_CONTROL) | SV_CCTRL_WAVETABLE, s->ioenh + SV_CODEC_CONTROL);
  1993. outb(inb(s->ioenh + SV_CODEC_INTMASK) | SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
  1994. wrindir(s, SV_CIUARTCONTROL, 5); /* output MIDI data to external and internal synth */
  1995. wrindir(s, SV_CIWAVETABLESRC, 1); /* Wavetable in PC RAM */
  1996. outb(0xff, s->iomidi+1); /* reset command */
  1997. outb(0x3f, s->iomidi+1); /* uart command */
  1998. if (!(inb(s->iomidi+1) & 0x80))
  1999. inb(s->iomidi);
  2000. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2001. init_timer(&s->midi.timer);
  2002. s->midi.timer.expires = jiffies+1;
  2003. s->midi.timer.data = (unsigned long)s;
  2004. s->midi.timer.function = sv_midi_timer;
  2005. add_timer(&s->midi.timer);
  2006. }
  2007. if (file->f_mode & FMODE_READ) {
  2008. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2009. }
  2010. if (file->f_mode & FMODE_WRITE) {
  2011. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  2012. }
  2013. spin_unlock_irqrestore(&s->lock, flags);
  2014. s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
  2015. up(&s->open_sem);
  2016. return nonseekable_open(inode, file);
  2017. }
  2018. static int sv_midi_release(struct inode *inode, struct file *file)
  2019. {
  2020. struct sv_state *s = (struct sv_state *)file->private_data;
  2021. DECLARE_WAITQUEUE(wait, current);
  2022. unsigned long flags;
  2023. unsigned count, tmo;
  2024. VALIDATE_STATE(s);
  2025. lock_kernel();
  2026. if (file->f_mode & FMODE_WRITE) {
  2027. add_wait_queue(&s->midi.owait, &wait);
  2028. for (;;) {
  2029. __set_current_state(TASK_INTERRUPTIBLE);
  2030. spin_lock_irqsave(&s->lock, flags);
  2031. count = s->midi.ocnt;
  2032. spin_unlock_irqrestore(&s->lock, flags);
  2033. if (count <= 0)
  2034. break;
  2035. if (signal_pending(current))
  2036. break;
  2037. if (file->f_flags & O_NONBLOCK) {
  2038. remove_wait_queue(&s->midi.owait, &wait);
  2039. set_current_state(TASK_RUNNING);
  2040. unlock_kernel();
  2041. return -EBUSY;
  2042. }
  2043. tmo = (count * HZ) / 3100;
  2044. if (!schedule_timeout(tmo ? : 1) && tmo)
  2045. printk(KERN_DEBUG "sv: midi timed out??\n");
  2046. }
  2047. remove_wait_queue(&s->midi.owait, &wait);
  2048. set_current_state(TASK_RUNNING);
  2049. }
  2050. down(&s->open_sem);
  2051. s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
  2052. spin_lock_irqsave(&s->lock, flags);
  2053. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2054. outb(inb(s->ioenh + SV_CODEC_INTMASK) & ~SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
  2055. del_timer(&s->midi.timer);
  2056. }
  2057. spin_unlock_irqrestore(&s->lock, flags);
  2058. wake_up(&s->open_wait);
  2059. up(&s->open_sem);
  2060. unlock_kernel();
  2061. return 0;
  2062. }
  2063. static /*const*/ struct file_operations sv_midi_fops = {
  2064. .owner = THIS_MODULE,
  2065. .llseek = no_llseek,
  2066. .read = sv_midi_read,
  2067. .write = sv_midi_write,
  2068. .poll = sv_midi_poll,
  2069. .open = sv_midi_open,
  2070. .release = sv_midi_release,
  2071. };
  2072. /* --------------------------------------------------------------------- */
  2073. static int sv_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  2074. {
  2075. static const unsigned char op_offset[18] = {
  2076. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
  2077. 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
  2078. 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
  2079. };
  2080. struct sv_state *s = (struct sv_state *)file->private_data;
  2081. struct dm_fm_voice v;
  2082. struct dm_fm_note n;
  2083. struct dm_fm_params p;
  2084. unsigned int io;
  2085. unsigned int regb;
  2086. switch (cmd) {
  2087. case FM_IOCTL_RESET:
  2088. for (regb = 0xb0; regb < 0xb9; regb++) {
  2089. outb(regb, s->iosynth);
  2090. outb(0, s->iosynth+1);
  2091. outb(regb, s->iosynth+2);
  2092. outb(0, s->iosynth+3);
  2093. }
  2094. return 0;
  2095. case FM_IOCTL_PLAY_NOTE:
  2096. if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
  2097. return -EFAULT;
  2098. if (n.voice >= 18)
  2099. return -EINVAL;
  2100. if (n.voice >= 9) {
  2101. regb = n.voice - 9;
  2102. io = s->iosynth+2;
  2103. } else {
  2104. regb = n.voice;
  2105. io = s->iosynth;
  2106. }
  2107. outb(0xa0 + regb, io);
  2108. outb(n.fnum & 0xff, io+1);
  2109. outb(0xb0 + regb, io);
  2110. outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
  2111. return 0;
  2112. case FM_IOCTL_SET_VOICE:
  2113. if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
  2114. return -EFAULT;
  2115. if (v.voice >= 18)
  2116. return -EINVAL;
  2117. regb = op_offset[v.voice];
  2118. io = s->iosynth + ((v.op & 1) << 1);
  2119. outb(0x20 + regb, io);
  2120. outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
  2121. ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
  2122. outb(0x40 + regb, io);
  2123. outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
  2124. outb(0x60 + regb, io);
  2125. outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
  2126. outb(0x80 + regb, io);
  2127. outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
  2128. outb(0xe0 + regb, io);
  2129. outb(v.waveform & 0x7, io+1);
  2130. if (n.voice >= 9) {
  2131. regb = n.voice - 9;
  2132. io = s->iosynth+2;
  2133. } else {
  2134. regb = n.voice;
  2135. io = s->iosynth;
  2136. }
  2137. outb(0xc0 + regb, io);
  2138. outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
  2139. (v.connection & 1), io+1);
  2140. return 0;
  2141. case FM_IOCTL_SET_PARAMS:
  2142. if (copy_from_user(&p, (void *__user )arg, sizeof(p)))
  2143. return -EFAULT;
  2144. outb(0x08, s->iosynth);
  2145. outb((p.kbd_split & 1) << 6, s->iosynth+1);
  2146. outb(0xbd, s->iosynth);
  2147. outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
  2148. ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->iosynth+1);
  2149. return 0;
  2150. case FM_IOCTL_SET_OPL:
  2151. outb(4, s->iosynth+2);
  2152. outb(arg, s->iosynth+3);
  2153. return 0;
  2154. case FM_IOCTL_SET_MODE:
  2155. outb(5, s->iosynth+2);
  2156. outb(arg & 1, s->iosynth+3);
  2157. return 0;
  2158. default:
  2159. return -EINVAL;
  2160. }
  2161. }
  2162. static int sv_dmfm_open(struct inode *inode, struct file *file)
  2163. {
  2164. int minor = iminor(inode);
  2165. DECLARE_WAITQUEUE(wait, current);
  2166. struct list_head *list;
  2167. struct sv_state *s;
  2168. for (list = devs.next; ; list = list->next) {
  2169. if (list == &devs)
  2170. return -ENODEV;
  2171. s = list_entry(list, struct sv_state, devs);
  2172. if (s->dev_dmfm == minor)
  2173. break;
  2174. }
  2175. VALIDATE_STATE(s);
  2176. file->private_data = s;
  2177. /* wait for device to become free */
  2178. down(&s->open_sem);
  2179. while (s->open_mode & FMODE_DMFM) {
  2180. if (file->f_flags & O_NONBLOCK) {
  2181. up(&s->open_sem);
  2182. return -EBUSY;
  2183. }
  2184. add_wait_queue(&s->open_wait, &wait);
  2185. __set_current_state(TASK_INTERRUPTIBLE);
  2186. up(&s->open_sem);
  2187. schedule();
  2188. remove_wait_queue(&s->open_wait, &wait);
  2189. set_current_state(TASK_RUNNING);
  2190. if (signal_pending(current))
  2191. return -ERESTARTSYS;
  2192. down(&s->open_sem);
  2193. }
  2194. /* init the stuff */
  2195. outb(1, s->iosynth);
  2196. outb(0x20, s->iosynth+1); /* enable waveforms */
  2197. outb(4, s->iosynth+2);
  2198. outb(0, s->iosynth+3); /* no 4op enabled */
  2199. outb(5, s->iosynth+2);
  2200. outb(1, s->iosynth+3); /* enable OPL3 */
  2201. s->open_mode |= FMODE_DMFM;
  2202. up(&s->open_sem);
  2203. return nonseekable_open(inode, file);
  2204. }
  2205. static int sv_dmfm_release(struct inode *inode, struct file *file)
  2206. {
  2207. struct sv_state *s = (struct sv_state *)file->private_data;
  2208. unsigned int regb;
  2209. VALIDATE_STATE(s);
  2210. lock_kernel();
  2211. down(&s->open_sem);
  2212. s->open_mode &= ~FMODE_DMFM;
  2213. for (regb = 0xb0; regb < 0xb9; regb++) {
  2214. outb(regb, s->iosynth);
  2215. outb(0, s->iosynth+1);
  2216. outb(regb, s->iosynth+2);
  2217. outb(0, s->iosynth+3);
  2218. }
  2219. wake_up(&s->open_wait);
  2220. up(&s->open_sem);
  2221. unlock_kernel();
  2222. return 0;
  2223. }
  2224. static /*const*/ struct file_operations sv_dmfm_fops = {
  2225. .owner = THIS_MODULE,
  2226. .llseek = no_llseek,
  2227. .ioctl = sv_dmfm_ioctl,
  2228. .open = sv_dmfm_open,
  2229. .release = sv_dmfm_release,
  2230. };
  2231. /* --------------------------------------------------------------------- */
  2232. /* maximum number of devices; only used for command line params */
  2233. #define NR_DEVICE 5
  2234. static int reverb[NR_DEVICE];
  2235. #if 0
  2236. static int wavetable[NR_DEVICE];
  2237. #endif
  2238. static unsigned int devindex;
  2239. module_param_array(reverb, bool, NULL, 0);
  2240. MODULE_PARM_DESC(reverb, "if 1 enables the reverb circuitry. NOTE: your card must have the reverb RAM");
  2241. #if 0
  2242. MODULE_PARM(wavetable, "1-" __MODULE_STRING(NR_DEVICE) "i");
  2243. MODULE_PARM_DESC(wavetable, "if 1 the wavetable synth is enabled");
  2244. #endif
  2245. MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
  2246. MODULE_DESCRIPTION("S3 SonicVibes Driver");
  2247. MODULE_LICENSE("GPL");
  2248. /* --------------------------------------------------------------------- */
  2249. static struct initvol {
  2250. int mixch;
  2251. int vol;
  2252. } initvol[] __devinitdata = {
  2253. { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
  2254. { SOUND_MIXER_WRITE_LINE1, 0x4040 },
  2255. { SOUND_MIXER_WRITE_CD, 0x4040 },
  2256. { SOUND_MIXER_WRITE_LINE, 0x4040 },
  2257. { SOUND_MIXER_WRITE_MIC, 0x4040 },
  2258. { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
  2259. { SOUND_MIXER_WRITE_LINE2, 0x4040 },
  2260. { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
  2261. { SOUND_MIXER_WRITE_PCM, 0x4040 }
  2262. };
  2263. #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
  2264. (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
  2265. #ifdef SUPPORT_JOYSTICK
  2266. static int __devinit sv_register_gameport(struct sv_state *s, int io_port)
  2267. {
  2268. struct gameport *gp;
  2269. if (!request_region(io_port, SV_EXTENT_GAME, "S3 SonicVibes Gameport")) {
  2270. printk(KERN_ERR "sv: gameport io ports are in use\n");
  2271. return -EBUSY;
  2272. }
  2273. s->gameport = gp = gameport_allocate_port();
  2274. if (!gp) {
  2275. printk(KERN_ERR "sv: can not allocate memory for gameport\n");
  2276. release_region(io_port, SV_EXTENT_GAME);
  2277. return -ENOMEM;
  2278. }
  2279. gameport_set_name(gp, "S3 SonicVibes Gameport");
  2280. gameport_set_phys(gp, "isa%04x/gameport0", io_port);
  2281. gp->dev.parent = &s->dev->dev;
  2282. gp->io = io_port;
  2283. gameport_register_port(gp);
  2284. return 0;
  2285. }
  2286. static inline void sv_unregister_gameport(struct sv_state *s)
  2287. {
  2288. if (s->gameport) {
  2289. int gpio = s->gameport->io;
  2290. gameport_unregister_port(s->gameport);
  2291. release_region(gpio, SV_EXTENT_GAME);
  2292. }
  2293. }
  2294. #else
  2295. static inline int sv_register_gameport(struct sv_state *s, int io_port) { return -ENOSYS; }
  2296. static inline void sv_unregister_gameport(struct sv_state *s) { }
  2297. #endif /* SUPPORT_JOYSTICK */
  2298. static int __devinit sv_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
  2299. {
  2300. static char __devinitdata sv_ddma_name[] = "S3 Inc. SonicVibes DDMA Controller";
  2301. struct sv_state *s;
  2302. mm_segment_t fs;
  2303. int i, val, ret;
  2304. int gpio;
  2305. char *ddmaname;
  2306. unsigned ddmanamelen;
  2307. if ((ret=pci_enable_device(pcidev)))
  2308. return ret;
  2309. if (!RSRCISIOREGION(pcidev, RESOURCE_SB) ||
  2310. !RSRCISIOREGION(pcidev, RESOURCE_ENH) ||
  2311. !RSRCISIOREGION(pcidev, RESOURCE_SYNTH) ||
  2312. !RSRCISIOREGION(pcidev, RESOURCE_MIDI) ||
  2313. !RSRCISIOREGION(pcidev, RESOURCE_GAME))
  2314. return -ENODEV;
  2315. if (pcidev->irq == 0)
  2316. return -ENODEV;
  2317. if (pci_set_dma_mask(pcidev, 0x00ffffff)) {
  2318. printk(KERN_WARNING "sonicvibes: architecture does not support 24bit PCI busmaster DMA\n");
  2319. return -ENODEV;
  2320. }
  2321. /* try to allocate a DDMA resource if not already available */
  2322. if (!RSRCISIOREGION(pcidev, RESOURCE_DDMA)) {
  2323. pcidev->resource[RESOURCE_DDMA].start = 0;
  2324. pcidev->resource[RESOURCE_DDMA].end = 2*SV_EXTENT_DMA-1;
  2325. pcidev->resource[RESOURCE_DDMA].flags = PCI_BASE_ADDRESS_SPACE_IO | IORESOURCE_IO;
  2326. ddmanamelen = strlen(sv_ddma_name)+1;
  2327. if (!(ddmaname = kmalloc(ddmanamelen, GFP_KERNEL)))
  2328. return -1;
  2329. memcpy(ddmaname, sv_ddma_name, ddmanamelen);
  2330. pcidev->resource[RESOURCE_DDMA].name = ddmaname;
  2331. if (pci_assign_resource(pcidev, RESOURCE_DDMA)) {
  2332. pcidev->resource[RESOURCE_DDMA].name = NULL;
  2333. kfree(ddmaname);
  2334. printk(KERN_ERR "sv: cannot allocate DDMA controller io ports\n");
  2335. return -EBUSY;
  2336. }
  2337. }
  2338. if (!(s = kmalloc(sizeof(struct sv_state), GFP_KERNEL))) {
  2339. printk(KERN_WARNING "sv: out of memory\n");
  2340. return -ENOMEM;
  2341. }
  2342. memset(s, 0, sizeof(struct sv_state));
  2343. init_waitqueue_head(&s->dma_adc.wait);
  2344. init_waitqueue_head(&s->dma_dac.wait);
  2345. init_waitqueue_head(&s->open_wait);
  2346. init_waitqueue_head(&s->midi.iwait);
  2347. init_waitqueue_head(&s->midi.owait);
  2348. init_MUTEX(&s->open_sem);
  2349. spin_lock_init(&s->lock);
  2350. s->magic = SV_MAGIC;
  2351. s->dev = pcidev;
  2352. s->iosb = pci_resource_start(pcidev, RESOURCE_SB);
  2353. s->ioenh = pci_resource_start(pcidev, RESOURCE_ENH);
  2354. s->iosynth = pci_resource_start(pcidev, RESOURCE_SYNTH);
  2355. s->iomidi = pci_resource_start(pcidev, RESOURCE_MIDI);
  2356. s->iodmaa = pci_resource_start(pcidev, RESOURCE_DDMA);
  2357. s->iodmac = pci_resource_start(pcidev, RESOURCE_DDMA) + SV_EXTENT_DMA;
  2358. gpio = pci_resource_start(pcidev, RESOURCE_GAME);
  2359. pci_write_config_dword(pcidev, 0x40, s->iodmaa | 9); /* enable and use extended mode */
  2360. pci_write_config_dword(pcidev, 0x48, s->iodmac | 9); /* enable */
  2361. printk(KERN_DEBUG "sv: io ports: %#lx %#lx %#lx %#lx %#x %#x %#x\n",
  2362. s->iosb, s->ioenh, s->iosynth, s->iomidi, gpio, s->iodmaa, s->iodmac);
  2363. s->irq = pcidev->irq;
  2364. /* hack */
  2365. pci_write_config_dword(pcidev, 0x60, wavetable_mem >> 12); /* wavetable base address */
  2366. ret = -EBUSY;
  2367. if (!request_region(s->ioenh, SV_EXTENT_ENH, "S3 SonicVibes PCM")) {
  2368. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->ioenh, s->ioenh+SV_EXTENT_ENH-1);
  2369. goto err_region5;
  2370. }
  2371. if (!request_region(s->iodmaa, SV_EXTENT_DMA, "S3 SonicVibes DMAA")) {
  2372. printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmaa, s->iodmaa+SV_EXTENT_DMA-1);
  2373. goto err_region4;
  2374. }
  2375. if (!request_region(s->iodmac, SV_EXTENT_DMA, "S3 SonicVibes DMAC")) {
  2376. printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmac, s->iodmac+SV_EXTENT_DMA-1);
  2377. goto err_region3;
  2378. }
  2379. if (!request_region(s->iomidi, SV_EXTENT_MIDI, "S3 SonicVibes Midi")) {
  2380. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iomidi, s->iomidi+SV_EXTENT_MIDI-1);
  2381. goto err_region2;
  2382. }
  2383. if (!request_region(s->iosynth, SV_EXTENT_SYNTH, "S3 SonicVibes Synth")) {
  2384. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iosynth, s->iosynth+SV_EXTENT_SYNTH-1);
  2385. goto err_region1;
  2386. }
  2387. /* initialize codec registers */
  2388. outb(0x80, s->ioenh + SV_CODEC_CONTROL); /* assert reset */
  2389. udelay(50);
  2390. outb(0x00, s->ioenh + SV_CODEC_CONTROL); /* deassert reset */
  2391. udelay(50);
  2392. outb(SV_CCTRL_INTADRIVE | SV_CCTRL_ENHANCED /*| SV_CCTRL_WAVETABLE */
  2393. | (reverb[devindex] ? SV_CCTRL_REVERB : 0), s->ioenh + SV_CODEC_CONTROL);
  2394. inb(s->ioenh + SV_CODEC_STATUS); /* clear ints */
  2395. wrindir(s, SV_CIDRIVECONTROL, 0); /* drive current 16mA */
  2396. wrindir(s, SV_CIENABLE, s->enable = 0); /* disable DMAA and DMAC */
  2397. outb(~(SV_CINTMASK_DMAA | SV_CINTMASK_DMAC), s->ioenh + SV_CODEC_INTMASK);
  2398. /* outb(0xff, s->iodmaa + SV_DMA_RESET); */
  2399. /* outb(0xff, s->iodmac + SV_DMA_RESET); */
  2400. inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
  2401. wrindir(s, SV_CIADCCLKSOURCE, 0); /* use pll as ADC clock source */
  2402. wrindir(s, SV_CIANALOGPWRDOWN, 0); /* power up the analog parts of the device */
  2403. wrindir(s, SV_CIDIGITALPWRDOWN, 0); /* power up the digital parts of the device */
  2404. setpll(s, SV_CIADCPLLM, 8000);
  2405. wrindir(s, SV_CISRSSPACE, 0x80); /* SRS off */
  2406. wrindir(s, SV_CIPCMSR0, (8000 * 65536 / FULLRATE) & 0xff);
  2407. wrindir(s, SV_CIPCMSR1, ((8000 * 65536 / FULLRATE) >> 8) & 0xff);
  2408. wrindir(s, SV_CIADCOUTPUT, 0);
  2409. /* request irq */
  2410. if ((ret=request_irq(s->irq,sv_interrupt,SA_SHIRQ,"S3 SonicVibes",s))) {
  2411. printk(KERN_ERR "sv: irq %u in use\n", s->irq);
  2412. goto err_irq;
  2413. }
  2414. printk(KERN_INFO "sv: found adapter at io %#lx irq %u dmaa %#06x dmac %#06x revision %u\n",
  2415. s->ioenh, s->irq, s->iodmaa, s->iodmac, rdindir(s, SV_CIREVISION));
  2416. /* register devices */
  2417. if ((s->dev_audio = register_sound_dsp(&sv_audio_fops, -1)) < 0) {
  2418. ret = s->dev_audio;
  2419. goto err_dev1;
  2420. }
  2421. if ((s->dev_mixer = register_sound_mixer(&sv_mixer_fops, -1)) < 0) {
  2422. ret = s->dev_mixer;
  2423. goto err_dev2;
  2424. }
  2425. if ((s->dev_midi = register_sound_midi(&sv_midi_fops, -1)) < 0) {
  2426. ret = s->dev_midi;
  2427. goto err_dev3;
  2428. }
  2429. if ((s->dev_dmfm = register_sound_special(&sv_dmfm_fops, 15 /* ?? */)) < 0) {
  2430. ret = s->dev_dmfm;
  2431. goto err_dev4;
  2432. }
  2433. pci_set_master(pcidev); /* enable bus mastering */
  2434. /* initialize the chips */
  2435. fs = get_fs();
  2436. set_fs(KERNEL_DS);
  2437. val = SOUND_MASK_LINE|SOUND_MASK_SYNTH;
  2438. mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
  2439. for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
  2440. val = initvol[i].vol;
  2441. mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
  2442. }
  2443. set_fs(fs);
  2444. /* register gameport */
  2445. sv_register_gameport(s, gpio);
  2446. /* store it in the driver field */
  2447. pci_set_drvdata(pcidev, s);
  2448. /* put it into driver list */
  2449. list_add_tail(&s->devs, &devs);
  2450. /* increment devindex */
  2451. if (devindex < NR_DEVICE-1)
  2452. devindex++;
  2453. return 0;
  2454. err_dev4:
  2455. unregister_sound_midi(s->dev_midi);
  2456. err_dev3:
  2457. unregister_sound_mixer(s->dev_mixer);
  2458. err_dev2:
  2459. unregister_sound_dsp(s->dev_audio);
  2460. err_dev1:
  2461. printk(KERN_ERR "sv: cannot register misc device\n");
  2462. free_irq(s->irq, s);
  2463. err_irq:
  2464. release_region(s->iosynth, SV_EXTENT_SYNTH);
  2465. err_region1:
  2466. release_region(s->iomidi, SV_EXTENT_MIDI);
  2467. err_region2:
  2468. release_region(s->iodmac, SV_EXTENT_DMA);
  2469. err_region3:
  2470. release_region(s->iodmaa, SV_EXTENT_DMA);
  2471. err_region4:
  2472. release_region(s->ioenh, SV_EXTENT_ENH);
  2473. err_region5:
  2474. kfree(s);
  2475. return ret;
  2476. }
  2477. static void __devexit sv_remove(struct pci_dev *dev)
  2478. {
  2479. struct sv_state *s = pci_get_drvdata(dev);
  2480. if (!s)
  2481. return;
  2482. list_del(&s->devs);
  2483. outb(~0, s->ioenh + SV_CODEC_INTMASK); /* disable ints */
  2484. synchronize_irq(s->irq);
  2485. inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
  2486. wrindir(s, SV_CIENABLE, 0); /* disable DMAA and DMAC */
  2487. /*outb(0, s->iodmaa + SV_DMA_RESET);*/
  2488. /*outb(0, s->iodmac + SV_DMA_RESET);*/
  2489. free_irq(s->irq, s);
  2490. sv_unregister_gameport(s);
  2491. release_region(s->iodmac, SV_EXTENT_DMA);
  2492. release_region(s->iodmaa, SV_EXTENT_DMA);
  2493. release_region(s->ioenh, SV_EXTENT_ENH);
  2494. release_region(s->iomidi, SV_EXTENT_MIDI);
  2495. release_region(s->iosynth, SV_EXTENT_SYNTH);
  2496. unregister_sound_dsp(s->dev_audio);
  2497. unregister_sound_mixer(s->dev_mixer);
  2498. unregister_sound_midi(s->dev_midi);
  2499. unregister_sound_special(s->dev_dmfm);
  2500. kfree(s);
  2501. pci_set_drvdata(dev, NULL);
  2502. }
  2503. static struct pci_device_id id_table[] = {
  2504. { PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SONICVIBES, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2505. { 0, }
  2506. };
  2507. MODULE_DEVICE_TABLE(pci, id_table);
  2508. static struct pci_driver sv_driver = {
  2509. .name = "sonicvibes",
  2510. .id_table = id_table,
  2511. .probe = sv_probe,
  2512. .remove = __devexit_p(sv_remove),
  2513. };
  2514. static int __init init_sonicvibes(void)
  2515. {
  2516. printk(KERN_INFO "sv: version v0.31 time " __TIME__ " " __DATE__ "\n");
  2517. #if 0
  2518. if (!(wavetable_mem = __get_free_pages(GFP_KERNEL, 20-PAGE_SHIFT)))
  2519. printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
  2520. #endif
  2521. return pci_register_driver(&sv_driver);
  2522. }
  2523. static void __exit cleanup_sonicvibes(void)
  2524. {
  2525. printk(KERN_INFO "sv: unloading\n");
  2526. pci_unregister_driver(&sv_driver);
  2527. if (wavetable_mem)
  2528. free_pages(wavetable_mem, 20-PAGE_SHIFT);
  2529. }
  2530. module_init(init_sonicvibes);
  2531. module_exit(cleanup_sonicvibes);
  2532. /* --------------------------------------------------------------------- */
  2533. #ifndef MODULE
  2534. /* format is: sonicvibes=[reverb] sonicvibesdmaio=dmaioaddr */
  2535. static int __init sonicvibes_setup(char *str)
  2536. {
  2537. static unsigned __initdata nr_dev = 0;
  2538. if (nr_dev >= NR_DEVICE)
  2539. return 0;
  2540. #if 0
  2541. if (get_option(&str, &reverb[nr_dev]) == 2)
  2542. (void)get_option(&str, &wavetable[nr_dev]);
  2543. #else
  2544. (void)get_option(&str, &reverb[nr_dev]);
  2545. #endif
  2546. nr_dev++;
  2547. return 1;
  2548. }
  2549. __setup("sonicvibes=", sonicvibes_setup);
  2550. #endif /* MODULE */