nec_vrc5477.c 54 KB

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  1. /***********************************************************************
  2. * Copyright 2001 MontaVista Software Inc.
  3. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  4. *
  5. * drivers/sound/nec_vrc5477.c
  6. * AC97 sound dirver for NEC Vrc5477 chip (an integrated,
  7. * multi-function controller chip for MIPS CPUs)
  8. *
  9. * VRA support Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. ***********************************************************************
  16. */
  17. /*
  18. * This code is derived from ite8172.c, which is written by Steve Longerbeam.
  19. *
  20. * Features:
  21. * Currently we only support the following capabilities:
  22. * . mono output to PCM L/R (line out).
  23. * . stereo output to PCM L/R (line out).
  24. * . mono input from PCM L (line in).
  25. * . stereo output from PCM (line in).
  26. * . sampling rate at 48k or variable sampling rate
  27. * . support /dev/dsp, /dev/mixer devices, standard OSS devices.
  28. * . only support 16-bit PCM format (hardware limit, no software
  29. * translation)
  30. * . support duplex, but no trigger or realtime.
  31. *
  32. * Specifically the following are not supported:
  33. * . app-set frag size.
  34. * . mmap'ed buffer access
  35. */
  36. /*
  37. * Original comments from ite8172.c file.
  38. */
  39. /*
  40. *
  41. * Notes:
  42. *
  43. * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
  44. * taken, slightly modified or not at all, from the ES1371 driver,
  45. * so refer to the credits in es1371.c for those. The rest of the
  46. * code (probe, open, read, write, the ISR, etc.) is new.
  47. * 2. The following support is untested:
  48. * * Memory mapping the audio buffers, and the ioctl controls that go
  49. * with it.
  50. * * S/PDIF output.
  51. * 3. The following is not supported:
  52. * * I2S input.
  53. * * legacy audio mode.
  54. * 4. Support for volume button interrupts is implemented but doesn't
  55. * work yet.
  56. *
  57. * Revision history
  58. * 02.08.2001 0.1 Initial release
  59. */
  60. #include <linux/module.h>
  61. #include <linux/string.h>
  62. #include <linux/kernel.h>
  63. #include <linux/ioport.h>
  64. #include <linux/sched.h>
  65. #include <linux/delay.h>
  66. #include <linux/sound.h>
  67. #include <linux/slab.h>
  68. #include <linux/soundcard.h>
  69. #include <linux/pci.h>
  70. #include <linux/init.h>
  71. #include <linux/poll.h>
  72. #include <linux/bitops.h>
  73. #include <linux/proc_fs.h>
  74. #include <linux/spinlock.h>
  75. #include <linux/smp_lock.h>
  76. #include <linux/ac97_codec.h>
  77. #include <asm/io.h>
  78. #include <asm/dma.h>
  79. #include <asm/uaccess.h>
  80. /* -------------------debug macros -------------------------------------- */
  81. /* #undef VRC5477_AC97_DEBUG */
  82. #define VRC5477_AC97_DEBUG
  83. #undef VRC5477_AC97_VERBOSE_DEBUG
  84. /* #define VRC5477_AC97_VERBOSE_DEBUG */
  85. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  86. #define VRC5477_AC97_DEBUG
  87. #endif
  88. #if defined(VRC5477_AC97_DEBUG)
  89. #define ASSERT(x) if (!(x)) { \
  90. panic("assertion failed at %s:%d: %s\n", __FILE__, __LINE__, #x); }
  91. #else
  92. #define ASSERT(x)
  93. #endif /* VRC5477_AC97_DEBUG */
  94. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  95. static u16 inTicket; /* check sync between intr & write */
  96. static u16 outTicket;
  97. #endif
  98. /* --------------------------------------------------------------------- */
  99. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  100. static const unsigned sample_shift[] = { 0, 1, 1, 2 };
  101. #define VRC5477_INT_CLR 0x0
  102. #define VRC5477_INT_STATUS 0x0
  103. #define VRC5477_CODEC_WR 0x4
  104. #define VRC5477_CODEC_RD 0x8
  105. #define VRC5477_CTRL 0x18
  106. #define VRC5477_ACLINK_CTRL 0x1c
  107. #define VRC5477_INT_MASK 0x24
  108. #define VRC5477_DAC1_CTRL 0x30
  109. #define VRC5477_DAC1L 0x34
  110. #define VRC5477_DAC1_BADDR 0x38
  111. #define VRC5477_DAC2_CTRL 0x3c
  112. #define VRC5477_DAC2L 0x40
  113. #define VRC5477_DAC2_BADDR 0x44
  114. #define VRC5477_DAC3_CTRL 0x48
  115. #define VRC5477_DAC3L 0x4c
  116. #define VRC5477_DAC3_BADDR 0x50
  117. #define VRC5477_ADC1_CTRL 0x54
  118. #define VRC5477_ADC1L 0x58
  119. #define VRC5477_ADC1_BADDR 0x5c
  120. #define VRC5477_ADC2_CTRL 0x60
  121. #define VRC5477_ADC2L 0x64
  122. #define VRC5477_ADC2_BADDR 0x68
  123. #define VRC5477_ADC3_CTRL 0x6c
  124. #define VRC5477_ADC3L 0x70
  125. #define VRC5477_ADC3_BADDR 0x74
  126. #define VRC5477_CODEC_WR_RWC (1 << 23)
  127. #define VRC5477_CODEC_RD_RRDYA (1 << 31)
  128. #define VRC5477_CODEC_RD_RRDYD (1 << 30)
  129. #define VRC5477_ACLINK_CTRL_RST_ON (1 << 15)
  130. #define VRC5477_ACLINK_CTRL_RST_TIME 0x7f
  131. #define VRC5477_ACLINK_CTRL_SYNC_ON (1 << 30)
  132. #define VRC5477_ACLINK_CTRL_CK_STOP_ON (1 << 31)
  133. #define VRC5477_CTRL_DAC2ENB (1 << 15)
  134. #define VRC5477_CTRL_ADC2ENB (1 << 14)
  135. #define VRC5477_CTRL_DAC1ENB (1 << 13)
  136. #define VRC5477_CTRL_ADC1ENB (1 << 12)
  137. #define VRC5477_INT_MASK_NMASK (1 << 31)
  138. #define VRC5477_INT_MASK_DAC1END (1 << 5)
  139. #define VRC5477_INT_MASK_DAC2END (1 << 4)
  140. #define VRC5477_INT_MASK_DAC3END (1 << 3)
  141. #define VRC5477_INT_MASK_ADC1END (1 << 2)
  142. #define VRC5477_INT_MASK_ADC2END (1 << 1)
  143. #define VRC5477_INT_MASK_ADC3END (1 << 0)
  144. #define VRC5477_DMA_ACTIVATION (1 << 31)
  145. #define VRC5477_DMA_WIP (1 << 30)
  146. #define VRC5477_AC97_MODULE_NAME "NEC_Vrc5477_audio"
  147. #define PFX VRC5477_AC97_MODULE_NAME ": "
  148. /* --------------------------------------------------------------------- */
  149. struct vrc5477_ac97_state {
  150. /* list of vrc5477_ac97 devices */
  151. struct list_head devs;
  152. /* the corresponding pci_dev structure */
  153. struct pci_dev *dev;
  154. /* soundcore stuff */
  155. int dev_audio;
  156. /* hardware resources */
  157. unsigned long io;
  158. unsigned int irq;
  159. #ifdef VRC5477_AC97_DEBUG
  160. /* debug /proc entry */
  161. struct proc_dir_entry *ps;
  162. struct proc_dir_entry *ac97_ps;
  163. #endif /* VRC5477_AC97_DEBUG */
  164. struct ac97_codec *codec;
  165. unsigned dacChannels, adcChannels;
  166. unsigned short dacRate, adcRate;
  167. unsigned short extended_status;
  168. spinlock_t lock;
  169. struct semaphore open_sem;
  170. mode_t open_mode;
  171. wait_queue_head_t open_wait;
  172. struct dmabuf {
  173. void *lbuf, *rbuf;
  174. dma_addr_t lbufDma, rbufDma;
  175. unsigned bufOrder;
  176. unsigned numFrag;
  177. unsigned fragShift;
  178. unsigned fragSize; /* redundant */
  179. unsigned fragTotalSize; /* = numFrag * fragSize(real) */
  180. unsigned nextIn;
  181. unsigned nextOut;
  182. int count;
  183. unsigned error; /* over/underrun */
  184. wait_queue_head_t wait;
  185. /* OSS stuff */
  186. unsigned stopped:1;
  187. unsigned ready:1;
  188. } dma_dac, dma_adc;
  189. #define WORK_BUF_SIZE 2048
  190. struct {
  191. u16 lchannel;
  192. u16 rchannel;
  193. } workBuf[WORK_BUF_SIZE/4];
  194. };
  195. /* --------------------------------------------------------------------- */
  196. static LIST_HEAD(devs);
  197. /* --------------------------------------------------------------------- */
  198. static inline unsigned ld2(unsigned int x)
  199. {
  200. unsigned r = 0;
  201. if (x >= 0x10000) {
  202. x >>= 16;
  203. r += 16;
  204. }
  205. if (x >= 0x100) {
  206. x >>= 8;
  207. r += 8;
  208. }
  209. if (x >= 0x10) {
  210. x >>= 4;
  211. r += 4;
  212. }
  213. if (x >= 4) {
  214. x >>= 2;
  215. r += 2;
  216. }
  217. if (x >= 2)
  218. r++;
  219. return r;
  220. }
  221. /* --------------------------------------------------------------------- */
  222. static u16 rdcodec(struct ac97_codec *codec, u8 addr)
  223. {
  224. struct vrc5477_ac97_state *s =
  225. (struct vrc5477_ac97_state *)codec->private_data;
  226. unsigned long flags;
  227. u32 result;
  228. spin_lock_irqsave(&s->lock, flags);
  229. /* wait until we can access codec registers */
  230. while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000);
  231. /* write the address and "read" command to codec */
  232. addr = addr & 0x7f;
  233. outl((addr << 16) | VRC5477_CODEC_WR_RWC, s->io + VRC5477_CODEC_WR);
  234. /* get the return result */
  235. udelay(100); /* workaround hardware bug */
  236. while ( (result = inl(s->io + VRC5477_CODEC_RD)) &
  237. (VRC5477_CODEC_RD_RRDYA | VRC5477_CODEC_RD_RRDYD) ) {
  238. /* we get either addr or data, or both */
  239. if (result & VRC5477_CODEC_RD_RRDYA) {
  240. ASSERT(addr == ((result >> 16) & 0x7f) );
  241. }
  242. if (result & VRC5477_CODEC_RD_RRDYD) {
  243. break;
  244. }
  245. }
  246. spin_unlock_irqrestore(&s->lock, flags);
  247. return result & 0xffff;
  248. }
  249. static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  250. {
  251. struct vrc5477_ac97_state *s =
  252. (struct vrc5477_ac97_state *)codec->private_data;
  253. unsigned long flags;
  254. spin_lock_irqsave(&s->lock, flags);
  255. /* wait until we can access codec registers */
  256. while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000);
  257. /* write the address and value to codec */
  258. outl((addr << 16) | data, s->io + VRC5477_CODEC_WR);
  259. spin_unlock_irqrestore(&s->lock, flags);
  260. }
  261. static void waitcodec(struct ac97_codec *codec)
  262. {
  263. struct vrc5477_ac97_state *s =
  264. (struct vrc5477_ac97_state *)codec->private_data;
  265. /* wait until we can access codec registers */
  266. while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000);
  267. }
  268. static int ac97_codec_not_present(struct ac97_codec *codec)
  269. {
  270. struct vrc5477_ac97_state *s =
  271. (struct vrc5477_ac97_state *)codec->private_data;
  272. unsigned long flags;
  273. unsigned short count = 0xffff;
  274. spin_lock_irqsave(&s->lock, flags);
  275. /* wait until we can access codec registers */
  276. do {
  277. if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000))
  278. break;
  279. } while (--count);
  280. if (count == 0) {
  281. spin_unlock_irqrestore(&s->lock, flags);
  282. return -1;
  283. }
  284. /* write 0 to reset */
  285. outl((AC97_RESET << 16) | 0, s->io + VRC5477_CODEC_WR);
  286. /* test whether we get a response from ac97 chip */
  287. count = 0xffff;
  288. do {
  289. if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000))
  290. break;
  291. } while (--count);
  292. if (count == 0) {
  293. spin_unlock_irqrestore(&s->lock, flags);
  294. return -1;
  295. }
  296. spin_unlock_irqrestore(&s->lock, flags);
  297. return 0;
  298. }
  299. /* --------------------------------------------------------------------- */
  300. static void vrc5477_ac97_delay(int msec)
  301. {
  302. unsigned long tmo;
  303. signed long tmo2;
  304. if (in_interrupt())
  305. return;
  306. tmo = jiffies + (msec*HZ)/1000;
  307. for (;;) {
  308. tmo2 = tmo - jiffies;
  309. if (tmo2 <= 0)
  310. break;
  311. schedule_timeout(tmo2);
  312. }
  313. }
  314. static void set_adc_rate(struct vrc5477_ac97_state *s, unsigned rate)
  315. {
  316. wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, rate);
  317. s->adcRate = rate;
  318. }
  319. static void set_dac_rate(struct vrc5477_ac97_state *s, unsigned rate)
  320. {
  321. if(s->extended_status & AC97_EXTSTAT_VRA) {
  322. wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, rate);
  323. s->dacRate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  324. }
  325. }
  326. static int ac97_codec_not_present(struct ac97_codec *codec)
  327. {
  328. struct vrc5477_ac97_state *s =
  329. (struct vrc5477_ac97_state *)codec->private_data;
  330. unsigned long flags;
  331. unsigned short count = 0xffff;
  332. spin_lock_irqsave(&s->lock, flags);
  333. /* wait until we can access codec registers */
  334. do {
  335. if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000))
  336. break;
  337. } while (--count);
  338. if (count == 0) {
  339. spin_unlock_irqrestore(&s->lock, flags);
  340. return -1;
  341. }
  342. /* write 0 to reset */
  343. outl((AC97_RESET << 16) | 0, s->io + VRC5477_CODEC_WR);
  344. /* test whether we get a response from ac97 chip */
  345. count = 0xffff;
  346. do {
  347. if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000))
  348. break;
  349. } while (--count);
  350. if (count == 0) {
  351. spin_unlock_irqrestore(&s->lock, flags);
  352. return -1;
  353. }
  354. spin_unlock_irqrestore(&s->lock, flags);
  355. return 0;
  356. }
  357. /* --------------------------------------------------------------------- */
  358. static inline void
  359. stop_dac(struct vrc5477_ac97_state *s)
  360. {
  361. struct dmabuf* db = &s->dma_dac;
  362. unsigned long flags;
  363. u32 temp;
  364. spin_lock_irqsave(&s->lock, flags);
  365. if (db->stopped) {
  366. spin_unlock_irqrestore(&s->lock, flags);
  367. return;
  368. }
  369. /* deactivate the dma */
  370. outl(0, s->io + VRC5477_DAC1_CTRL);
  371. outl(0, s->io + VRC5477_DAC2_CTRL);
  372. /* wait for DAM completely stop */
  373. while (inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP);
  374. while (inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP);
  375. /* disable dac slots in aclink */
  376. temp = inl(s->io + VRC5477_CTRL);
  377. temp &= ~ (VRC5477_CTRL_DAC1ENB | VRC5477_CTRL_DAC2ENB);
  378. outl (temp, s->io + VRC5477_CTRL);
  379. /* disable interrupts */
  380. temp = inl(s->io + VRC5477_INT_MASK);
  381. temp &= ~ (VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END);
  382. outl (temp, s->io + VRC5477_INT_MASK);
  383. /* clear pending ones */
  384. outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END,
  385. s->io + VRC5477_INT_CLR);
  386. db->stopped = 1;
  387. spin_unlock_irqrestore(&s->lock, flags);
  388. }
  389. static void start_dac(struct vrc5477_ac97_state *s)
  390. {
  391. struct dmabuf* db = &s->dma_dac;
  392. unsigned long flags;
  393. u32 dmaLength;
  394. u32 temp;
  395. spin_lock_irqsave(&s->lock, flags);
  396. if (!db->stopped) {
  397. spin_unlock_irqrestore(&s->lock, flags);
  398. return;
  399. }
  400. /* we should have some data to do the DMA trasnfer */
  401. ASSERT(db->count >= db->fragSize);
  402. /* clear pending fales interrupts */
  403. outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END,
  404. s->io + VRC5477_INT_CLR);
  405. /* enable interrupts */
  406. temp = inl(s->io + VRC5477_INT_MASK);
  407. temp |= VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END;
  408. outl(temp, s->io + VRC5477_INT_MASK);
  409. /* setup dma base addr */
  410. outl(db->lbufDma + db->nextOut, s->io + VRC5477_DAC1_BADDR);
  411. if (s->dacChannels == 1) {
  412. outl(db->lbufDma + db->nextOut, s->io + VRC5477_DAC2_BADDR);
  413. } else {
  414. outl(db->rbufDma + db->nextOut, s->io + VRC5477_DAC2_BADDR);
  415. }
  416. /* set dma length, in the unit of 0x10 bytes */
  417. dmaLength = db->fragSize >> 4;
  418. outl(dmaLength, s->io + VRC5477_DAC1L);
  419. outl(dmaLength, s->io + VRC5477_DAC2L);
  420. /* activate dma */
  421. outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_DAC1_CTRL);
  422. outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_DAC2_CTRL);
  423. /* enable dac slots - we should hear the music now! */
  424. temp = inl(s->io + VRC5477_CTRL);
  425. temp |= (VRC5477_CTRL_DAC1ENB | VRC5477_CTRL_DAC2ENB);
  426. outl (temp, s->io + VRC5477_CTRL);
  427. /* it is time to setup next dma transfer */
  428. ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP);
  429. ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP);
  430. temp = db->nextOut + db->fragSize;
  431. if (temp >= db->fragTotalSize) {
  432. ASSERT(temp == db->fragTotalSize);
  433. temp = 0;
  434. }
  435. outl(db->lbufDma + temp, s->io + VRC5477_DAC1_BADDR);
  436. if (s->dacChannels == 1) {
  437. outl(db->lbufDma + temp, s->io + VRC5477_DAC2_BADDR);
  438. } else {
  439. outl(db->rbufDma + temp, s->io + VRC5477_DAC2_BADDR);
  440. }
  441. db->stopped = 0;
  442. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  443. outTicket = *(u16*)(db->lbuf+db->nextOut);
  444. if (db->count > db->fragSize) {
  445. ASSERT((u16)(outTicket+1) == *(u16*)(db->lbuf+temp));
  446. }
  447. #endif
  448. spin_unlock_irqrestore(&s->lock, flags);
  449. }
  450. static inline void stop_adc(struct vrc5477_ac97_state *s)
  451. {
  452. struct dmabuf* db = &s->dma_adc;
  453. unsigned long flags;
  454. u32 temp;
  455. spin_lock_irqsave(&s->lock, flags);
  456. if (db->stopped) {
  457. spin_unlock_irqrestore(&s->lock, flags);
  458. return;
  459. }
  460. /* deactivate the dma */
  461. outl(0, s->io + VRC5477_ADC1_CTRL);
  462. outl(0, s->io + VRC5477_ADC2_CTRL);
  463. /* disable adc slots in aclink */
  464. temp = inl(s->io + VRC5477_CTRL);
  465. temp &= ~ (VRC5477_CTRL_ADC1ENB | VRC5477_CTRL_ADC2ENB);
  466. outl (temp, s->io + VRC5477_CTRL);
  467. /* disable interrupts */
  468. temp = inl(s->io + VRC5477_INT_MASK);
  469. temp &= ~ (VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END);
  470. outl (temp, s->io + VRC5477_INT_MASK);
  471. /* clear pending ones */
  472. outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END,
  473. s->io + VRC5477_INT_CLR);
  474. db->stopped = 1;
  475. spin_unlock_irqrestore(&s->lock, flags);
  476. }
  477. static void start_adc(struct vrc5477_ac97_state *s)
  478. {
  479. struct dmabuf* db = &s->dma_adc;
  480. unsigned long flags;
  481. u32 dmaLength;
  482. u32 temp;
  483. spin_lock_irqsave(&s->lock, flags);
  484. if (!db->stopped) {
  485. spin_unlock_irqrestore(&s->lock, flags);
  486. return;
  487. }
  488. /* we should at least have some free space in the buffer */
  489. ASSERT(db->count < db->fragTotalSize - db->fragSize * 2);
  490. /* clear pending ones */
  491. outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END,
  492. s->io + VRC5477_INT_CLR);
  493. /* enable interrupts */
  494. temp = inl(s->io + VRC5477_INT_MASK);
  495. temp |= VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END;
  496. outl(temp, s->io + VRC5477_INT_MASK);
  497. /* setup dma base addr */
  498. outl(db->lbufDma + db->nextIn, s->io + VRC5477_ADC1_BADDR);
  499. outl(db->rbufDma + db->nextIn, s->io + VRC5477_ADC2_BADDR);
  500. /* setup dma length */
  501. dmaLength = db->fragSize >> 4;
  502. outl(dmaLength, s->io + VRC5477_ADC1L);
  503. outl(dmaLength, s->io + VRC5477_ADC2L);
  504. /* activate dma */
  505. outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_ADC1_CTRL);
  506. outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_ADC2_CTRL);
  507. /* enable adc slots */
  508. temp = inl(s->io + VRC5477_CTRL);
  509. temp |= (VRC5477_CTRL_ADC1ENB | VRC5477_CTRL_ADC2ENB);
  510. outl (temp, s->io + VRC5477_CTRL);
  511. /* it is time to setup next dma transfer */
  512. temp = db->nextIn + db->fragSize;
  513. if (temp >= db->fragTotalSize) {
  514. ASSERT(temp == db->fragTotalSize);
  515. temp = 0;
  516. }
  517. outl(db->lbufDma + temp, s->io + VRC5477_ADC1_BADDR);
  518. outl(db->rbufDma + temp, s->io + VRC5477_ADC2_BADDR);
  519. db->stopped = 0;
  520. spin_unlock_irqrestore(&s->lock, flags);
  521. }
  522. /* --------------------------------------------------------------------- */
  523. #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
  524. #define DMABUF_MINORDER 1
  525. static inline void dealloc_dmabuf(struct vrc5477_ac97_state *s,
  526. struct dmabuf *db)
  527. {
  528. if (db->lbuf) {
  529. ASSERT(db->rbuf);
  530. pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder,
  531. db->lbuf, db->lbufDma);
  532. pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder,
  533. db->rbuf, db->rbufDma);
  534. db->lbuf = db->rbuf = NULL;
  535. }
  536. db->nextIn = db->nextOut = 0;
  537. db->ready = 0;
  538. }
  539. static int prog_dmabuf(struct vrc5477_ac97_state *s,
  540. struct dmabuf *db,
  541. unsigned rate)
  542. {
  543. int order;
  544. unsigned bufsize;
  545. if (!db->lbuf) {
  546. ASSERT(!db->rbuf);
  547. db->ready = 0;
  548. for (order = DMABUF_DEFAULTORDER;
  549. order >= DMABUF_MINORDER;
  550. order--) {
  551. db->lbuf = pci_alloc_consistent(s->dev,
  552. PAGE_SIZE << order,
  553. &db->lbufDma);
  554. db->rbuf = pci_alloc_consistent(s->dev,
  555. PAGE_SIZE << order,
  556. &db->rbufDma);
  557. if (db->lbuf && db->rbuf) break;
  558. if (db->lbuf) {
  559. ASSERT(!db->rbuf);
  560. pci_free_consistent(s->dev,
  561. PAGE_SIZE << order,
  562. db->lbuf,
  563. db->lbufDma);
  564. }
  565. }
  566. if (!db->lbuf) {
  567. ASSERT(!db->rbuf);
  568. return -ENOMEM;
  569. }
  570. db->bufOrder = order;
  571. }
  572. db->count = 0;
  573. db->nextIn = db->nextOut = 0;
  574. bufsize = PAGE_SIZE << db->bufOrder;
  575. db->fragShift = ld2(rate * 2 / 100);
  576. if (db->fragShift < 4) db->fragShift = 4;
  577. db->numFrag = bufsize >> db->fragShift;
  578. while (db->numFrag < 4 && db->fragShift > 4) {
  579. db->fragShift--;
  580. db->numFrag = bufsize >> db->fragShift;
  581. }
  582. db->fragSize = 1 << db->fragShift;
  583. db->fragTotalSize = db->numFrag << db->fragShift;
  584. memset(db->lbuf, 0, db->fragTotalSize);
  585. memset(db->rbuf, 0, db->fragTotalSize);
  586. db->ready = 1;
  587. return 0;
  588. }
  589. static inline int prog_dmabuf_adc(struct vrc5477_ac97_state *s)
  590. {
  591. stop_adc(s);
  592. return prog_dmabuf(s, &s->dma_adc, s->adcRate);
  593. }
  594. static inline int prog_dmabuf_dac(struct vrc5477_ac97_state *s)
  595. {
  596. stop_dac(s);
  597. return prog_dmabuf(s, &s->dma_dac, s->dacRate);
  598. }
  599. /* --------------------------------------------------------------------- */
  600. /* hold spinlock for the following! */
  601. static inline void vrc5477_ac97_adc_interrupt(struct vrc5477_ac97_state *s)
  602. {
  603. struct dmabuf* adc = &s->dma_adc;
  604. unsigned temp;
  605. /* we need two frags avaiable because one is already being used
  606. * and the other will be used when next interrupt happens.
  607. */
  608. if (adc->count >= adc->fragTotalSize - adc->fragSize) {
  609. stop_adc(s);
  610. adc->error++;
  611. printk(KERN_INFO PFX "adc overrun\n");
  612. return;
  613. }
  614. /* set the base addr for next DMA transfer */
  615. temp = adc->nextIn + 2*adc->fragSize;
  616. if (temp >= adc->fragTotalSize) {
  617. ASSERT( (temp == adc->fragTotalSize) ||
  618. (temp == adc->fragTotalSize + adc->fragSize) );
  619. temp -= adc->fragTotalSize;
  620. }
  621. outl(adc->lbufDma + temp, s->io + VRC5477_ADC1_BADDR);
  622. outl(adc->rbufDma + temp, s->io + VRC5477_ADC2_BADDR);
  623. /* adjust nextIn */
  624. adc->nextIn += adc->fragSize;
  625. if (adc->nextIn >= adc->fragTotalSize) {
  626. ASSERT(adc->nextIn == adc->fragTotalSize);
  627. adc->nextIn = 0;
  628. }
  629. /* adjust count */
  630. adc->count += adc->fragSize;
  631. /* wake up anybody listening */
  632. if (waitqueue_active(&adc->wait)) {
  633. wake_up_interruptible(&adc->wait);
  634. }
  635. }
  636. static inline void vrc5477_ac97_dac_interrupt(struct vrc5477_ac97_state *s)
  637. {
  638. struct dmabuf* dac = &s->dma_dac;
  639. unsigned temp;
  640. /* next DMA transfer should already started */
  641. // ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP);
  642. // ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP);
  643. /* let us set for next next DMA transfer */
  644. temp = dac->nextOut + dac->fragSize*2;
  645. if (temp >= dac->fragTotalSize) {
  646. ASSERT( (temp == dac->fragTotalSize) ||
  647. (temp == dac->fragTotalSize + dac->fragSize) );
  648. temp -= dac->fragTotalSize;
  649. }
  650. outl(dac->lbufDma + temp, s->io + VRC5477_DAC1_BADDR);
  651. if (s->dacChannels == 1) {
  652. outl(dac->lbufDma + temp, s->io + VRC5477_DAC2_BADDR);
  653. } else {
  654. outl(dac->rbufDma + temp, s->io + VRC5477_DAC2_BADDR);
  655. }
  656. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  657. if (*(u16*)(dac->lbuf + dac->nextOut) != outTicket) {
  658. printk("assert fail: - %d vs %d\n",
  659. *(u16*)(dac->lbuf + dac->nextOut),
  660. outTicket);
  661. ASSERT(1 == 0);
  662. }
  663. #endif
  664. /* adjust nextOut pointer */
  665. dac->nextOut += dac->fragSize;
  666. if (dac->nextOut >= dac->fragTotalSize) {
  667. ASSERT(dac->nextOut == dac->fragTotalSize);
  668. dac->nextOut = 0;
  669. }
  670. /* adjust count */
  671. dac->count -= dac->fragSize;
  672. if (dac->count <=0 ) {
  673. /* buffer under run */
  674. dac->count = 0;
  675. dac->nextIn = dac->nextOut;
  676. stop_dac(s);
  677. }
  678. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  679. if (dac->count) {
  680. outTicket ++;
  681. ASSERT(*(u16*)(dac->lbuf + dac->nextOut) == outTicket);
  682. }
  683. #endif
  684. /* we cannot have both under run and someone is waiting on us */
  685. ASSERT(! (waitqueue_active(&dac->wait) && (dac->count <= 0)) );
  686. /* wake up anybody listening */
  687. if (waitqueue_active(&dac->wait))
  688. wake_up_interruptible(&dac->wait);
  689. }
  690. static irqreturn_t vrc5477_ac97_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  691. {
  692. struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)dev_id;
  693. u32 irqStatus;
  694. u32 adcInterrupts, dacInterrupts;
  695. spin_lock(&s->lock);
  696. /* get irqStatus and clear the detected ones */
  697. irqStatus = inl(s->io + VRC5477_INT_STATUS);
  698. outl(irqStatus, s->io + VRC5477_INT_CLR);
  699. /* let us see what we get */
  700. dacInterrupts = VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END;
  701. adcInterrupts = VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END;
  702. if (irqStatus & dacInterrupts) {
  703. /* we should get both interrupts, but just in case ... */
  704. if (irqStatus & VRC5477_INT_MASK_DAC1END) {
  705. vrc5477_ac97_dac_interrupt(s);
  706. }
  707. if ( (irqStatus & dacInterrupts) != dacInterrupts ) {
  708. printk(KERN_WARNING "vrc5477_ac97 : dac interrupts not in sync!!!\n");
  709. stop_dac(s);
  710. start_dac(s);
  711. }
  712. } else if (irqStatus & adcInterrupts) {
  713. /* we should get both interrupts, but just in case ... */
  714. if(irqStatus & VRC5477_INT_MASK_ADC1END) {
  715. vrc5477_ac97_adc_interrupt(s);
  716. }
  717. if ( (irqStatus & adcInterrupts) != adcInterrupts ) {
  718. printk(KERN_WARNING "vrc5477_ac97 : adc interrupts not in sync!!!\n");
  719. stop_adc(s);
  720. start_adc(s);
  721. }
  722. }
  723. spin_unlock(&s->lock);
  724. return IRQ_HANDLED;
  725. }
  726. /* --------------------------------------------------------------------- */
  727. static int vrc5477_ac97_open_mixdev(struct inode *inode, struct file *file)
  728. {
  729. int minor = iminor(inode);
  730. struct list_head *list;
  731. struct vrc5477_ac97_state *s;
  732. for (list = devs.next; ; list = list->next) {
  733. if (list == &devs)
  734. return -ENODEV;
  735. s = list_entry(list, struct vrc5477_ac97_state, devs);
  736. if (s->codec->dev_mixer == minor)
  737. break;
  738. }
  739. file->private_data = s;
  740. return nonseekable_open(inode, file);
  741. }
  742. static int vrc5477_ac97_release_mixdev(struct inode *inode, struct file *file)
  743. {
  744. return 0;
  745. }
  746. static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  747. unsigned long arg)
  748. {
  749. return codec->mixer_ioctl(codec, cmd, arg);
  750. }
  751. static int vrc5477_ac97_ioctl_mixdev(struct inode *inode, struct file *file,
  752. unsigned int cmd, unsigned long arg)
  753. {
  754. struct vrc5477_ac97_state *s =
  755. (struct vrc5477_ac97_state *)file->private_data;
  756. struct ac97_codec *codec = s->codec;
  757. return mixdev_ioctl(codec, cmd, arg);
  758. }
  759. static /*const*/ struct file_operations vrc5477_ac97_mixer_fops = {
  760. .owner = THIS_MODULE,
  761. .llseek = no_llseek,
  762. .ioctl = vrc5477_ac97_ioctl_mixdev,
  763. .open = vrc5477_ac97_open_mixdev,
  764. .release = vrc5477_ac97_release_mixdev,
  765. };
  766. /* --------------------------------------------------------------------- */
  767. static int drain_dac(struct vrc5477_ac97_state *s, int nonblock)
  768. {
  769. unsigned long flags;
  770. int count, tmo;
  771. if (!s->dma_dac.ready)
  772. return 0;
  773. for (;;) {
  774. spin_lock_irqsave(&s->lock, flags);
  775. count = s->dma_dac.count;
  776. spin_unlock_irqrestore(&s->lock, flags);
  777. if (count <= 0)
  778. break;
  779. if (signal_pending(current))
  780. break;
  781. if (nonblock)
  782. return -EBUSY;
  783. tmo = 1000 * count / s->dacRate / 2;
  784. vrc5477_ac97_delay(tmo);
  785. }
  786. if (signal_pending(current))
  787. return -ERESTARTSYS;
  788. return 0;
  789. }
  790. /* --------------------------------------------------------------------- */
  791. static inline int
  792. copy_two_channel_adc_to_user(struct vrc5477_ac97_state *s,
  793. char *buffer,
  794. int copyCount)
  795. {
  796. struct dmabuf *db = &s->dma_adc;
  797. int bufStart = db->nextOut;
  798. for (; copyCount > 0; ) {
  799. int i;
  800. int count = copyCount;
  801. if (count > WORK_BUF_SIZE/2) count = WORK_BUF_SIZE/2;
  802. for (i=0; i< count/2; i++) {
  803. s->workBuf[i].lchannel =
  804. *(u16*)(db->lbuf + bufStart + i*2);
  805. s->workBuf[i].rchannel =
  806. *(u16*)(db->rbuf + bufStart + i*2);
  807. }
  808. if (copy_to_user(buffer, s->workBuf, count*2)) {
  809. return -1;
  810. }
  811. copyCount -= count;
  812. bufStart += count;
  813. ASSERT(bufStart <= db->fragTotalSize);
  814. buffer += count *2;
  815. }
  816. return 0;
  817. }
  818. /* return the total bytes that is copied */
  819. static inline int
  820. copy_adc_to_user(struct vrc5477_ac97_state *s,
  821. char * buffer,
  822. size_t count,
  823. int avail)
  824. {
  825. struct dmabuf *db = &s->dma_adc;
  826. int copyCount=0;
  827. int copyFragCount=0;
  828. int totalCopyCount = 0;
  829. int totalCopyFragCount = 0;
  830. unsigned long flags;
  831. /* adjust count to signel channel byte count */
  832. count >>= s->adcChannels - 1;
  833. /* we may have to "copy" twice as ring buffer wraps around */
  834. for (; (avail > 0) && (count > 0); ) {
  835. /* determine max possible copy count for single channel */
  836. copyCount = count;
  837. if (copyCount > avail) {
  838. copyCount = avail;
  839. }
  840. if (copyCount + db->nextOut > db->fragTotalSize) {
  841. copyCount = db->fragTotalSize - db->nextOut;
  842. ASSERT((copyCount % db->fragSize) == 0);
  843. }
  844. copyFragCount = (copyCount-1) >> db->fragShift;
  845. copyFragCount = (copyFragCount+1) << db->fragShift;
  846. ASSERT(copyFragCount >= copyCount);
  847. /* we copy differently based on adc channels */
  848. if (s->adcChannels == 1) {
  849. if (copy_to_user(buffer,
  850. db->lbuf + db->nextOut,
  851. copyCount))
  852. return -1;
  853. } else {
  854. /* *sigh* we have to mix two streams into one */
  855. if (copy_two_channel_adc_to_user(s, buffer, copyCount))
  856. return -1;
  857. }
  858. count -= copyCount;
  859. totalCopyCount += copyCount;
  860. avail -= copyFragCount;
  861. totalCopyFragCount += copyFragCount;
  862. buffer += copyCount << (s->adcChannels-1);
  863. db->nextOut += copyFragCount;
  864. if (db->nextOut >= db->fragTotalSize) {
  865. ASSERT(db->nextOut == db->fragTotalSize);
  866. db->nextOut = 0;
  867. }
  868. ASSERT((copyFragCount % db->fragSize) == 0);
  869. ASSERT( (count == 0) || (copyCount == copyFragCount));
  870. }
  871. spin_lock_irqsave(&s->lock, flags);
  872. db->count -= totalCopyFragCount;
  873. spin_unlock_irqrestore(&s->lock, flags);
  874. return totalCopyCount << (s->adcChannels-1);
  875. }
  876. static ssize_t
  877. vrc5477_ac97_read(struct file *file,
  878. char *buffer,
  879. size_t count,
  880. loff_t *ppos)
  881. {
  882. struct vrc5477_ac97_state *s =
  883. (struct vrc5477_ac97_state *)file->private_data;
  884. struct dmabuf *db = &s->dma_adc;
  885. ssize_t ret = 0;
  886. unsigned long flags;
  887. int copyCount;
  888. size_t avail;
  889. if (!access_ok(VERIFY_WRITE, buffer, count))
  890. return -EFAULT;
  891. ASSERT(db->ready);
  892. while (count > 0) {
  893. // wait for samples in capture buffer
  894. do {
  895. spin_lock_irqsave(&s->lock, flags);
  896. if (db->stopped)
  897. start_adc(s);
  898. avail = db->count;
  899. spin_unlock_irqrestore(&s->lock, flags);
  900. if (avail <= 0) {
  901. if (file->f_flags & O_NONBLOCK) {
  902. if (!ret)
  903. ret = -EAGAIN;
  904. return ret;
  905. }
  906. interruptible_sleep_on(&db->wait);
  907. if (signal_pending(current)) {
  908. if (!ret)
  909. ret = -ERESTARTSYS;
  910. return ret;
  911. }
  912. }
  913. } while (avail <= 0);
  914. ASSERT( (avail % db->fragSize) == 0);
  915. copyCount = copy_adc_to_user(s, buffer, count, avail);
  916. if (copyCount <=0 ) {
  917. if (!ret) ret = -EFAULT;
  918. return ret;
  919. }
  920. count -= copyCount;
  921. buffer += copyCount;
  922. ret += copyCount;
  923. } // while (count > 0)
  924. return ret;
  925. }
  926. static inline int
  927. copy_two_channel_dac_from_user(struct vrc5477_ac97_state *s,
  928. const char *buffer,
  929. int copyCount)
  930. {
  931. struct dmabuf *db = &s->dma_dac;
  932. int bufStart = db->nextIn;
  933. ASSERT(db->ready);
  934. for (; copyCount > 0; ) {
  935. int i;
  936. int count = copyCount;
  937. if (count > WORK_BUF_SIZE/2) count = WORK_BUF_SIZE/2;
  938. if (copy_from_user(s->workBuf, buffer, count*2)) {
  939. return -1;
  940. }
  941. for (i=0; i< count/2; i++) {
  942. *(u16*)(db->lbuf + bufStart + i*2) =
  943. s->workBuf[i].lchannel;
  944. *(u16*)(db->rbuf + bufStart + i*2) =
  945. s->workBuf[i].rchannel;
  946. }
  947. copyCount -= count;
  948. bufStart += count;
  949. ASSERT(bufStart <= db->fragTotalSize);
  950. buffer += count *2;
  951. }
  952. return 0;
  953. }
  954. /* return the total bytes that is copied */
  955. static inline int
  956. copy_dac_from_user(struct vrc5477_ac97_state *s,
  957. const char *buffer,
  958. size_t count,
  959. int avail)
  960. {
  961. struct dmabuf *db = &s->dma_dac;
  962. int copyCount=0;
  963. int copyFragCount=0;
  964. int totalCopyCount = 0;
  965. int totalCopyFragCount = 0;
  966. unsigned long flags;
  967. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  968. int i;
  969. #endif
  970. /* adjust count to signel channel byte count */
  971. count >>= s->dacChannels - 1;
  972. /* we may have to "copy" twice as ring buffer wraps around */
  973. for (; (avail > 0) && (count > 0); ) {
  974. /* determine max possible copy count for single channel */
  975. copyCount = count;
  976. if (copyCount > avail) {
  977. copyCount = avail;
  978. }
  979. if (copyCount + db->nextIn > db->fragTotalSize) {
  980. copyCount = db->fragTotalSize - db->nextIn;
  981. ASSERT(copyCount > 0);
  982. }
  983. copyFragCount = copyCount;
  984. ASSERT(copyFragCount >= copyCount);
  985. /* we copy differently based on the number channels */
  986. if (s->dacChannels == 1) {
  987. if (copy_from_user(db->lbuf + db->nextIn,
  988. buffer,
  989. copyCount))
  990. return -1;
  991. /* fill gaps with 0 */
  992. memset(db->lbuf + db->nextIn + copyCount,
  993. 0,
  994. copyFragCount - copyCount);
  995. } else {
  996. /* we have demux the stream into two separate ones */
  997. if (copy_two_channel_dac_from_user(s, buffer, copyCount))
  998. return -1;
  999. /* fill gaps with 0 */
  1000. memset(db->lbuf + db->nextIn + copyCount,
  1001. 0,
  1002. copyFragCount - copyCount);
  1003. memset(db->rbuf + db->nextIn + copyCount,
  1004. 0,
  1005. copyFragCount - copyCount);
  1006. }
  1007. #if defined(VRC5477_AC97_VERBOSE_DEBUG)
  1008. for (i=0; i< copyFragCount; i+= db->fragSize) {
  1009. *(u16*)(db->lbuf + db->nextIn + i) = inTicket ++;
  1010. }
  1011. #endif
  1012. count -= copyCount;
  1013. totalCopyCount += copyCount;
  1014. avail -= copyFragCount;
  1015. totalCopyFragCount += copyFragCount;
  1016. buffer += copyCount << (s->dacChannels - 1);
  1017. db->nextIn += copyFragCount;
  1018. if (db->nextIn >= db->fragTotalSize) {
  1019. ASSERT(db->nextIn == db->fragTotalSize);
  1020. db->nextIn = 0;
  1021. }
  1022. ASSERT( (count == 0) || (copyCount == copyFragCount));
  1023. }
  1024. spin_lock_irqsave(&s->lock, flags);
  1025. db->count += totalCopyFragCount;
  1026. if (db->stopped) {
  1027. start_dac(s);
  1028. }
  1029. /* nextIn should not be equal to nextOut unless we are full */
  1030. ASSERT( ( (db->count == db->fragTotalSize) &&
  1031. (db->nextIn == db->nextOut) ) ||
  1032. ( (db->count < db->fragTotalSize) &&
  1033. (db->nextIn != db->nextOut) ) );
  1034. spin_unlock_irqrestore(&s->lock, flags);
  1035. return totalCopyCount << (s->dacChannels-1);
  1036. }
  1037. static ssize_t vrc5477_ac97_write(struct file *file, const char *buffer,
  1038. size_t count, loff_t *ppos)
  1039. {
  1040. struct vrc5477_ac97_state *s =
  1041. (struct vrc5477_ac97_state *)file->private_data;
  1042. struct dmabuf *db = &s->dma_dac;
  1043. ssize_t ret;
  1044. unsigned long flags;
  1045. int copyCount, avail;
  1046. if (!access_ok(VERIFY_READ, buffer, count))
  1047. return -EFAULT;
  1048. ret = 0;
  1049. while (count > 0) {
  1050. // wait for space in playback buffer
  1051. do {
  1052. spin_lock_irqsave(&s->lock, flags);
  1053. avail = db->fragTotalSize - db->count;
  1054. spin_unlock_irqrestore(&s->lock, flags);
  1055. if (avail <= 0) {
  1056. if (file->f_flags & O_NONBLOCK) {
  1057. if (!ret)
  1058. ret = -EAGAIN;
  1059. return ret;
  1060. }
  1061. interruptible_sleep_on(&db->wait);
  1062. if (signal_pending(current)) {
  1063. if (!ret)
  1064. ret = -ERESTARTSYS;
  1065. return ret;
  1066. }
  1067. }
  1068. } while (avail <= 0);
  1069. copyCount = copy_dac_from_user(s, buffer, count, avail);
  1070. if (copyCount < 0) {
  1071. if (!ret) ret = -EFAULT;
  1072. return ret;
  1073. }
  1074. count -= copyCount;
  1075. buffer += copyCount;
  1076. ret += copyCount;
  1077. } // while (count > 0)
  1078. return ret;
  1079. }
  1080. /* No kernel lock - we have our own spinlock */
  1081. static unsigned int vrc5477_ac97_poll(struct file *file,
  1082. struct poll_table_struct *wait)
  1083. {
  1084. struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)file->private_data;
  1085. unsigned long flags;
  1086. unsigned int mask = 0;
  1087. if (file->f_mode & FMODE_WRITE)
  1088. poll_wait(file, &s->dma_dac.wait, wait);
  1089. if (file->f_mode & FMODE_READ)
  1090. poll_wait(file, &s->dma_adc.wait, wait);
  1091. spin_lock_irqsave(&s->lock, flags);
  1092. if (file->f_mode & FMODE_READ) {
  1093. if (s->dma_adc.count >= (signed)s->dma_adc.fragSize)
  1094. mask |= POLLIN | POLLRDNORM;
  1095. }
  1096. if (file->f_mode & FMODE_WRITE) {
  1097. if ((signed)s->dma_dac.fragTotalSize >=
  1098. s->dma_dac.count + (signed)s->dma_dac.fragSize)
  1099. mask |= POLLOUT | POLLWRNORM;
  1100. }
  1101. spin_unlock_irqrestore(&s->lock, flags);
  1102. return mask;
  1103. }
  1104. #ifdef VRC5477_AC97_DEBUG
  1105. static struct ioctl_str_t {
  1106. unsigned int cmd;
  1107. const char* str;
  1108. } ioctl_str[] = {
  1109. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1110. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1111. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1112. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1113. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1114. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1115. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1116. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1117. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1118. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1119. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1120. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1121. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1122. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1123. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1124. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1125. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1126. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1127. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1128. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1129. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1130. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1131. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1132. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1133. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1134. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1135. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1136. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1137. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1138. {OSS_GETVERSION, "OSS_GETVERSION"},
  1139. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1140. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1141. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1142. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1143. };
  1144. #endif
  1145. static int vrc5477_ac97_ioctl(struct inode *inode, struct file *file,
  1146. unsigned int cmd, unsigned long arg)
  1147. {
  1148. struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)file->private_data;
  1149. unsigned long flags;
  1150. audio_buf_info abinfo;
  1151. int count;
  1152. int val, ret;
  1153. #ifdef VRC5477_AC97_DEBUG
  1154. for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
  1155. if (ioctl_str[count].cmd == cmd)
  1156. break;
  1157. }
  1158. if (count < sizeof(ioctl_str)/sizeof(ioctl_str[0]))
  1159. printk(KERN_INFO PFX "ioctl %s\n", ioctl_str[count].str);
  1160. else
  1161. printk(KERN_INFO PFX "ioctl unknown, 0x%x\n", cmd);
  1162. #endif
  1163. switch (cmd) {
  1164. case OSS_GETVERSION:
  1165. return put_user(SOUND_VERSION, (int *)arg);
  1166. case SNDCTL_DSP_SYNC:
  1167. if (file->f_mode & FMODE_WRITE)
  1168. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1169. return 0;
  1170. case SNDCTL_DSP_SETDUPLEX:
  1171. return 0;
  1172. case SNDCTL_DSP_GETCAPS:
  1173. return put_user(DSP_CAP_DUPLEX, (int *)arg);
  1174. case SNDCTL_DSP_RESET:
  1175. if (file->f_mode & FMODE_WRITE) {
  1176. stop_dac(s);
  1177. synchronize_irq(s->irq);
  1178. s->dma_dac.count = 0;
  1179. s->dma_dac.nextIn = s->dma_dac.nextOut = 0;
  1180. }
  1181. if (file->f_mode & FMODE_READ) {
  1182. stop_adc(s);
  1183. synchronize_irq(s->irq);
  1184. s->dma_adc.count = 0;
  1185. s->dma_adc.nextIn = s->dma_adc.nextOut = 0;
  1186. }
  1187. return 0;
  1188. case SNDCTL_DSP_SPEED:
  1189. if (get_user(val, (int *)arg))
  1190. return -EFAULT;
  1191. if (val >= 0) {
  1192. if (file->f_mode & FMODE_READ) {
  1193. stop_adc(s);
  1194. set_adc_rate(s, val);
  1195. if ((ret = prog_dmabuf_adc(s)))
  1196. return ret;
  1197. }
  1198. if (file->f_mode & FMODE_WRITE) {
  1199. stop_dac(s);
  1200. set_dac_rate(s, val);
  1201. if ((ret = prog_dmabuf_dac(s)))
  1202. return ret;
  1203. }
  1204. }
  1205. return put_user((file->f_mode & FMODE_READ) ?
  1206. s->adcRate : s->dacRate, (int *)arg);
  1207. case SNDCTL_DSP_STEREO:
  1208. if (get_user(val, (int *)arg))
  1209. return -EFAULT;
  1210. if (file->f_mode & FMODE_READ) {
  1211. stop_adc(s);
  1212. if (val)
  1213. s->adcChannels = 2;
  1214. else
  1215. s->adcChannels = 1;
  1216. if ((ret = prog_dmabuf_adc(s)))
  1217. return ret;
  1218. }
  1219. if (file->f_mode & FMODE_WRITE) {
  1220. stop_dac(s);
  1221. if (val)
  1222. s->dacChannels = 2;
  1223. else
  1224. s->dacChannels = 1;
  1225. if ((ret = prog_dmabuf_dac(s)))
  1226. return ret;
  1227. }
  1228. return 0;
  1229. case SNDCTL_DSP_CHANNELS:
  1230. if (get_user(val, (int *)arg))
  1231. return -EFAULT;
  1232. if (val != 0) {
  1233. if ( (val != 1) && (val != 2)) val = 2;
  1234. if (file->f_mode & FMODE_READ) {
  1235. stop_adc(s);
  1236. s->dacChannels = val;
  1237. if ((ret = prog_dmabuf_adc(s)))
  1238. return ret;
  1239. }
  1240. if (file->f_mode & FMODE_WRITE) {
  1241. stop_dac(s);
  1242. s->dacChannels = val;
  1243. if ((ret = prog_dmabuf_dac(s)))
  1244. return ret;
  1245. }
  1246. }
  1247. return put_user(val, (int *)arg);
  1248. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1249. return put_user(AFMT_S16_LE, (int *)arg);
  1250. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1251. if (get_user(val, (int *)arg))
  1252. return -EFAULT;
  1253. if (val != AFMT_QUERY) {
  1254. if (val != AFMT_S16_LE) return -EINVAL;
  1255. if (file->f_mode & FMODE_READ) {
  1256. stop_adc(s);
  1257. if ((ret = prog_dmabuf_adc(s)))
  1258. return ret;
  1259. }
  1260. if (file->f_mode & FMODE_WRITE) {
  1261. stop_dac(s);
  1262. if ((ret = prog_dmabuf_dac(s)))
  1263. return ret;
  1264. }
  1265. } else {
  1266. val = AFMT_S16_LE;
  1267. }
  1268. return put_user(val, (int *)arg);
  1269. case SNDCTL_DSP_POST:
  1270. return 0;
  1271. case SNDCTL_DSP_GETTRIGGER:
  1272. case SNDCTL_DSP_SETTRIGGER:
  1273. /* NO trigger */
  1274. return -EINVAL;
  1275. case SNDCTL_DSP_GETOSPACE:
  1276. if (!(file->f_mode & FMODE_WRITE))
  1277. return -EINVAL;
  1278. abinfo.fragsize = s->dma_dac.fragSize << (s->dacChannels-1);
  1279. spin_lock_irqsave(&s->lock, flags);
  1280. count = s->dma_dac.count;
  1281. spin_unlock_irqrestore(&s->lock, flags);
  1282. abinfo.bytes = (s->dma_dac.fragTotalSize - count) <<
  1283. (s->dacChannels-1);
  1284. abinfo.fragstotal = s->dma_dac.numFrag;
  1285. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragShift >>
  1286. (s->dacChannels-1);
  1287. return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1288. case SNDCTL_DSP_GETISPACE:
  1289. if (!(file->f_mode & FMODE_READ))
  1290. return -EINVAL;
  1291. abinfo.fragsize = s->dma_adc.fragSize << (s->adcChannels-1);
  1292. spin_lock_irqsave(&s->lock, flags);
  1293. count = s->dma_adc.count;
  1294. spin_unlock_irqrestore(&s->lock, flags);
  1295. if (count < 0)
  1296. count = 0;
  1297. abinfo.bytes = count << (s->adcChannels-1);
  1298. abinfo.fragstotal = s->dma_adc.numFrag;
  1299. abinfo.fragments = (abinfo.bytes >> s->dma_adc.fragShift) >>
  1300. (s->adcChannels-1);
  1301. return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1302. case SNDCTL_DSP_NONBLOCK:
  1303. file->f_flags |= O_NONBLOCK;
  1304. return 0;
  1305. case SNDCTL_DSP_GETODELAY:
  1306. if (!(file->f_mode & FMODE_WRITE))
  1307. return -EINVAL;
  1308. spin_lock_irqsave(&s->lock, flags);
  1309. count = s->dma_dac.count;
  1310. spin_unlock_irqrestore(&s->lock, flags);
  1311. return put_user(count, (int *)arg);
  1312. case SNDCTL_DSP_GETIPTR:
  1313. case SNDCTL_DSP_GETOPTR:
  1314. /* we cannot get DMA ptr */
  1315. return -EINVAL;
  1316. case SNDCTL_DSP_GETBLKSIZE:
  1317. if (file->f_mode & FMODE_WRITE)
  1318. return put_user(s->dma_dac.fragSize << (s->dacChannels-1), (int *)arg);
  1319. else
  1320. return put_user(s->dma_adc.fragSize << (s->adcChannels-1), (int *)arg);
  1321. case SNDCTL_DSP_SETFRAGMENT:
  1322. /* we ignore fragment size request */
  1323. return 0;
  1324. case SNDCTL_DSP_SUBDIVIDE:
  1325. /* what is this for? [jsun] */
  1326. return 0;
  1327. case SOUND_PCM_READ_RATE:
  1328. return put_user((file->f_mode & FMODE_READ) ?
  1329. s->adcRate : s->dacRate, (int *)arg);
  1330. case SOUND_PCM_READ_CHANNELS:
  1331. if (file->f_mode & FMODE_READ)
  1332. return put_user(s->adcChannels, (int *)arg);
  1333. else
  1334. return put_user(s->dacChannels ? 2 : 1, (int *)arg);
  1335. case SOUND_PCM_READ_BITS:
  1336. return put_user(16, (int *)arg);
  1337. case SOUND_PCM_WRITE_FILTER:
  1338. case SNDCTL_DSP_SETSYNCRO:
  1339. case SOUND_PCM_READ_FILTER:
  1340. return -EINVAL;
  1341. }
  1342. return mixdev_ioctl(s->codec, cmd, arg);
  1343. }
  1344. static int vrc5477_ac97_open(struct inode *inode, struct file *file)
  1345. {
  1346. int minor = iminor(inode);
  1347. DECLARE_WAITQUEUE(wait, current);
  1348. unsigned long flags;
  1349. struct list_head *list;
  1350. struct vrc5477_ac97_state *s;
  1351. int ret=0;
  1352. nonseekable_open(inode, file);
  1353. for (list = devs.next; ; list = list->next) {
  1354. if (list == &devs)
  1355. return -ENODEV;
  1356. s = list_entry(list, struct vrc5477_ac97_state, devs);
  1357. if (!((s->dev_audio ^ minor) & ~0xf))
  1358. break;
  1359. }
  1360. file->private_data = s;
  1361. /* wait for device to become free */
  1362. down(&s->open_sem);
  1363. while (s->open_mode & file->f_mode) {
  1364. if (file->f_flags & O_NONBLOCK) {
  1365. up(&s->open_sem);
  1366. return -EBUSY;
  1367. }
  1368. add_wait_queue(&s->open_wait, &wait);
  1369. __set_current_state(TASK_INTERRUPTIBLE);
  1370. up(&s->open_sem);
  1371. schedule();
  1372. remove_wait_queue(&s->open_wait, &wait);
  1373. set_current_state(TASK_RUNNING);
  1374. if (signal_pending(current))
  1375. return -ERESTARTSYS;
  1376. down(&s->open_sem);
  1377. }
  1378. spin_lock_irqsave(&s->lock, flags);
  1379. if (file->f_mode & FMODE_READ) {
  1380. /* set default settings */
  1381. set_adc_rate(s, 48000);
  1382. s->adcChannels = 2;
  1383. ret = prog_dmabuf_adc(s);
  1384. if (ret) goto bailout;
  1385. }
  1386. if (file->f_mode & FMODE_WRITE) {
  1387. /* set default settings */
  1388. set_dac_rate(s, 48000);
  1389. s->dacChannels = 2;
  1390. ret = prog_dmabuf_dac(s);
  1391. if (ret) goto bailout;
  1392. }
  1393. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1394. bailout:
  1395. spin_unlock_irqrestore(&s->lock, flags);
  1396. up(&s->open_sem);
  1397. return ret;
  1398. }
  1399. static int vrc5477_ac97_release(struct inode *inode, struct file *file)
  1400. {
  1401. struct vrc5477_ac97_state *s =
  1402. (struct vrc5477_ac97_state *)file->private_data;
  1403. lock_kernel();
  1404. if (file->f_mode & FMODE_WRITE)
  1405. drain_dac(s, file->f_flags & O_NONBLOCK);
  1406. down(&s->open_sem);
  1407. if (file->f_mode & FMODE_WRITE) {
  1408. stop_dac(s);
  1409. dealloc_dmabuf(s, &s->dma_dac);
  1410. }
  1411. if (file->f_mode & FMODE_READ) {
  1412. stop_adc(s);
  1413. dealloc_dmabuf(s, &s->dma_adc);
  1414. }
  1415. s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
  1416. up(&s->open_sem);
  1417. wake_up(&s->open_wait);
  1418. unlock_kernel();
  1419. return 0;
  1420. }
  1421. static /*const*/ struct file_operations vrc5477_ac97_audio_fops = {
  1422. .owner = THIS_MODULE,
  1423. .llseek = no_llseek,
  1424. .read = vrc5477_ac97_read,
  1425. .write = vrc5477_ac97_write,
  1426. .poll = vrc5477_ac97_poll,
  1427. .ioctl = vrc5477_ac97_ioctl,
  1428. // .mmap = vrc5477_ac97_mmap,
  1429. .open = vrc5477_ac97_open,
  1430. .release = vrc5477_ac97_release,
  1431. };
  1432. /* --------------------------------------------------------------------- */
  1433. /* --------------------------------------------------------------------- */
  1434. /*
  1435. * for debugging purposes, we'll create a proc device that dumps the
  1436. * CODEC chipstate
  1437. */
  1438. #ifdef VRC5477_AC97_DEBUG
  1439. struct {
  1440. const char *regname;
  1441. unsigned regaddr;
  1442. } vrc5477_ac97_regs[] = {
  1443. {"VRC5477_INT_STATUS", VRC5477_INT_STATUS},
  1444. {"VRC5477_CODEC_WR", VRC5477_CODEC_WR},
  1445. {"VRC5477_CODEC_RD", VRC5477_CODEC_RD},
  1446. {"VRC5477_CTRL", VRC5477_CTRL},
  1447. {"VRC5477_ACLINK_CTRL", VRC5477_ACLINK_CTRL},
  1448. {"VRC5477_INT_MASK", VRC5477_INT_MASK},
  1449. {"VRC5477_DAC1_CTRL", VRC5477_DAC1_CTRL},
  1450. {"VRC5477_DAC1L", VRC5477_DAC1L},
  1451. {"VRC5477_DAC1_BADDR", VRC5477_DAC1_BADDR},
  1452. {"VRC5477_DAC2_CTRL", VRC5477_DAC2_CTRL},
  1453. {"VRC5477_DAC2L", VRC5477_DAC2L},
  1454. {"VRC5477_DAC2_BADDR", VRC5477_DAC2_BADDR},
  1455. {"VRC5477_DAC3_CTRL", VRC5477_DAC3_CTRL},
  1456. {"VRC5477_DAC3L", VRC5477_DAC3L},
  1457. {"VRC5477_DAC3_BADDR", VRC5477_DAC3_BADDR},
  1458. {"VRC5477_ADC1_CTRL", VRC5477_ADC1_CTRL},
  1459. {"VRC5477_ADC1L", VRC5477_ADC1L},
  1460. {"VRC5477_ADC1_BADDR", VRC5477_ADC1_BADDR},
  1461. {"VRC5477_ADC2_CTRL", VRC5477_ADC2_CTRL},
  1462. {"VRC5477_ADC2L", VRC5477_ADC2L},
  1463. {"VRC5477_ADC2_BADDR", VRC5477_ADC2_BADDR},
  1464. {"VRC5477_ADC3_CTRL", VRC5477_ADC3_CTRL},
  1465. {"VRC5477_ADC3L", VRC5477_ADC3L},
  1466. {"VRC5477_ADC3_BADDR", VRC5477_ADC3_BADDR},
  1467. {NULL, 0x0}
  1468. };
  1469. static int proc_vrc5477_ac97_dump (char *buf, char **start, off_t fpos,
  1470. int length, int *eof, void *data)
  1471. {
  1472. struct vrc5477_ac97_state *s;
  1473. int cnt, len = 0;
  1474. if (list_empty(&devs))
  1475. return 0;
  1476. s = list_entry(devs.next, struct vrc5477_ac97_state, devs);
  1477. /* print out header */
  1478. len += sprintf(buf + len, "\n\t\tVrc5477 Audio Debug\n\n");
  1479. // print out digital controller state
  1480. len += sprintf (buf + len, "NEC Vrc5477 Audio Controller registers\n");
  1481. len += sprintf (buf + len, "---------------------------------\n");
  1482. for (cnt=0; vrc5477_ac97_regs[cnt].regname != NULL; cnt++) {
  1483. len+= sprintf (buf + len, "%-20s = %08x\n",
  1484. vrc5477_ac97_regs[cnt].regname,
  1485. inl(s->io + vrc5477_ac97_regs[cnt].regaddr));
  1486. }
  1487. /* print out driver state */
  1488. len += sprintf (buf + len, "NEC Vrc5477 Audio driver states\n");
  1489. len += sprintf (buf + len, "---------------------------------\n");
  1490. len += sprintf (buf + len, "dacChannels = %d\n", s->dacChannels);
  1491. len += sprintf (buf + len, "adcChannels = %d\n", s->adcChannels);
  1492. len += sprintf (buf + len, "dacRate = %d\n", s->dacRate);
  1493. len += sprintf (buf + len, "adcRate = %d\n", s->adcRate);
  1494. len += sprintf (buf + len, "dma_dac is %s ready\n",
  1495. s->dma_dac.ready? "" : "not");
  1496. if (s->dma_dac.ready) {
  1497. len += sprintf (buf + len, "dma_dac is %s stopped.\n",
  1498. s->dma_dac.stopped? "" : "not");
  1499. len += sprintf (buf + len, "dma_dac.fragSize = %x\n",
  1500. s->dma_dac.fragSize);
  1501. len += sprintf (buf + len, "dma_dac.fragShift = %x\n",
  1502. s->dma_dac.fragShift);
  1503. len += sprintf (buf + len, "dma_dac.numFrag = %x\n",
  1504. s->dma_dac.numFrag);
  1505. len += sprintf (buf + len, "dma_dac.fragTotalSize = %x\n",
  1506. s->dma_dac.fragTotalSize);
  1507. len += sprintf (buf + len, "dma_dac.nextIn = %x\n",
  1508. s->dma_dac.nextIn);
  1509. len += sprintf (buf + len, "dma_dac.nextOut = %x\n",
  1510. s->dma_dac.nextOut);
  1511. len += sprintf (buf + len, "dma_dac.count = %x\n",
  1512. s->dma_dac.count);
  1513. }
  1514. len += sprintf (buf + len, "dma_adc is %s ready\n",
  1515. s->dma_adc.ready? "" : "not");
  1516. if (s->dma_adc.ready) {
  1517. len += sprintf (buf + len, "dma_adc is %s stopped.\n",
  1518. s->dma_adc.stopped? "" : "not");
  1519. len += sprintf (buf + len, "dma_adc.fragSize = %x\n",
  1520. s->dma_adc.fragSize);
  1521. len += sprintf (buf + len, "dma_adc.fragShift = %x\n",
  1522. s->dma_adc.fragShift);
  1523. len += sprintf (buf + len, "dma_adc.numFrag = %x\n",
  1524. s->dma_adc.numFrag);
  1525. len += sprintf (buf + len, "dma_adc.fragTotalSize = %x\n",
  1526. s->dma_adc.fragTotalSize);
  1527. len += sprintf (buf + len, "dma_adc.nextIn = %x\n",
  1528. s->dma_adc.nextIn);
  1529. len += sprintf (buf + len, "dma_adc.nextOut = %x\n",
  1530. s->dma_adc.nextOut);
  1531. len += sprintf (buf + len, "dma_adc.count = %x\n",
  1532. s->dma_adc.count);
  1533. }
  1534. /* print out CODEC state */
  1535. len += sprintf (buf + len, "\nAC97 CODEC registers\n");
  1536. len += sprintf (buf + len, "----------------------\n");
  1537. for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
  1538. len+= sprintf (buf + len, "reg %02x = %04x\n",
  1539. cnt, rdcodec(s->codec, cnt));
  1540. if (fpos >=len){
  1541. *start = buf;
  1542. *eof =1;
  1543. return 0;
  1544. }
  1545. *start = buf + fpos;
  1546. if ((len -= fpos) > length)
  1547. return length;
  1548. *eof =1;
  1549. return len;
  1550. }
  1551. #endif /* VRC5477_AC97_DEBUG */
  1552. /* --------------------------------------------------------------------- */
  1553. /* maximum number of devices; only used for command line params */
  1554. #define NR_DEVICE 5
  1555. static unsigned int devindex;
  1556. MODULE_AUTHOR("Monta Vista Software, jsun@mvista.com or jsun@junsun.net");
  1557. MODULE_DESCRIPTION("NEC Vrc5477 audio (AC97) Driver");
  1558. MODULE_LICENSE("GPL");
  1559. static int __devinit vrc5477_ac97_probe(struct pci_dev *pcidev,
  1560. const struct pci_device_id *pciid)
  1561. {
  1562. struct vrc5477_ac97_state *s;
  1563. #ifdef VRC5477_AC97_DEBUG
  1564. char proc_str[80];
  1565. #endif
  1566. if (pcidev->irq == 0)
  1567. return -1;
  1568. if (!(s = kmalloc(sizeof(struct vrc5477_ac97_state), GFP_KERNEL))) {
  1569. printk(KERN_ERR PFX "alloc of device struct failed\n");
  1570. return -1;
  1571. }
  1572. memset(s, 0, sizeof(struct vrc5477_ac97_state));
  1573. init_waitqueue_head(&s->dma_adc.wait);
  1574. init_waitqueue_head(&s->dma_dac.wait);
  1575. init_waitqueue_head(&s->open_wait);
  1576. init_MUTEX(&s->open_sem);
  1577. spin_lock_init(&s->lock);
  1578. s->dev = pcidev;
  1579. s->io = pci_resource_start(pcidev, 0);
  1580. s->irq = pcidev->irq;
  1581. s->codec = ac97_alloc_codec();
  1582. s->codec->private_data = s;
  1583. s->codec->id = 0;
  1584. s->codec->codec_read = rdcodec;
  1585. s->codec->codec_write = wrcodec;
  1586. s->codec->codec_wait = waitcodec;
  1587. /* setting some other default values such as
  1588. * adcChannels, adcRate is done in open() so that
  1589. * no persistent state across file opens.
  1590. */
  1591. /* test if get response from ac97, if not return */
  1592. if (ac97_codec_not_present(s->codec)) {
  1593. printk(KERN_ERR PFX "no ac97 codec\n");
  1594. goto err_region;
  1595. }
  1596. /* test if get response from ac97, if not return */
  1597. if (ac97_codec_not_present(&(s->codec))) {
  1598. printk(KERN_ERR PFX "no ac97 codec\n");
  1599. goto err_region;
  1600. }
  1601. if (!request_region(s->io, pci_resource_len(pcidev,0),
  1602. VRC5477_AC97_MODULE_NAME)) {
  1603. printk(KERN_ERR PFX "io ports %#lx->%#lx in use\n",
  1604. s->io, s->io + pci_resource_len(pcidev,0)-1);
  1605. goto err_region;
  1606. }
  1607. if (request_irq(s->irq, vrc5477_ac97_interrupt, SA_INTERRUPT,
  1608. VRC5477_AC97_MODULE_NAME, s)) {
  1609. printk(KERN_ERR PFX "irq %u in use\n", s->irq);
  1610. goto err_irq;
  1611. }
  1612. printk(KERN_INFO PFX "IO at %#lx, IRQ %d\n", s->io, s->irq);
  1613. /* register devices */
  1614. if ((s->dev_audio = register_sound_dsp(&vrc5477_ac97_audio_fops, -1)) < 0)
  1615. goto err_dev1;
  1616. if ((s->codec->dev_mixer =
  1617. register_sound_mixer(&vrc5477_ac97_mixer_fops, -1)) < 0)
  1618. goto err_dev2;
  1619. #ifdef VRC5477_AC97_DEBUG
  1620. /* initialize the debug proc device */
  1621. s->ps = create_proc_read_entry(VRC5477_AC97_MODULE_NAME, 0, NULL,
  1622. proc_vrc5477_ac97_dump, NULL);
  1623. #endif /* VRC5477_AC97_DEBUG */
  1624. /* enable pci io and bus mastering */
  1625. if (pci_enable_device(pcidev))
  1626. goto err_dev3;
  1627. pci_set_master(pcidev);
  1628. /* cold reset the AC97 */
  1629. outl(VRC5477_ACLINK_CTRL_RST_ON | VRC5477_ACLINK_CTRL_RST_TIME,
  1630. s->io + VRC5477_ACLINK_CTRL);
  1631. while (inl(s->io + VRC5477_ACLINK_CTRL) & VRC5477_ACLINK_CTRL_RST_ON);
  1632. /* codec init */
  1633. if (!ac97_probe_codec(s->codec))
  1634. goto err_dev3;
  1635. #ifdef VRC5477_AC97_DEBUG
  1636. sprintf(proc_str, "driver/%s/%d/ac97",
  1637. VRC5477_AC97_MODULE_NAME, s->codec->id);
  1638. s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
  1639. ac97_read_proc, s->codec);
  1640. /* TODO : why this proc file does not show up? */
  1641. #endif
  1642. /* Try to enable variable rate audio mode. */
  1643. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1644. rdcodec(s->codec, AC97_EXTENDED_STATUS) | AC97_EXTSTAT_VRA);
  1645. /* Did we enable it? */
  1646. if(rdcodec(s->codec, AC97_EXTENDED_STATUS) & AC97_EXTSTAT_VRA)
  1647. s->extended_status |= AC97_EXTSTAT_VRA;
  1648. else {
  1649. s->dacRate = 48000;
  1650. printk(KERN_INFO PFX "VRA mode not enabled; rate fixed at %d.",
  1651. s->dacRate);
  1652. }
  1653. /* let us get the default volumne louder */
  1654. wrcodec(s->codec, 0x2, 0x1010); /* master volume, middle */
  1655. wrcodec(s->codec, 0xc, 0x10); /* phone volume, middle */
  1656. // wrcodec(s->codec, 0xe, 0x10); /* misc volume, middle */
  1657. wrcodec(s->codec, 0x10, 0x8000); /* line-in 2 line-out disable */
  1658. wrcodec(s->codec, 0x18, 0x0707); /* PCM out (line out) middle */
  1659. /* by default we select line in the input */
  1660. wrcodec(s->codec, 0x1a, 0x0404);
  1661. wrcodec(s->codec, 0x1c, 0x0f0f);
  1662. wrcodec(s->codec, 0x1e, 0x07);
  1663. /* enable the master interrupt but disable all others */
  1664. outl(VRC5477_INT_MASK_NMASK, s->io + VRC5477_INT_MASK);
  1665. /* store it in the driver field */
  1666. pci_set_drvdata(pcidev, s);
  1667. pcidev->dma_mask = 0xffffffff;
  1668. /* put it into driver list */
  1669. list_add_tail(&s->devs, &devs);
  1670. /* increment devindex */
  1671. if (devindex < NR_DEVICE-1)
  1672. devindex++;
  1673. return 0;
  1674. err_dev3:
  1675. unregister_sound_mixer(s->codec->dev_mixer);
  1676. err_dev2:
  1677. unregister_sound_dsp(s->dev_audio);
  1678. err_dev1:
  1679. printk(KERN_ERR PFX "cannot register misc device\n");
  1680. free_irq(s->irq, s);
  1681. err_irq:
  1682. release_region(s->io, pci_resource_len(pcidev,0));
  1683. err_region:
  1684. ac97_release_codec(codec);
  1685. kfree(s);
  1686. return -1;
  1687. }
  1688. static void __devexit vrc5477_ac97_remove(struct pci_dev *dev)
  1689. {
  1690. struct vrc5477_ac97_state *s = pci_get_drvdata(dev);
  1691. if (!s)
  1692. return;
  1693. list_del(&s->devs);
  1694. #ifdef VRC5477_AC97_DEBUG
  1695. if (s->ps)
  1696. remove_proc_entry(VRC5477_AC97_MODULE_NAME, NULL);
  1697. #endif /* VRC5477_AC97_DEBUG */
  1698. synchronize_irq();
  1699. free_irq(s->irq, s);
  1700. release_region(s->io, pci_resource_len(dev,0));
  1701. unregister_sound_dsp(s->dev_audio);
  1702. unregister_sound_mixer(s->codec->dev_mixer);
  1703. ac97_release_codec(s->codec);
  1704. kfree(s);
  1705. pci_set_drvdata(dev, NULL);
  1706. }
  1707. static struct pci_device_id id_table[] = {
  1708. { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_VRC5477_AC97,
  1709. PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  1710. { 0, }
  1711. };
  1712. MODULE_DEVICE_TABLE(pci, id_table);
  1713. static struct pci_driver vrc5477_ac97_driver = {
  1714. .name = VRC5477_AC97_MODULE_NAME,
  1715. .id_table = id_table,
  1716. .probe = vrc5477_ac97_probe,
  1717. .remove = __devexit_p(vrc5477_ac97_remove)
  1718. };
  1719. static int __init init_vrc5477_ac97(void)
  1720. {
  1721. printk("Vrc5477 AC97 driver: version v0.2 time " __TIME__ " " __DATE__ " by Jun Sun\n");
  1722. return pci_register_driver(&vrc5477_ac97_driver);
  1723. }
  1724. static void __exit cleanup_vrc5477_ac97(void)
  1725. {
  1726. printk(KERN_INFO PFX "unloading\n");
  1727. pci_unregister_driver(&vrc5477_ac97_driver);
  1728. }
  1729. module_init(init_vrc5477_ac97);
  1730. module_exit(cleanup_vrc5477_ac97);