es1371.c 93 KB

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  1. /*****************************************************************************/
  2. /*
  3. * es1371.c -- Creative Ensoniq ES1371.
  4. *
  5. * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. * Special thanks to Ensoniq
  22. *
  23. * Supported devices:
  24. * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
  25. * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
  26. * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
  27. * /dev/midi simple MIDI UART interface, no ioctl
  28. *
  29. * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
  30. * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
  31. * there are several MIDI to PCM (WAV) packages, one of them is timidity.
  32. *
  33. * Revision history
  34. * 04.06.1998 0.1 Initial release
  35. * Mixer stuff should be overhauled; especially optional AC97 mixer bits
  36. * should be detected. This results in strange behaviour of some mixer
  37. * settings, like master volume and mic.
  38. * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
  39. * 03.08.1998 0.3 Do not include modversions.h
  40. * Now mixer behaviour can basically be selected between
  41. * "OSS documented" and "OSS actual" behaviour
  42. * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
  43. * 27.10.1998 0.5 Fix joystick support
  44. * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
  45. * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
  46. * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
  47. * Don't wake up app until there are fragsize bytes to read/write
  48. * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
  49. * hopefully killed the egcs section type conflict
  50. * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
  51. * reported by Johan Maes <joma@telindus.be>
  52. * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
  53. * read/write cannot be executed
  54. * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
  55. * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
  56. * Alpha fixes reported by Peter Jones <pjones@redhat.com>
  57. * Another Alpha fix (wait_src_ready in init routine)
  58. * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
  59. * Note: joystick address handling might still be wrong on archs
  60. * other than i386
  61. * 15.06.1999 0.12 Fix bad allocation bug.
  62. * Thanks to Deti Fliegl <fliegl@in.tum.de>
  63. * 28.06.1999 0.13 Add pci_set_master
  64. * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
  65. * added kernel command line option "es1371=joystickaddr"
  66. * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
  67. * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
  68. * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
  69. * module_init/__setup fixes
  70. * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
  71. * Added detection for ES1371 revision ID so that we can
  72. * detect the ES1373 and later parts.
  73. * added AC97 #defines for readability
  74. * added a /proc file system for dumping hardware state
  75. * updated SRC and CODEC w/r functions to accommodate bugs
  76. * in some versions of the ES137x chips.
  77. * 31.08.1999 0.17 add spin_lock_init
  78. * replaced current->state = x with set_current_state(x)
  79. * 03.09.1999 0.18 change read semantics for MIDI to match
  80. * OSS more closely; remove possible wakeup race
  81. * 21.10.1999 0.19 Round sampling rates, requested by
  82. * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
  83. * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
  84. * Codec ID printing changes
  85. * 28.10.1999 0.21 More waitqueue races fixed
  86. * Joe Cotellese <joec@ensoniq.com>
  87. * Changed PCI detection routine so we can more easily
  88. * detect ES137x chip and derivatives.
  89. * 05.01.2000 0.22 Should now work with rev7 boards; patch by
  90. * Eric Lemar, elemar@cs.washington.edu
  91. * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
  92. * Tim Janik's BSE (Bedevilled Sound Engine) found this
  93. * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
  94. * 07.02.2000 0.25 Use ac97_codec
  95. * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
  96. * Use pci_module_init
  97. * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
  98. * 12.12.2000 0.28 More dma buffer initializations, patch from
  99. * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
  100. * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
  101. * the CT5880 revision.
  102. * suggested by Stephan Müller <smueller@chronox.de>
  103. * 31.01.2001 0.30 Register/Unregister gameport
  104. * Fix SETTRIGGER non OSS API conformity
  105. * 14.07.2001 0.31 Add list of laptops needing amplifier control
  106. * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
  107. */
  108. /*****************************************************************************/
  109. #include <linux/interrupt.h>
  110. #include <linux/module.h>
  111. #include <linux/string.h>
  112. #include <linux/ioport.h>
  113. #include <linux/sched.h>
  114. #include <linux/delay.h>
  115. #include <linux/sound.h>
  116. #include <linux/slab.h>
  117. #include <linux/soundcard.h>
  118. #include <linux/pci.h>
  119. #include <linux/init.h>
  120. #include <linux/poll.h>
  121. #include <linux/bitops.h>
  122. #include <linux/proc_fs.h>
  123. #include <linux/spinlock.h>
  124. #include <linux/smp_lock.h>
  125. #include <linux/ac97_codec.h>
  126. #include <linux/gameport.h>
  127. #include <linux/wait.h>
  128. #include <linux/dma-mapping.h>
  129. #include <asm/io.h>
  130. #include <asm/page.h>
  131. #include <asm/uaccess.h>
  132. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  133. #define SUPPORT_JOYSTICK
  134. #endif
  135. /* --------------------------------------------------------------------- */
  136. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  137. #define ES1371_DEBUG
  138. #define DBG(x) {}
  139. /*#define DBG(x) {x}*/
  140. /* --------------------------------------------------------------------- */
  141. #ifndef PCI_VENDOR_ID_ENSONIQ
  142. #define PCI_VENDOR_ID_ENSONIQ 0x1274
  143. #endif
  144. #ifndef PCI_VENDOR_ID_ECTIVA
  145. #define PCI_VENDOR_ID_ECTIVA 0x1102
  146. #endif
  147. #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
  148. #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
  149. #endif
  150. #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
  151. #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
  152. #endif
  153. #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
  154. #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
  155. #endif
  156. /* ES1371 chip ID */
  157. /* This is a little confusing because all ES1371 compatible chips have the
  158. same DEVICE_ID, the only thing differentiating them is the REV_ID field.
  159. This is only significant if you want to enable features on the later parts.
  160. Yes, I know it's stupid and why didn't we use the sub IDs?
  161. */
  162. #define ES1371REV_ES1373_A 0x04
  163. #define ES1371REV_ES1373_B 0x06
  164. #define ES1371REV_CT5880_A 0x07
  165. #define CT5880REV_CT5880_C 0x02
  166. #define CT5880REV_CT5880_D 0x03
  167. #define ES1371REV_ES1371_B 0x09
  168. #define EV1938REV_EV1938_A 0x00
  169. #define ES1371REV_ES1373_8 0x08
  170. #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
  171. #define ES1371_EXTENT 0x40
  172. #define JOY_EXTENT 8
  173. #define ES1371_REG_CONTROL 0x00
  174. #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
  175. #define ES1371_REG_UART_DATA 0x08
  176. #define ES1371_REG_UART_STATUS 0x09
  177. #define ES1371_REG_UART_CONTROL 0x09
  178. #define ES1371_REG_UART_TEST 0x0a
  179. #define ES1371_REG_MEMPAGE 0x0c
  180. #define ES1371_REG_SRCONV 0x10
  181. #define ES1371_REG_CODEC 0x14
  182. #define ES1371_REG_LEGACY 0x18
  183. #define ES1371_REG_SERIAL_CONTROL 0x20
  184. #define ES1371_REG_DAC1_SCOUNT 0x24
  185. #define ES1371_REG_DAC2_SCOUNT 0x28
  186. #define ES1371_REG_ADC_SCOUNT 0x2c
  187. #define ES1371_REG_DAC1_FRAMEADR 0xc30
  188. #define ES1371_REG_DAC1_FRAMECNT 0xc34
  189. #define ES1371_REG_DAC2_FRAMEADR 0xc38
  190. #define ES1371_REG_DAC2_FRAMECNT 0xc3c
  191. #define ES1371_REG_ADC_FRAMEADR 0xd30
  192. #define ES1371_REG_ADC_FRAMECNT 0xd34
  193. #define ES1371_FMT_U8_MONO 0
  194. #define ES1371_FMT_U8_STEREO 1
  195. #define ES1371_FMT_S16_MONO 2
  196. #define ES1371_FMT_S16_STEREO 3
  197. #define ES1371_FMT_STEREO 1
  198. #define ES1371_FMT_S16 2
  199. #define ES1371_FMT_MASK 3
  200. static const unsigned sample_size[] = { 1, 2, 2, 4 };
  201. static const unsigned sample_shift[] = { 0, 1, 1, 2 };
  202. #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
  203. #define CTRL_SPDIFEN_B 0x04000000
  204. #define CTRL_JOY_SHIFT 24
  205. #define CTRL_JOY_MASK 3
  206. #define CTRL_JOY_200 0x00000000 /* joystick base address */
  207. #define CTRL_JOY_208 0x01000000
  208. #define CTRL_JOY_210 0x02000000
  209. #define CTRL_JOY_218 0x03000000
  210. #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
  211. #define CTRL_GPIO_IN1 0x00200000
  212. #define CTRL_GPIO_IN2 0x00400000
  213. #define CTRL_GPIO_IN3 0x00800000
  214. #define CTRL_GPIO_OUT0 0x00010000
  215. #define CTRL_GPIO_OUT1 0x00020000
  216. #define CTRL_GPIO_OUT2 0x00040000
  217. #define CTRL_GPIO_OUT3 0x00080000
  218. #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
  219. #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
  220. #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
  221. #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
  222. #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
  223. #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
  224. #define CTRL_PDLEV0 0x00000000 /* power down level */
  225. #define CTRL_PDLEV1 0x00000100
  226. #define CTRL_PDLEV2 0x00000200
  227. #define CTRL_PDLEV3 0x00000300
  228. #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
  229. #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
  230. #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
  231. #define CTRL_ADC_EN 0x00000010 /* enable ADC */
  232. #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
  233. #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
  234. #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
  235. #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
  236. #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
  237. #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
  238. #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
  239. #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
  240. #define STAT_TESTMODE 0x00010000 /* test ASIC */
  241. #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
  242. #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
  243. #define STAT_SH_VC 6
  244. #define STAT_MPWR 0x00000020 /* power level interrupt */
  245. #define STAT_MCCB 0x00000010 /* CCB int pending */
  246. #define STAT_UART 0x00000008 /* UART int pending */
  247. #define STAT_DAC1 0x00000004 /* DAC1 int pending */
  248. #define STAT_DAC2 0x00000002 /* DAC2 int pending */
  249. #define STAT_ADC 0x00000001 /* ADC int pending */
  250. #define USTAT_RXINT 0x80 /* UART rx int pending */
  251. #define USTAT_TXINT 0x04 /* UART tx int pending */
  252. #define USTAT_TXRDY 0x02 /* UART tx ready */
  253. #define USTAT_RXRDY 0x01 /* UART rx ready */
  254. #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
  255. #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
  256. #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
  257. #define UCTRL_CNTRL 0x03 /* control field */
  258. #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
  259. /* sample rate converter */
  260. #define SRC_OKSTATE 1
  261. #define SRC_RAMADDR_MASK 0xfe000000
  262. #define SRC_RAMADDR_SHIFT 25
  263. #define SRC_DAC1FREEZE (1UL << 21)
  264. #define SRC_DAC2FREEZE (1UL << 20)
  265. #define SRC_ADCFREEZE (1UL << 19)
  266. #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
  267. #define SRC_BUSY 0x00800000 /* SRC busy */
  268. #define SRC_DIS 0x00400000 /* 1 = disable SRC */
  269. #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
  270. #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
  271. #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
  272. #define SRC_CTLMASK 0x00780000
  273. #define SRC_RAMDATA_MASK 0x0000ffff
  274. #define SRC_RAMDATA_SHIFT 0
  275. #define SRCREG_ADC 0x78
  276. #define SRCREG_DAC1 0x70
  277. #define SRCREG_DAC2 0x74
  278. #define SRCREG_VOL_ADC 0x6c
  279. #define SRCREG_VOL_DAC1 0x7c
  280. #define SRCREG_VOL_DAC2 0x7e
  281. #define SRCREG_TRUNC_N 0x00
  282. #define SRCREG_INT_REGS 0x01
  283. #define SRCREG_ACCUM_FRAC 0x02
  284. #define SRCREG_VFREQ_FRAC 0x03
  285. #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
  286. #define CODEC_PIADD_MASK 0x007f0000
  287. #define CODEC_PIADD_SHIFT 16
  288. #define CODEC_PIDAT_MASK 0x0000ffff
  289. #define CODEC_PIDAT_SHIFT 0
  290. #define CODEC_RDY 0x80000000 /* AC97 read data valid */
  291. #define CODEC_WIP 0x40000000 /* AC97 write in progress */
  292. #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
  293. #define CODEC_POADD_MASK 0x007f0000
  294. #define CODEC_POADD_SHIFT 16
  295. #define CODEC_PODAT_MASK 0x0000ffff
  296. #define CODEC_PODAT_SHIFT 0
  297. #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
  298. #define LEGACY_FIRQ 0x01000000 /* force IRQ */
  299. #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
  300. #define SCTRL_P2ENDINC 0x00380000 /* */
  301. #define SCTRL_SH_P2ENDINC 19
  302. #define SCTRL_P2STINC 0x00070000 /* */
  303. #define SCTRL_SH_P2STINC 16
  304. #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
  305. #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
  306. #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
  307. #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
  308. #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
  309. #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
  310. #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
  311. #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
  312. #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
  313. #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
  314. #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
  315. #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
  316. #define SCTRL_R1FMT 0x00000030 /* format mask */
  317. #define SCTRL_SH_R1FMT 4
  318. #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
  319. #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
  320. #define SCTRL_P2FMT 0x0000000c /* format mask */
  321. #define SCTRL_SH_P2FMT 2
  322. #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
  323. #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
  324. #define SCTRL_P1FMT 0x00000003 /* format mask */
  325. #define SCTRL_SH_P1FMT 0
  326. /* misc stuff */
  327. #define POLL_COUNT 0x1000
  328. #define FMODE_DAC 4 /* slight misuse of mode_t */
  329. /* MIDI buffer sizes */
  330. #define MIDIINBUF 256
  331. #define MIDIOUTBUF 256
  332. #define FMODE_MIDI_SHIFT 3
  333. #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
  334. #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
  335. #define ES1371_MODULE_NAME "es1371"
  336. #define PFX ES1371_MODULE_NAME ": "
  337. /* --------------------------------------------------------------------- */
  338. struct es1371_state {
  339. /* magic */
  340. unsigned int magic;
  341. /* list of es1371 devices */
  342. struct list_head devs;
  343. /* the corresponding pci_dev structure */
  344. struct pci_dev *dev;
  345. /* soundcore stuff */
  346. int dev_audio;
  347. int dev_dac;
  348. int dev_midi;
  349. /* hardware resources */
  350. unsigned long io; /* long for SPARC */
  351. unsigned int irq;
  352. /* PCI ID's */
  353. u16 vendor;
  354. u16 device;
  355. u8 rev; /* the chip revision */
  356. /* options */
  357. int spdif_volume; /* S/PDIF output is enabled if != -1 */
  358. #ifdef ES1371_DEBUG
  359. /* debug /proc entry */
  360. struct proc_dir_entry *ps;
  361. #endif /* ES1371_DEBUG */
  362. struct ac97_codec *codec;
  363. /* wave stuff */
  364. unsigned ctrl;
  365. unsigned sctrl;
  366. unsigned dac1rate, dac2rate, adcrate;
  367. spinlock_t lock;
  368. struct semaphore open_sem;
  369. mode_t open_mode;
  370. wait_queue_head_t open_wait;
  371. struct dmabuf {
  372. void *rawbuf;
  373. dma_addr_t dmaaddr;
  374. unsigned buforder;
  375. unsigned numfrag;
  376. unsigned fragshift;
  377. unsigned hwptr, swptr;
  378. unsigned total_bytes;
  379. int count;
  380. unsigned error; /* over/underrun */
  381. wait_queue_head_t wait;
  382. /* redundant, but makes calculations easier */
  383. unsigned fragsize;
  384. unsigned dmasize;
  385. unsigned fragsamples;
  386. /* OSS stuff */
  387. unsigned mapped:1;
  388. unsigned ready:1;
  389. unsigned endcleared:1;
  390. unsigned enabled:1;
  391. unsigned ossfragshift;
  392. int ossmaxfrags;
  393. unsigned subdivision;
  394. } dma_dac1, dma_dac2, dma_adc;
  395. /* midi stuff */
  396. struct {
  397. unsigned ird, iwr, icnt;
  398. unsigned ord, owr, ocnt;
  399. wait_queue_head_t iwait;
  400. wait_queue_head_t owait;
  401. unsigned char ibuf[MIDIINBUF];
  402. unsigned char obuf[MIDIOUTBUF];
  403. } midi;
  404. #ifdef SUPPORT_JOYSTICK
  405. struct gameport *gameport;
  406. #endif
  407. struct semaphore sem;
  408. };
  409. /* --------------------------------------------------------------------- */
  410. static LIST_HEAD(devs);
  411. /* --------------------------------------------------------------------- */
  412. static inline unsigned ld2(unsigned int x)
  413. {
  414. unsigned r = 0;
  415. if (x >= 0x10000) {
  416. x >>= 16;
  417. r += 16;
  418. }
  419. if (x >= 0x100) {
  420. x >>= 8;
  421. r += 8;
  422. }
  423. if (x >= 0x10) {
  424. x >>= 4;
  425. r += 4;
  426. }
  427. if (x >= 4) {
  428. x >>= 2;
  429. r += 2;
  430. }
  431. if (x >= 2)
  432. r++;
  433. return r;
  434. }
  435. /* --------------------------------------------------------------------- */
  436. static unsigned wait_src_ready(struct es1371_state *s)
  437. {
  438. unsigned int t, r;
  439. for (t = 0; t < POLL_COUNT; t++) {
  440. if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
  441. return r;
  442. udelay(1);
  443. }
  444. printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
  445. return r;
  446. }
  447. static unsigned src_read(struct es1371_state *s, unsigned reg)
  448. {
  449. unsigned int temp,i,orig;
  450. /* wait for ready */
  451. temp = wait_src_ready (s);
  452. /* we can only access the SRC at certain times, make sure
  453. we're allowed to before we read */
  454. orig = temp;
  455. /* expose the SRC state bits */
  456. outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
  457. s->io + ES1371_REG_SRCONV);
  458. /* now, wait for busy and the correct time to read */
  459. temp = wait_src_ready (s);
  460. if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
  461. /* wait for the right state */
  462. for (i=0; i<POLL_COUNT; i++){
  463. temp = inl (s->io + ES1371_REG_SRCONV);
  464. if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
  465. break;
  466. }
  467. }
  468. /* hide the state bits */
  469. outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
  470. return temp;
  471. }
  472. static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
  473. {
  474. unsigned int r;
  475. r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
  476. r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
  477. r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
  478. outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
  479. }
  480. /* --------------------------------------------------------------------- */
  481. /* most of the following here is black magic */
  482. static void set_adc_rate(struct es1371_state *s, unsigned rate)
  483. {
  484. unsigned long flags;
  485. unsigned int n, truncm, freq;
  486. if (rate > 48000)
  487. rate = 48000;
  488. if (rate < 4000)
  489. rate = 4000;
  490. n = rate / 3000;
  491. if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
  492. n--;
  493. truncm = (21 * n - 1) | 1;
  494. freq = ((48000UL << 15) / rate) * n;
  495. s->adcrate = (48000UL << 15) / (freq / n);
  496. spin_lock_irqsave(&s->lock, flags);
  497. if (rate >= 24000) {
  498. if (truncm > 239)
  499. truncm = 239;
  500. src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
  501. (((239 - truncm) >> 1) << 9) | (n << 4));
  502. } else {
  503. if (truncm > 119)
  504. truncm = 119;
  505. src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
  506. 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
  507. }
  508. src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
  509. (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
  510. ((freq >> 5) & 0xfc00));
  511. src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
  512. src_write(s, SRCREG_VOL_ADC, n << 8);
  513. src_write(s, SRCREG_VOL_ADC+1, n << 8);
  514. spin_unlock_irqrestore(&s->lock, flags);
  515. }
  516. static void set_dac1_rate(struct es1371_state *s, unsigned rate)
  517. {
  518. unsigned long flags;
  519. unsigned int freq, r;
  520. if (rate > 48000)
  521. rate = 48000;
  522. if (rate < 4000)
  523. rate = 4000;
  524. freq = ((rate << 15) + 1500) / 3000;
  525. s->dac1rate = (freq * 3000 + 16384) >> 15;
  526. spin_lock_irqsave(&s->lock, flags);
  527. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
  528. outl(r, s->io + ES1371_REG_SRCONV);
  529. src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
  530. (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
  531. ((freq >> 5) & 0xfc00));
  532. src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
  533. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
  534. outl(r, s->io + ES1371_REG_SRCONV);
  535. spin_unlock_irqrestore(&s->lock, flags);
  536. }
  537. static void set_dac2_rate(struct es1371_state *s, unsigned rate)
  538. {
  539. unsigned long flags;
  540. unsigned int freq, r;
  541. if (rate > 48000)
  542. rate = 48000;
  543. if (rate < 4000)
  544. rate = 4000;
  545. freq = ((rate << 15) + 1500) / 3000;
  546. s->dac2rate = (freq * 3000 + 16384) >> 15;
  547. spin_lock_irqsave(&s->lock, flags);
  548. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
  549. outl(r, s->io + ES1371_REG_SRCONV);
  550. src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
  551. (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
  552. ((freq >> 5) & 0xfc00));
  553. src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
  554. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
  555. outl(r, s->io + ES1371_REG_SRCONV);
  556. spin_unlock_irqrestore(&s->lock, flags);
  557. }
  558. /* --------------------------------------------------------------------- */
  559. static void __devinit src_init(struct es1371_state *s)
  560. {
  561. unsigned int i;
  562. /* before we enable or disable the SRC we need
  563. to wait for it to become ready */
  564. wait_src_ready(s);
  565. outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
  566. for (i = 0; i < 0x80; i++)
  567. src_write(s, i, 0);
  568. src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
  569. src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
  570. src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
  571. src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
  572. src_write(s, SRCREG_VOL_ADC, 1 << 12);
  573. src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
  574. src_write(s, SRCREG_VOL_DAC1, 1 << 12);
  575. src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
  576. src_write(s, SRCREG_VOL_DAC2, 1 << 12);
  577. src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
  578. set_adc_rate(s, 22050);
  579. set_dac1_rate(s, 22050);
  580. set_dac2_rate(s, 22050);
  581. /* WARNING:
  582. * enabling the sample rate converter without properly programming
  583. * its parameters causes the chip to lock up (the SRC busy bit will
  584. * be stuck high, and I've found no way to rectify this other than
  585. * power cycle)
  586. */
  587. wait_src_ready(s);
  588. outl(0, s->io+ES1371_REG_SRCONV);
  589. }
  590. /* --------------------------------------------------------------------- */
  591. static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  592. {
  593. struct es1371_state *s = (struct es1371_state *)codec->private_data;
  594. unsigned long flags;
  595. unsigned t, x;
  596. spin_lock_irqsave(&s->lock, flags);
  597. for (t = 0; t < POLL_COUNT; t++)
  598. if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
  599. break;
  600. /* save the current state for later */
  601. x = wait_src_ready(s);
  602. /* enable SRC state data in SRC mux */
  603. outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
  604. s->io+ES1371_REG_SRCONV);
  605. /* wait for not busy (state 0) first to avoid
  606. transition states */
  607. for (t=0; t<POLL_COUNT; t++){
  608. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
  609. break;
  610. udelay(1);
  611. }
  612. /* wait for a SAFE time to write addr/data and then do it, dammit */
  613. for (t=0; t<POLL_COUNT; t++){
  614. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
  615. break;
  616. udelay(1);
  617. }
  618. outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
  619. ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
  620. /* restore SRC reg */
  621. wait_src_ready(s);
  622. outl(x, s->io+ES1371_REG_SRCONV);
  623. spin_unlock_irqrestore(&s->lock, flags);
  624. }
  625. static u16 rdcodec(struct ac97_codec *codec, u8 addr)
  626. {
  627. struct es1371_state *s = (struct es1371_state *)codec->private_data;
  628. unsigned long flags;
  629. unsigned t, x;
  630. spin_lock_irqsave(&s->lock, flags);
  631. /* wait for WIP to go away */
  632. for (t = 0; t < 0x1000; t++)
  633. if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
  634. break;
  635. /* save the current state for later */
  636. x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
  637. /* enable SRC state data in SRC mux */
  638. outl( x | 0x00010000,
  639. s->io+ES1371_REG_SRCONV);
  640. /* wait for not busy (state 0) first to avoid
  641. transition states */
  642. for (t=0; t<POLL_COUNT; t++){
  643. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
  644. break;
  645. udelay(1);
  646. }
  647. /* wait for a SAFE time to write addr/data and then do it, dammit */
  648. for (t=0; t<POLL_COUNT; t++){
  649. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
  650. break;
  651. udelay(1);
  652. }
  653. outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
  654. /* restore SRC reg */
  655. wait_src_ready(s);
  656. outl(x, s->io+ES1371_REG_SRCONV);
  657. /* wait for WIP again */
  658. for (t = 0; t < 0x1000; t++)
  659. if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
  660. break;
  661. /* now wait for the stinkin' data (RDY) */
  662. for (t = 0; t < POLL_COUNT; t++)
  663. if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
  664. break;
  665. spin_unlock_irqrestore(&s->lock, flags);
  666. return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
  667. }
  668. /* --------------------------------------------------------------------- */
  669. static inline void stop_adc(struct es1371_state *s)
  670. {
  671. unsigned long flags;
  672. spin_lock_irqsave(&s->lock, flags);
  673. s->ctrl &= ~CTRL_ADC_EN;
  674. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  675. spin_unlock_irqrestore(&s->lock, flags);
  676. }
  677. static inline void stop_dac1(struct es1371_state *s)
  678. {
  679. unsigned long flags;
  680. spin_lock_irqsave(&s->lock, flags);
  681. s->ctrl &= ~CTRL_DAC1_EN;
  682. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  683. spin_unlock_irqrestore(&s->lock, flags);
  684. }
  685. static inline void stop_dac2(struct es1371_state *s)
  686. {
  687. unsigned long flags;
  688. spin_lock_irqsave(&s->lock, flags);
  689. s->ctrl &= ~CTRL_DAC2_EN;
  690. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  691. spin_unlock_irqrestore(&s->lock, flags);
  692. }
  693. static void start_dac1(struct es1371_state *s)
  694. {
  695. unsigned long flags;
  696. unsigned fragremain, fshift;
  697. spin_lock_irqsave(&s->lock, flags);
  698. if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
  699. && s->dma_dac1.ready) {
  700. s->ctrl |= CTRL_DAC1_EN;
  701. s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
  702. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  703. fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
  704. fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
  705. if (fragremain < 2*fshift)
  706. fragremain = s->dma_dac1.fragsize;
  707. outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
  708. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  709. outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
  710. }
  711. spin_unlock_irqrestore(&s->lock, flags);
  712. }
  713. static void start_dac2(struct es1371_state *s)
  714. {
  715. unsigned long flags;
  716. unsigned fragremain, fshift;
  717. spin_lock_irqsave(&s->lock, flags);
  718. if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
  719. && s->dma_dac2.ready) {
  720. s->ctrl |= CTRL_DAC2_EN;
  721. s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
  722. SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
  723. (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
  724. (0 << SCTRL_SH_P2STINC);
  725. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  726. fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
  727. fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
  728. if (fragremain < 2*fshift)
  729. fragremain = s->dma_dac2.fragsize;
  730. outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
  731. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  732. outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
  733. }
  734. spin_unlock_irqrestore(&s->lock, flags);
  735. }
  736. static void start_adc(struct es1371_state *s)
  737. {
  738. unsigned long flags;
  739. unsigned fragremain, fshift;
  740. spin_lock_irqsave(&s->lock, flags);
  741. if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
  742. && s->dma_adc.ready) {
  743. s->ctrl |= CTRL_ADC_EN;
  744. s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
  745. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  746. fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
  747. fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
  748. if (fragremain < 2*fshift)
  749. fragremain = s->dma_adc.fragsize;
  750. outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
  751. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  752. outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
  753. }
  754. spin_unlock_irqrestore(&s->lock, flags);
  755. }
  756. /* --------------------------------------------------------------------- */
  757. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  758. #define DMABUF_MINORDER 1
  759. static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
  760. {
  761. struct page *page, *pend;
  762. if (db->rawbuf) {
  763. /* undo marking the pages as reserved */
  764. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  765. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  766. ClearPageReserved(page);
  767. pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
  768. }
  769. db->rawbuf = NULL;
  770. db->mapped = db->ready = 0;
  771. }
  772. static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
  773. {
  774. int order;
  775. unsigned bytepersec;
  776. unsigned bufs;
  777. struct page *page, *pend;
  778. db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
  779. if (!db->rawbuf) {
  780. db->ready = db->mapped = 0;
  781. for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
  782. if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
  783. break;
  784. if (!db->rawbuf)
  785. return -ENOMEM;
  786. db->buforder = order;
  787. /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
  788. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  789. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  790. SetPageReserved(page);
  791. }
  792. fmt &= ES1371_FMT_MASK;
  793. bytepersec = rate << sample_shift[fmt];
  794. bufs = PAGE_SIZE << db->buforder;
  795. if (db->ossfragshift) {
  796. if ((1000 << db->ossfragshift) < bytepersec)
  797. db->fragshift = ld2(bytepersec/1000);
  798. else
  799. db->fragshift = db->ossfragshift;
  800. } else {
  801. db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
  802. if (db->fragshift < 3)
  803. db->fragshift = 3;
  804. }
  805. db->numfrag = bufs >> db->fragshift;
  806. while (db->numfrag < 4 && db->fragshift > 3) {
  807. db->fragshift--;
  808. db->numfrag = bufs >> db->fragshift;
  809. }
  810. db->fragsize = 1 << db->fragshift;
  811. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  812. db->numfrag = db->ossmaxfrags;
  813. db->fragsamples = db->fragsize >> sample_shift[fmt];
  814. db->dmasize = db->numfrag << db->fragshift;
  815. memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
  816. outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
  817. outl(db->dmaaddr, s->io+(reg & 0xff));
  818. outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
  819. db->enabled = 1;
  820. db->ready = 1;
  821. return 0;
  822. }
  823. static inline int prog_dmabuf_adc(struct es1371_state *s)
  824. {
  825. stop_adc(s);
  826. return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
  827. ES1371_REG_ADC_FRAMEADR);
  828. }
  829. static inline int prog_dmabuf_dac2(struct es1371_state *s)
  830. {
  831. stop_dac2(s);
  832. return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
  833. ES1371_REG_DAC2_FRAMEADR);
  834. }
  835. static inline int prog_dmabuf_dac1(struct es1371_state *s)
  836. {
  837. stop_dac1(s);
  838. return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
  839. ES1371_REG_DAC1_FRAMEADR);
  840. }
  841. static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
  842. {
  843. unsigned hwptr, diff;
  844. outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
  845. hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
  846. diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
  847. db->hwptr = hwptr;
  848. return diff;
  849. }
  850. static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
  851. {
  852. if (bptr + len > bsize) {
  853. unsigned x = bsize - bptr;
  854. memset(((char *)buf) + bptr, c, x);
  855. bptr = 0;
  856. len -= x;
  857. }
  858. memset(((char *)buf) + bptr, c, len);
  859. }
  860. /* call with spinlock held! */
  861. static void es1371_update_ptr(struct es1371_state *s)
  862. {
  863. int diff;
  864. /* update ADC pointer */
  865. if (s->ctrl & CTRL_ADC_EN) {
  866. diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
  867. s->dma_adc.total_bytes += diff;
  868. s->dma_adc.count += diff;
  869. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  870. wake_up(&s->dma_adc.wait);
  871. if (!s->dma_adc.mapped) {
  872. if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
  873. s->ctrl &= ~CTRL_ADC_EN;
  874. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  875. s->dma_adc.error++;
  876. }
  877. }
  878. }
  879. /* update DAC1 pointer */
  880. if (s->ctrl & CTRL_DAC1_EN) {
  881. diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
  882. s->dma_dac1.total_bytes += diff;
  883. if (s->dma_dac1.mapped) {
  884. s->dma_dac1.count += diff;
  885. if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
  886. wake_up(&s->dma_dac1.wait);
  887. } else {
  888. s->dma_dac1.count -= diff;
  889. if (s->dma_dac1.count <= 0) {
  890. s->ctrl &= ~CTRL_DAC1_EN;
  891. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  892. s->dma_dac1.error++;
  893. } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
  894. clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
  895. s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
  896. s->dma_dac1.endcleared = 1;
  897. }
  898. if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
  899. wake_up(&s->dma_dac1.wait);
  900. }
  901. }
  902. /* update DAC2 pointer */
  903. if (s->ctrl & CTRL_DAC2_EN) {
  904. diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
  905. s->dma_dac2.total_bytes += diff;
  906. if (s->dma_dac2.mapped) {
  907. s->dma_dac2.count += diff;
  908. if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
  909. wake_up(&s->dma_dac2.wait);
  910. } else {
  911. s->dma_dac2.count -= diff;
  912. if (s->dma_dac2.count <= 0) {
  913. s->ctrl &= ~CTRL_DAC2_EN;
  914. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  915. s->dma_dac2.error++;
  916. } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
  917. clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
  918. s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
  919. s->dma_dac2.endcleared = 1;
  920. }
  921. if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
  922. wake_up(&s->dma_dac2.wait);
  923. }
  924. }
  925. }
  926. /* hold spinlock for the following! */
  927. static void es1371_handle_midi(struct es1371_state *s)
  928. {
  929. unsigned char ch;
  930. int wake;
  931. if (!(s->ctrl & CTRL_UART_EN))
  932. return;
  933. wake = 0;
  934. while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
  935. ch = inb(s->io+ES1371_REG_UART_DATA);
  936. if (s->midi.icnt < MIDIINBUF) {
  937. s->midi.ibuf[s->midi.iwr] = ch;
  938. s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
  939. s->midi.icnt++;
  940. }
  941. wake = 1;
  942. }
  943. if (wake)
  944. wake_up(&s->midi.iwait);
  945. wake = 0;
  946. while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
  947. outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
  948. s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
  949. s->midi.ocnt--;
  950. if (s->midi.ocnt < MIDIOUTBUF-16)
  951. wake = 1;
  952. }
  953. if (wake)
  954. wake_up(&s->midi.owait);
  955. outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
  956. }
  957. static irqreturn_t es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  958. {
  959. struct es1371_state *s = (struct es1371_state *)dev_id;
  960. unsigned int intsrc, sctl;
  961. /* fastpath out, to ease interrupt sharing */
  962. intsrc = inl(s->io+ES1371_REG_STATUS);
  963. if (!(intsrc & 0x80000000))
  964. return IRQ_NONE;
  965. spin_lock(&s->lock);
  966. /* clear audio interrupts first */
  967. sctl = s->sctrl;
  968. if (intsrc & STAT_ADC)
  969. sctl &= ~SCTRL_R1INTEN;
  970. if (intsrc & STAT_DAC1)
  971. sctl &= ~SCTRL_P1INTEN;
  972. if (intsrc & STAT_DAC2)
  973. sctl &= ~SCTRL_P2INTEN;
  974. outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
  975. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  976. es1371_update_ptr(s);
  977. es1371_handle_midi(s);
  978. spin_unlock(&s->lock);
  979. return IRQ_HANDLED;
  980. }
  981. /* --------------------------------------------------------------------- */
  982. static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
  983. #define VALIDATE_STATE(s) \
  984. ({ \
  985. if (!(s) || (s)->magic != ES1371_MAGIC) { \
  986. printk(invalid_magic); \
  987. return -ENXIO; \
  988. } \
  989. })
  990. /* --------------------------------------------------------------------- */
  991. /* Conversion table for S/PDIF PCM volume emulation through the SRC */
  992. /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
  993. static const unsigned short DACVolTable[101] =
  994. {
  995. 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
  996. 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
  997. 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
  998. 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
  999. 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
  1000. 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
  1001. 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
  1002. 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
  1003. 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
  1004. 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
  1005. 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
  1006. 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
  1007. 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
  1008. };
  1009. /*
  1010. * when we are in S/PDIF mode, we want to disable any analog output so
  1011. * we filter the mixer ioctls
  1012. */
  1013. static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
  1014. {
  1015. struct es1371_state *s = (struct es1371_state *)codec->private_data;
  1016. int val;
  1017. unsigned long flags;
  1018. unsigned int left, right;
  1019. VALIDATE_STATE(s);
  1020. /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
  1021. if (s->spdif_volume == -1)
  1022. return codec->mixer_ioctl(codec, cmd, arg);
  1023. switch (cmd) {
  1024. case SOUND_MIXER_WRITE_VOLUME:
  1025. return 0;
  1026. case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
  1027. if (get_user(val, (int __user *)arg))
  1028. return -EFAULT;
  1029. right = ((val >> 8) & 0xff);
  1030. left = (val & 0xff);
  1031. if (right > 100)
  1032. right = 100;
  1033. if (left > 100)
  1034. left = 100;
  1035. s->spdif_volume = (right << 8) | left;
  1036. spin_lock_irqsave(&s->lock, flags);
  1037. src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
  1038. src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
  1039. spin_unlock_irqrestore(&s->lock, flags);
  1040. return 0;
  1041. case SOUND_MIXER_READ_PCM:
  1042. return put_user(s->spdif_volume, (int __user *)arg);
  1043. }
  1044. return codec->mixer_ioctl(codec, cmd, arg);
  1045. }
  1046. /* --------------------------------------------------------------------- */
  1047. /*
  1048. * AC97 Mixer Register to Connections mapping of the Concert 97 board
  1049. *
  1050. * AC97_MASTER_VOL_STEREO Line Out
  1051. * AC97_MASTER_VOL_MONO TAD Output
  1052. * AC97_PCBEEP_VOL none
  1053. * AC97_PHONE_VOL TAD Input (mono)
  1054. * AC97_MIC_VOL MIC Input (mono)
  1055. * AC97_LINEIN_VOL Line Input (stereo)
  1056. * AC97_CD_VOL CD Input (stereo)
  1057. * AC97_VIDEO_VOL none
  1058. * AC97_AUX_VOL Aux Input (stereo)
  1059. * AC97_PCMOUT_VOL Wave Output (stereo)
  1060. */
  1061. static int es1371_open_mixdev(struct inode *inode, struct file *file)
  1062. {
  1063. int minor = iminor(inode);
  1064. struct list_head *list;
  1065. struct es1371_state *s;
  1066. for (list = devs.next; ; list = list->next) {
  1067. if (list == &devs)
  1068. return -ENODEV;
  1069. s = list_entry(list, struct es1371_state, devs);
  1070. if (s->codec->dev_mixer == minor)
  1071. break;
  1072. }
  1073. VALIDATE_STATE(s);
  1074. file->private_data = s;
  1075. return nonseekable_open(inode, file);
  1076. }
  1077. static int es1371_release_mixdev(struct inode *inode, struct file *file)
  1078. {
  1079. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1080. VALIDATE_STATE(s);
  1081. return 0;
  1082. }
  1083. static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1084. {
  1085. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1086. struct ac97_codec *codec = s->codec;
  1087. return mixdev_ioctl(codec, cmd, arg);
  1088. }
  1089. static /*const*/ struct file_operations es1371_mixer_fops = {
  1090. .owner = THIS_MODULE,
  1091. .llseek = no_llseek,
  1092. .ioctl = es1371_ioctl_mixdev,
  1093. .open = es1371_open_mixdev,
  1094. .release = es1371_release_mixdev,
  1095. };
  1096. /* --------------------------------------------------------------------- */
  1097. static int drain_dac1(struct es1371_state *s, int nonblock)
  1098. {
  1099. DECLARE_WAITQUEUE(wait, current);
  1100. unsigned long flags;
  1101. int count, tmo;
  1102. if (s->dma_dac1.mapped || !s->dma_dac1.ready)
  1103. return 0;
  1104. add_wait_queue(&s->dma_dac1.wait, &wait);
  1105. for (;;) {
  1106. __set_current_state(TASK_INTERRUPTIBLE);
  1107. spin_lock_irqsave(&s->lock, flags);
  1108. count = s->dma_dac1.count;
  1109. spin_unlock_irqrestore(&s->lock, flags);
  1110. if (count <= 0)
  1111. break;
  1112. if (signal_pending(current))
  1113. break;
  1114. if (nonblock) {
  1115. remove_wait_queue(&s->dma_dac1.wait, &wait);
  1116. set_current_state(TASK_RUNNING);
  1117. return -EBUSY;
  1118. }
  1119. tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
  1120. tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
  1121. if (!schedule_timeout(tmo + 1))
  1122. DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
  1123. }
  1124. remove_wait_queue(&s->dma_dac1.wait, &wait);
  1125. set_current_state(TASK_RUNNING);
  1126. if (signal_pending(current))
  1127. return -ERESTARTSYS;
  1128. return 0;
  1129. }
  1130. static int drain_dac2(struct es1371_state *s, int nonblock)
  1131. {
  1132. DECLARE_WAITQUEUE(wait, current);
  1133. unsigned long flags;
  1134. int count, tmo;
  1135. if (s->dma_dac2.mapped || !s->dma_dac2.ready)
  1136. return 0;
  1137. add_wait_queue(&s->dma_dac2.wait, &wait);
  1138. for (;;) {
  1139. __set_current_state(TASK_UNINTERRUPTIBLE);
  1140. spin_lock_irqsave(&s->lock, flags);
  1141. count = s->dma_dac2.count;
  1142. spin_unlock_irqrestore(&s->lock, flags);
  1143. if (count <= 0)
  1144. break;
  1145. if (signal_pending(current))
  1146. break;
  1147. if (nonblock) {
  1148. remove_wait_queue(&s->dma_dac2.wait, &wait);
  1149. set_current_state(TASK_RUNNING);
  1150. return -EBUSY;
  1151. }
  1152. tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
  1153. tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
  1154. if (!schedule_timeout(tmo + 1))
  1155. DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
  1156. }
  1157. remove_wait_queue(&s->dma_dac2.wait, &wait);
  1158. set_current_state(TASK_RUNNING);
  1159. if (signal_pending(current))
  1160. return -ERESTARTSYS;
  1161. return 0;
  1162. }
  1163. /* --------------------------------------------------------------------- */
  1164. static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1165. {
  1166. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1167. DECLARE_WAITQUEUE(wait, current);
  1168. ssize_t ret = 0;
  1169. unsigned long flags;
  1170. unsigned swptr;
  1171. int cnt;
  1172. VALIDATE_STATE(s);
  1173. if (s->dma_adc.mapped)
  1174. return -ENXIO;
  1175. if (!access_ok(VERIFY_WRITE, buffer, count))
  1176. return -EFAULT;
  1177. down(&s->sem);
  1178. if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
  1179. goto out2;
  1180. add_wait_queue(&s->dma_adc.wait, &wait);
  1181. while (count > 0) {
  1182. spin_lock_irqsave(&s->lock, flags);
  1183. swptr = s->dma_adc.swptr;
  1184. cnt = s->dma_adc.dmasize-swptr;
  1185. if (s->dma_adc.count < cnt)
  1186. cnt = s->dma_adc.count;
  1187. if (cnt <= 0)
  1188. __set_current_state(TASK_INTERRUPTIBLE);
  1189. spin_unlock_irqrestore(&s->lock, flags);
  1190. if (cnt > count)
  1191. cnt = count;
  1192. if (cnt <= 0) {
  1193. if (s->dma_adc.enabled)
  1194. start_adc(s);
  1195. if (file->f_flags & O_NONBLOCK) {
  1196. if (!ret)
  1197. ret = -EAGAIN;
  1198. goto out;
  1199. }
  1200. up(&s->sem);
  1201. schedule();
  1202. if (signal_pending(current)) {
  1203. if (!ret)
  1204. ret = -ERESTARTSYS;
  1205. goto out2;
  1206. }
  1207. down(&s->sem);
  1208. if (s->dma_adc.mapped)
  1209. {
  1210. ret = -ENXIO;
  1211. goto out;
  1212. }
  1213. continue;
  1214. }
  1215. if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
  1216. if (!ret)
  1217. ret = -EFAULT;
  1218. goto out;
  1219. }
  1220. swptr = (swptr + cnt) % s->dma_adc.dmasize;
  1221. spin_lock_irqsave(&s->lock, flags);
  1222. s->dma_adc.swptr = swptr;
  1223. s->dma_adc.count -= cnt;
  1224. spin_unlock_irqrestore(&s->lock, flags);
  1225. count -= cnt;
  1226. buffer += cnt;
  1227. ret += cnt;
  1228. if (s->dma_adc.enabled)
  1229. start_adc(s);
  1230. }
  1231. out:
  1232. up(&s->sem);
  1233. out2:
  1234. remove_wait_queue(&s->dma_adc.wait, &wait);
  1235. set_current_state(TASK_RUNNING);
  1236. return ret;
  1237. }
  1238. static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1239. {
  1240. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1241. DECLARE_WAITQUEUE(wait, current);
  1242. ssize_t ret;
  1243. unsigned long flags;
  1244. unsigned swptr;
  1245. int cnt;
  1246. VALIDATE_STATE(s);
  1247. if (s->dma_dac2.mapped)
  1248. return -ENXIO;
  1249. if (!access_ok(VERIFY_READ, buffer, count))
  1250. return -EFAULT;
  1251. down(&s->sem);
  1252. if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
  1253. goto out3;
  1254. ret = 0;
  1255. add_wait_queue(&s->dma_dac2.wait, &wait);
  1256. while (count > 0) {
  1257. spin_lock_irqsave(&s->lock, flags);
  1258. if (s->dma_dac2.count < 0) {
  1259. s->dma_dac2.count = 0;
  1260. s->dma_dac2.swptr = s->dma_dac2.hwptr;
  1261. }
  1262. swptr = s->dma_dac2.swptr;
  1263. cnt = s->dma_dac2.dmasize-swptr;
  1264. if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
  1265. cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
  1266. if (cnt <= 0)
  1267. __set_current_state(TASK_INTERRUPTIBLE);
  1268. spin_unlock_irqrestore(&s->lock, flags);
  1269. if (cnt > count)
  1270. cnt = count;
  1271. if (cnt <= 0) {
  1272. if (s->dma_dac2.enabled)
  1273. start_dac2(s);
  1274. if (file->f_flags & O_NONBLOCK) {
  1275. if (!ret)
  1276. ret = -EAGAIN;
  1277. goto out;
  1278. }
  1279. up(&s->sem);
  1280. schedule();
  1281. if (signal_pending(current)) {
  1282. if (!ret)
  1283. ret = -ERESTARTSYS;
  1284. goto out2;
  1285. }
  1286. down(&s->sem);
  1287. if (s->dma_dac2.mapped)
  1288. {
  1289. ret = -ENXIO;
  1290. goto out;
  1291. }
  1292. continue;
  1293. }
  1294. if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
  1295. if (!ret)
  1296. ret = -EFAULT;
  1297. goto out;
  1298. }
  1299. swptr = (swptr + cnt) % s->dma_dac2.dmasize;
  1300. spin_lock_irqsave(&s->lock, flags);
  1301. s->dma_dac2.swptr = swptr;
  1302. s->dma_dac2.count += cnt;
  1303. s->dma_dac2.endcleared = 0;
  1304. spin_unlock_irqrestore(&s->lock, flags);
  1305. count -= cnt;
  1306. buffer += cnt;
  1307. ret += cnt;
  1308. if (s->dma_dac2.enabled)
  1309. start_dac2(s);
  1310. }
  1311. out:
  1312. up(&s->sem);
  1313. out2:
  1314. remove_wait_queue(&s->dma_dac2.wait, &wait);
  1315. out3:
  1316. set_current_state(TASK_RUNNING);
  1317. return ret;
  1318. }
  1319. /* No kernel lock - we have our own spinlock */
  1320. static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
  1321. {
  1322. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1323. unsigned long flags;
  1324. unsigned int mask = 0;
  1325. VALIDATE_STATE(s);
  1326. if (file->f_mode & FMODE_WRITE) {
  1327. if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
  1328. return 0;
  1329. poll_wait(file, &s->dma_dac2.wait, wait);
  1330. }
  1331. if (file->f_mode & FMODE_READ) {
  1332. if (!s->dma_adc.ready && prog_dmabuf_adc(s))
  1333. return 0;
  1334. poll_wait(file, &s->dma_adc.wait, wait);
  1335. }
  1336. spin_lock_irqsave(&s->lock, flags);
  1337. es1371_update_ptr(s);
  1338. if (file->f_mode & FMODE_READ) {
  1339. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  1340. mask |= POLLIN | POLLRDNORM;
  1341. }
  1342. if (file->f_mode & FMODE_WRITE) {
  1343. if (s->dma_dac2.mapped) {
  1344. if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
  1345. mask |= POLLOUT | POLLWRNORM;
  1346. } else {
  1347. if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
  1348. mask |= POLLOUT | POLLWRNORM;
  1349. }
  1350. }
  1351. spin_unlock_irqrestore(&s->lock, flags);
  1352. return mask;
  1353. }
  1354. static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
  1355. {
  1356. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1357. struct dmabuf *db;
  1358. int ret = 0;
  1359. unsigned long size;
  1360. VALIDATE_STATE(s);
  1361. lock_kernel();
  1362. down(&s->sem);
  1363. if (vma->vm_flags & VM_WRITE) {
  1364. if ((ret = prog_dmabuf_dac2(s)) != 0) {
  1365. goto out;
  1366. }
  1367. db = &s->dma_dac2;
  1368. } else if (vma->vm_flags & VM_READ) {
  1369. if ((ret = prog_dmabuf_adc(s)) != 0) {
  1370. goto out;
  1371. }
  1372. db = &s->dma_adc;
  1373. } else {
  1374. ret = -EINVAL;
  1375. goto out;
  1376. }
  1377. if (vma->vm_pgoff != 0) {
  1378. ret = -EINVAL;
  1379. goto out;
  1380. }
  1381. size = vma->vm_end - vma->vm_start;
  1382. if (size > (PAGE_SIZE << db->buforder)) {
  1383. ret = -EINVAL;
  1384. goto out;
  1385. }
  1386. if (remap_pfn_range(vma, vma->vm_start,
  1387. virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
  1388. size, vma->vm_page_prot)) {
  1389. ret = -EAGAIN;
  1390. goto out;
  1391. }
  1392. db->mapped = 1;
  1393. out:
  1394. up(&s->sem);
  1395. unlock_kernel();
  1396. return ret;
  1397. }
  1398. static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1399. {
  1400. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1401. unsigned long flags;
  1402. audio_buf_info abinfo;
  1403. count_info cinfo;
  1404. int count;
  1405. int val, mapped, ret;
  1406. void __user *argp = (void __user *)arg;
  1407. int __user *p = argp;
  1408. VALIDATE_STATE(s);
  1409. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
  1410. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1411. switch (cmd) {
  1412. case OSS_GETVERSION:
  1413. return put_user(SOUND_VERSION, p);
  1414. case SNDCTL_DSP_SYNC:
  1415. if (file->f_mode & FMODE_WRITE)
  1416. return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
  1417. return 0;
  1418. case SNDCTL_DSP_SETDUPLEX:
  1419. return 0;
  1420. case SNDCTL_DSP_GETCAPS:
  1421. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1422. case SNDCTL_DSP_RESET:
  1423. if (file->f_mode & FMODE_WRITE) {
  1424. stop_dac2(s);
  1425. synchronize_irq(s->irq);
  1426. s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
  1427. }
  1428. if (file->f_mode & FMODE_READ) {
  1429. stop_adc(s);
  1430. synchronize_irq(s->irq);
  1431. s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1432. }
  1433. return 0;
  1434. case SNDCTL_DSP_SPEED:
  1435. if (get_user(val, p))
  1436. return -EFAULT;
  1437. if (val >= 0) {
  1438. if (file->f_mode & FMODE_READ) {
  1439. stop_adc(s);
  1440. s->dma_adc.ready = 0;
  1441. set_adc_rate(s, val);
  1442. }
  1443. if (file->f_mode & FMODE_WRITE) {
  1444. stop_dac2(s);
  1445. s->dma_dac2.ready = 0;
  1446. set_dac2_rate(s, val);
  1447. }
  1448. }
  1449. return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
  1450. case SNDCTL_DSP_STEREO:
  1451. if (get_user(val, p))
  1452. return -EFAULT;
  1453. if (file->f_mode & FMODE_READ) {
  1454. stop_adc(s);
  1455. s->dma_adc.ready = 0;
  1456. spin_lock_irqsave(&s->lock, flags);
  1457. if (val)
  1458. s->sctrl |= SCTRL_R1SMB;
  1459. else
  1460. s->sctrl &= ~SCTRL_R1SMB;
  1461. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1462. spin_unlock_irqrestore(&s->lock, flags);
  1463. }
  1464. if (file->f_mode & FMODE_WRITE) {
  1465. stop_dac2(s);
  1466. s->dma_dac2.ready = 0;
  1467. spin_lock_irqsave(&s->lock, flags);
  1468. if (val)
  1469. s->sctrl |= SCTRL_P2SMB;
  1470. else
  1471. s->sctrl &= ~SCTRL_P2SMB;
  1472. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1473. spin_unlock_irqrestore(&s->lock, flags);
  1474. }
  1475. return 0;
  1476. case SNDCTL_DSP_CHANNELS:
  1477. if (get_user(val, p))
  1478. return -EFAULT;
  1479. if (val != 0) {
  1480. if (file->f_mode & FMODE_READ) {
  1481. stop_adc(s);
  1482. s->dma_adc.ready = 0;
  1483. spin_lock_irqsave(&s->lock, flags);
  1484. if (val >= 2)
  1485. s->sctrl |= SCTRL_R1SMB;
  1486. else
  1487. s->sctrl &= ~SCTRL_R1SMB;
  1488. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1489. spin_unlock_irqrestore(&s->lock, flags);
  1490. }
  1491. if (file->f_mode & FMODE_WRITE) {
  1492. stop_dac2(s);
  1493. s->dma_dac2.ready = 0;
  1494. spin_lock_irqsave(&s->lock, flags);
  1495. if (val >= 2)
  1496. s->sctrl |= SCTRL_P2SMB;
  1497. else
  1498. s->sctrl &= ~SCTRL_P2SMB;
  1499. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1500. spin_unlock_irqrestore(&s->lock, flags);
  1501. }
  1502. }
  1503. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
  1504. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1505. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1506. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1507. if (get_user(val, p))
  1508. return -EFAULT;
  1509. if (val != AFMT_QUERY) {
  1510. if (file->f_mode & FMODE_READ) {
  1511. stop_adc(s);
  1512. s->dma_adc.ready = 0;
  1513. spin_lock_irqsave(&s->lock, flags);
  1514. if (val == AFMT_S16_LE)
  1515. s->sctrl |= SCTRL_R1SEB;
  1516. else
  1517. s->sctrl &= ~SCTRL_R1SEB;
  1518. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1519. spin_unlock_irqrestore(&s->lock, flags);
  1520. }
  1521. if (file->f_mode & FMODE_WRITE) {
  1522. stop_dac2(s);
  1523. s->dma_dac2.ready = 0;
  1524. spin_lock_irqsave(&s->lock, flags);
  1525. if (val == AFMT_S16_LE)
  1526. s->sctrl |= SCTRL_P2SEB;
  1527. else
  1528. s->sctrl &= ~SCTRL_P2SEB;
  1529. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1530. spin_unlock_irqrestore(&s->lock, flags);
  1531. }
  1532. }
  1533. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
  1534. AFMT_S16_LE : AFMT_U8, p);
  1535. case SNDCTL_DSP_POST:
  1536. return 0;
  1537. case SNDCTL_DSP_GETTRIGGER:
  1538. val = 0;
  1539. if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
  1540. val |= PCM_ENABLE_INPUT;
  1541. if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
  1542. val |= PCM_ENABLE_OUTPUT;
  1543. return put_user(val, p);
  1544. case SNDCTL_DSP_SETTRIGGER:
  1545. if (get_user(val, p))
  1546. return -EFAULT;
  1547. if (file->f_mode & FMODE_READ) {
  1548. if (val & PCM_ENABLE_INPUT) {
  1549. if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
  1550. return ret;
  1551. s->dma_adc.enabled = 1;
  1552. start_adc(s);
  1553. } else {
  1554. s->dma_adc.enabled = 0;
  1555. stop_adc(s);
  1556. }
  1557. }
  1558. if (file->f_mode & FMODE_WRITE) {
  1559. if (val & PCM_ENABLE_OUTPUT) {
  1560. if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
  1561. return ret;
  1562. s->dma_dac2.enabled = 1;
  1563. start_dac2(s);
  1564. } else {
  1565. s->dma_dac2.enabled = 0;
  1566. stop_dac2(s);
  1567. }
  1568. }
  1569. return 0;
  1570. case SNDCTL_DSP_GETOSPACE:
  1571. if (!(file->f_mode & FMODE_WRITE))
  1572. return -EINVAL;
  1573. if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
  1574. return val;
  1575. spin_lock_irqsave(&s->lock, flags);
  1576. es1371_update_ptr(s);
  1577. abinfo.fragsize = s->dma_dac2.fragsize;
  1578. count = s->dma_dac2.count;
  1579. if (count < 0)
  1580. count = 0;
  1581. abinfo.bytes = s->dma_dac2.dmasize - count;
  1582. abinfo.fragstotal = s->dma_dac2.numfrag;
  1583. abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
  1584. spin_unlock_irqrestore(&s->lock, flags);
  1585. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1586. case SNDCTL_DSP_GETISPACE:
  1587. if (!(file->f_mode & FMODE_READ))
  1588. return -EINVAL;
  1589. if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
  1590. return val;
  1591. spin_lock_irqsave(&s->lock, flags);
  1592. es1371_update_ptr(s);
  1593. abinfo.fragsize = s->dma_adc.fragsize;
  1594. count = s->dma_adc.count;
  1595. if (count < 0)
  1596. count = 0;
  1597. abinfo.bytes = count;
  1598. abinfo.fragstotal = s->dma_adc.numfrag;
  1599. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1600. spin_unlock_irqrestore(&s->lock, flags);
  1601. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1602. case SNDCTL_DSP_NONBLOCK:
  1603. file->f_flags |= O_NONBLOCK;
  1604. return 0;
  1605. case SNDCTL_DSP_GETODELAY:
  1606. if (!(file->f_mode & FMODE_WRITE))
  1607. return -EINVAL;
  1608. if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
  1609. return val;
  1610. spin_lock_irqsave(&s->lock, flags);
  1611. es1371_update_ptr(s);
  1612. count = s->dma_dac2.count;
  1613. spin_unlock_irqrestore(&s->lock, flags);
  1614. if (count < 0)
  1615. count = 0;
  1616. return put_user(count, p);
  1617. case SNDCTL_DSP_GETIPTR:
  1618. if (!(file->f_mode & FMODE_READ))
  1619. return -EINVAL;
  1620. if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
  1621. return val;
  1622. spin_lock_irqsave(&s->lock, flags);
  1623. es1371_update_ptr(s);
  1624. cinfo.bytes = s->dma_adc.total_bytes;
  1625. count = s->dma_adc.count;
  1626. if (count < 0)
  1627. count = 0;
  1628. cinfo.blocks = count >> s->dma_adc.fragshift;
  1629. cinfo.ptr = s->dma_adc.hwptr;
  1630. if (s->dma_adc.mapped)
  1631. s->dma_adc.count &= s->dma_adc.fragsize-1;
  1632. spin_unlock_irqrestore(&s->lock, flags);
  1633. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1634. return -EFAULT;
  1635. return 0;
  1636. case SNDCTL_DSP_GETOPTR:
  1637. if (!(file->f_mode & FMODE_WRITE))
  1638. return -EINVAL;
  1639. if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
  1640. return val;
  1641. spin_lock_irqsave(&s->lock, flags);
  1642. es1371_update_ptr(s);
  1643. cinfo.bytes = s->dma_dac2.total_bytes;
  1644. count = s->dma_dac2.count;
  1645. if (count < 0)
  1646. count = 0;
  1647. cinfo.blocks = count >> s->dma_dac2.fragshift;
  1648. cinfo.ptr = s->dma_dac2.hwptr;
  1649. if (s->dma_dac2.mapped)
  1650. s->dma_dac2.count &= s->dma_dac2.fragsize-1;
  1651. spin_unlock_irqrestore(&s->lock, flags);
  1652. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1653. return -EFAULT;
  1654. return 0;
  1655. case SNDCTL_DSP_GETBLKSIZE:
  1656. if (file->f_mode & FMODE_WRITE) {
  1657. if ((val = prog_dmabuf_dac2(s)))
  1658. return val;
  1659. return put_user(s->dma_dac2.fragsize, p);
  1660. }
  1661. if ((val = prog_dmabuf_adc(s)))
  1662. return val;
  1663. return put_user(s->dma_adc.fragsize, p);
  1664. case SNDCTL_DSP_SETFRAGMENT:
  1665. if (get_user(val, p))
  1666. return -EFAULT;
  1667. if (file->f_mode & FMODE_READ) {
  1668. s->dma_adc.ossfragshift = val & 0xffff;
  1669. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1670. if (s->dma_adc.ossfragshift < 4)
  1671. s->dma_adc.ossfragshift = 4;
  1672. if (s->dma_adc.ossfragshift > 15)
  1673. s->dma_adc.ossfragshift = 15;
  1674. if (s->dma_adc.ossmaxfrags < 4)
  1675. s->dma_adc.ossmaxfrags = 4;
  1676. }
  1677. if (file->f_mode & FMODE_WRITE) {
  1678. s->dma_dac2.ossfragshift = val & 0xffff;
  1679. s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
  1680. if (s->dma_dac2.ossfragshift < 4)
  1681. s->dma_dac2.ossfragshift = 4;
  1682. if (s->dma_dac2.ossfragshift > 15)
  1683. s->dma_dac2.ossfragshift = 15;
  1684. if (s->dma_dac2.ossmaxfrags < 4)
  1685. s->dma_dac2.ossmaxfrags = 4;
  1686. }
  1687. return 0;
  1688. case SNDCTL_DSP_SUBDIVIDE:
  1689. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1690. (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
  1691. return -EINVAL;
  1692. if (get_user(val, p))
  1693. return -EFAULT;
  1694. if (val != 1 && val != 2 && val != 4)
  1695. return -EINVAL;
  1696. if (file->f_mode & FMODE_READ)
  1697. s->dma_adc.subdivision = val;
  1698. if (file->f_mode & FMODE_WRITE)
  1699. s->dma_dac2.subdivision = val;
  1700. return 0;
  1701. case SOUND_PCM_READ_RATE:
  1702. return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
  1703. case SOUND_PCM_READ_CHANNELS:
  1704. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
  1705. case SOUND_PCM_READ_BITS:
  1706. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p);
  1707. case SOUND_PCM_WRITE_FILTER:
  1708. case SNDCTL_DSP_SETSYNCRO:
  1709. case SOUND_PCM_READ_FILTER:
  1710. return -EINVAL;
  1711. }
  1712. return mixdev_ioctl(s->codec, cmd, arg);
  1713. }
  1714. static int es1371_open(struct inode *inode, struct file *file)
  1715. {
  1716. int minor = iminor(inode);
  1717. DECLARE_WAITQUEUE(wait, current);
  1718. unsigned long flags;
  1719. struct list_head *list;
  1720. struct es1371_state *s;
  1721. for (list = devs.next; ; list = list->next) {
  1722. if (list == &devs)
  1723. return -ENODEV;
  1724. s = list_entry(list, struct es1371_state, devs);
  1725. if (!((s->dev_audio ^ minor) & ~0xf))
  1726. break;
  1727. }
  1728. VALIDATE_STATE(s);
  1729. file->private_data = s;
  1730. /* wait for device to become free */
  1731. down(&s->open_sem);
  1732. while (s->open_mode & file->f_mode) {
  1733. if (file->f_flags & O_NONBLOCK) {
  1734. up(&s->open_sem);
  1735. return -EBUSY;
  1736. }
  1737. add_wait_queue(&s->open_wait, &wait);
  1738. __set_current_state(TASK_INTERRUPTIBLE);
  1739. up(&s->open_sem);
  1740. schedule();
  1741. remove_wait_queue(&s->open_wait, &wait);
  1742. set_current_state(TASK_RUNNING);
  1743. if (signal_pending(current))
  1744. return -ERESTARTSYS;
  1745. down(&s->open_sem);
  1746. }
  1747. if (file->f_mode & FMODE_READ) {
  1748. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
  1749. s->dma_adc.enabled = 1;
  1750. set_adc_rate(s, 8000);
  1751. }
  1752. if (file->f_mode & FMODE_WRITE) {
  1753. s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
  1754. s->dma_dac2.enabled = 1;
  1755. set_dac2_rate(s, 8000);
  1756. }
  1757. spin_lock_irqsave(&s->lock, flags);
  1758. if (file->f_mode & FMODE_READ) {
  1759. s->sctrl &= ~SCTRL_R1FMT;
  1760. if ((minor & 0xf) == SND_DEV_DSP16)
  1761. s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
  1762. else
  1763. s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
  1764. }
  1765. if (file->f_mode & FMODE_WRITE) {
  1766. s->sctrl &= ~SCTRL_P2FMT;
  1767. if ((minor & 0xf) == SND_DEV_DSP16)
  1768. s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
  1769. else
  1770. s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
  1771. }
  1772. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1773. spin_unlock_irqrestore(&s->lock, flags);
  1774. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1775. up(&s->open_sem);
  1776. init_MUTEX(&s->sem);
  1777. return nonseekable_open(inode, file);
  1778. }
  1779. static int es1371_release(struct inode *inode, struct file *file)
  1780. {
  1781. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1782. VALIDATE_STATE(s);
  1783. lock_kernel();
  1784. if (file->f_mode & FMODE_WRITE)
  1785. drain_dac2(s, file->f_flags & O_NONBLOCK);
  1786. down(&s->open_sem);
  1787. if (file->f_mode & FMODE_WRITE) {
  1788. stop_dac2(s);
  1789. dealloc_dmabuf(s, &s->dma_dac2);
  1790. }
  1791. if (file->f_mode & FMODE_READ) {
  1792. stop_adc(s);
  1793. dealloc_dmabuf(s, &s->dma_adc);
  1794. }
  1795. s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
  1796. up(&s->open_sem);
  1797. wake_up(&s->open_wait);
  1798. unlock_kernel();
  1799. return 0;
  1800. }
  1801. static /*const*/ struct file_operations es1371_audio_fops = {
  1802. .owner = THIS_MODULE,
  1803. .llseek = no_llseek,
  1804. .read = es1371_read,
  1805. .write = es1371_write,
  1806. .poll = es1371_poll,
  1807. .ioctl = es1371_ioctl,
  1808. .mmap = es1371_mmap,
  1809. .open = es1371_open,
  1810. .release = es1371_release,
  1811. };
  1812. /* --------------------------------------------------------------------- */
  1813. static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1814. {
  1815. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1816. DECLARE_WAITQUEUE(wait, current);
  1817. ssize_t ret = 0;
  1818. unsigned long flags;
  1819. unsigned swptr;
  1820. int cnt;
  1821. VALIDATE_STATE(s);
  1822. if (s->dma_dac1.mapped)
  1823. return -ENXIO;
  1824. if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
  1825. return ret;
  1826. if (!access_ok(VERIFY_READ, buffer, count))
  1827. return -EFAULT;
  1828. add_wait_queue(&s->dma_dac1.wait, &wait);
  1829. while (count > 0) {
  1830. spin_lock_irqsave(&s->lock, flags);
  1831. if (s->dma_dac1.count < 0) {
  1832. s->dma_dac1.count = 0;
  1833. s->dma_dac1.swptr = s->dma_dac1.hwptr;
  1834. }
  1835. swptr = s->dma_dac1.swptr;
  1836. cnt = s->dma_dac1.dmasize-swptr;
  1837. if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
  1838. cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
  1839. if (cnt <= 0)
  1840. __set_current_state(TASK_INTERRUPTIBLE);
  1841. spin_unlock_irqrestore(&s->lock, flags);
  1842. if (cnt > count)
  1843. cnt = count;
  1844. if (cnt <= 0) {
  1845. if (s->dma_dac1.enabled)
  1846. start_dac1(s);
  1847. if (file->f_flags & O_NONBLOCK) {
  1848. if (!ret)
  1849. ret = -EAGAIN;
  1850. break;
  1851. }
  1852. schedule();
  1853. if (signal_pending(current)) {
  1854. if (!ret)
  1855. ret = -ERESTARTSYS;
  1856. break;
  1857. }
  1858. continue;
  1859. }
  1860. if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
  1861. if (!ret)
  1862. ret = -EFAULT;
  1863. break;
  1864. }
  1865. swptr = (swptr + cnt) % s->dma_dac1.dmasize;
  1866. spin_lock_irqsave(&s->lock, flags);
  1867. s->dma_dac1.swptr = swptr;
  1868. s->dma_dac1.count += cnt;
  1869. s->dma_dac1.endcleared = 0;
  1870. spin_unlock_irqrestore(&s->lock, flags);
  1871. count -= cnt;
  1872. buffer += cnt;
  1873. ret += cnt;
  1874. if (s->dma_dac1.enabled)
  1875. start_dac1(s);
  1876. }
  1877. remove_wait_queue(&s->dma_dac1.wait, &wait);
  1878. set_current_state(TASK_RUNNING);
  1879. return ret;
  1880. }
  1881. /* No kernel lock - we have our own spinlock */
  1882. static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
  1883. {
  1884. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1885. unsigned long flags;
  1886. unsigned int mask = 0;
  1887. VALIDATE_STATE(s);
  1888. if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
  1889. return 0;
  1890. poll_wait(file, &s->dma_dac1.wait, wait);
  1891. spin_lock_irqsave(&s->lock, flags);
  1892. es1371_update_ptr(s);
  1893. if (s->dma_dac1.mapped) {
  1894. if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
  1895. mask |= POLLOUT | POLLWRNORM;
  1896. } else {
  1897. if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
  1898. mask |= POLLOUT | POLLWRNORM;
  1899. }
  1900. spin_unlock_irqrestore(&s->lock, flags);
  1901. return mask;
  1902. }
  1903. static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
  1904. {
  1905. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1906. int ret;
  1907. unsigned long size;
  1908. VALIDATE_STATE(s);
  1909. if (!(vma->vm_flags & VM_WRITE))
  1910. return -EINVAL;
  1911. lock_kernel();
  1912. if ((ret = prog_dmabuf_dac1(s)) != 0)
  1913. goto out;
  1914. ret = -EINVAL;
  1915. if (vma->vm_pgoff != 0)
  1916. goto out;
  1917. size = vma->vm_end - vma->vm_start;
  1918. if (size > (PAGE_SIZE << s->dma_dac1.buforder))
  1919. goto out;
  1920. ret = -EAGAIN;
  1921. if (remap_pfn_range(vma, vma->vm_start,
  1922. virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT,
  1923. size, vma->vm_page_prot))
  1924. goto out;
  1925. s->dma_dac1.mapped = 1;
  1926. ret = 0;
  1927. out:
  1928. unlock_kernel();
  1929. return ret;
  1930. }
  1931. static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1932. {
  1933. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1934. unsigned long flags;
  1935. audio_buf_info abinfo;
  1936. count_info cinfo;
  1937. int count;
  1938. int val, ret;
  1939. int __user *p = (int __user *)arg;
  1940. VALIDATE_STATE(s);
  1941. switch (cmd) {
  1942. case OSS_GETVERSION:
  1943. return put_user(SOUND_VERSION, p);
  1944. case SNDCTL_DSP_SYNC:
  1945. return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
  1946. case SNDCTL_DSP_SETDUPLEX:
  1947. return -EINVAL;
  1948. case SNDCTL_DSP_GETCAPS:
  1949. return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1950. case SNDCTL_DSP_RESET:
  1951. stop_dac1(s);
  1952. synchronize_irq(s->irq);
  1953. s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
  1954. return 0;
  1955. case SNDCTL_DSP_SPEED:
  1956. if (get_user(val, p))
  1957. return -EFAULT;
  1958. if (val >= 0) {
  1959. stop_dac1(s);
  1960. s->dma_dac1.ready = 0;
  1961. set_dac1_rate(s, val);
  1962. }
  1963. return put_user(s->dac1rate, p);
  1964. case SNDCTL_DSP_STEREO:
  1965. if (get_user(val, p))
  1966. return -EFAULT;
  1967. stop_dac1(s);
  1968. s->dma_dac1.ready = 0;
  1969. spin_lock_irqsave(&s->lock, flags);
  1970. if (val)
  1971. s->sctrl |= SCTRL_P1SMB;
  1972. else
  1973. s->sctrl &= ~SCTRL_P1SMB;
  1974. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1975. spin_unlock_irqrestore(&s->lock, flags);
  1976. return 0;
  1977. case SNDCTL_DSP_CHANNELS:
  1978. if (get_user(val, p))
  1979. return -EFAULT;
  1980. if (val != 0) {
  1981. stop_dac1(s);
  1982. s->dma_dac1.ready = 0;
  1983. spin_lock_irqsave(&s->lock, flags);
  1984. if (val >= 2)
  1985. s->sctrl |= SCTRL_P1SMB;
  1986. else
  1987. s->sctrl &= ~SCTRL_P1SMB;
  1988. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1989. spin_unlock_irqrestore(&s->lock, flags);
  1990. }
  1991. return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
  1992. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1993. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1994. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1995. if (get_user(val, p))
  1996. return -EFAULT;
  1997. if (val != AFMT_QUERY) {
  1998. stop_dac1(s);
  1999. s->dma_dac1.ready = 0;
  2000. spin_lock_irqsave(&s->lock, flags);
  2001. if (val == AFMT_S16_LE)
  2002. s->sctrl |= SCTRL_P1SEB;
  2003. else
  2004. s->sctrl &= ~SCTRL_P1SEB;
  2005. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  2006. spin_unlock_irqrestore(&s->lock, flags);
  2007. }
  2008. return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p);
  2009. case SNDCTL_DSP_POST:
  2010. return 0;
  2011. case SNDCTL_DSP_GETTRIGGER:
  2012. return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p);
  2013. case SNDCTL_DSP_SETTRIGGER:
  2014. if (get_user(val, p))
  2015. return -EFAULT;
  2016. if (val & PCM_ENABLE_OUTPUT) {
  2017. if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
  2018. return ret;
  2019. s->dma_dac1.enabled = 1;
  2020. start_dac1(s);
  2021. } else {
  2022. s->dma_dac1.enabled = 0;
  2023. stop_dac1(s);
  2024. }
  2025. return 0;
  2026. case SNDCTL_DSP_GETOSPACE:
  2027. if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
  2028. return val;
  2029. spin_lock_irqsave(&s->lock, flags);
  2030. es1371_update_ptr(s);
  2031. abinfo.fragsize = s->dma_dac1.fragsize;
  2032. count = s->dma_dac1.count;
  2033. if (count < 0)
  2034. count = 0;
  2035. abinfo.bytes = s->dma_dac1.dmasize - count;
  2036. abinfo.fragstotal = s->dma_dac1.numfrag;
  2037. abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
  2038. spin_unlock_irqrestore(&s->lock, flags);
  2039. return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  2040. case SNDCTL_DSP_NONBLOCK:
  2041. file->f_flags |= O_NONBLOCK;
  2042. return 0;
  2043. case SNDCTL_DSP_GETODELAY:
  2044. if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
  2045. return val;
  2046. spin_lock_irqsave(&s->lock, flags);
  2047. es1371_update_ptr(s);
  2048. count = s->dma_dac1.count;
  2049. spin_unlock_irqrestore(&s->lock, flags);
  2050. if (count < 0)
  2051. count = 0;
  2052. return put_user(count, p);
  2053. case SNDCTL_DSP_GETOPTR:
  2054. if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
  2055. return val;
  2056. spin_lock_irqsave(&s->lock, flags);
  2057. es1371_update_ptr(s);
  2058. cinfo.bytes = s->dma_dac1.total_bytes;
  2059. count = s->dma_dac1.count;
  2060. if (count < 0)
  2061. count = 0;
  2062. cinfo.blocks = count >> s->dma_dac1.fragshift;
  2063. cinfo.ptr = s->dma_dac1.hwptr;
  2064. if (s->dma_dac1.mapped)
  2065. s->dma_dac1.count &= s->dma_dac1.fragsize-1;
  2066. spin_unlock_irqrestore(&s->lock, flags);
  2067. if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo)))
  2068. return -EFAULT;
  2069. return 0;
  2070. case SNDCTL_DSP_GETBLKSIZE:
  2071. if ((val = prog_dmabuf_dac1(s)))
  2072. return val;
  2073. return put_user(s->dma_dac1.fragsize, p);
  2074. case SNDCTL_DSP_SETFRAGMENT:
  2075. if (get_user(val, p))
  2076. return -EFAULT;
  2077. s->dma_dac1.ossfragshift = val & 0xffff;
  2078. s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
  2079. if (s->dma_dac1.ossfragshift < 4)
  2080. s->dma_dac1.ossfragshift = 4;
  2081. if (s->dma_dac1.ossfragshift > 15)
  2082. s->dma_dac1.ossfragshift = 15;
  2083. if (s->dma_dac1.ossmaxfrags < 4)
  2084. s->dma_dac1.ossmaxfrags = 4;
  2085. return 0;
  2086. case SNDCTL_DSP_SUBDIVIDE:
  2087. if (s->dma_dac1.subdivision)
  2088. return -EINVAL;
  2089. if (get_user(val, p))
  2090. return -EFAULT;
  2091. if (val != 1 && val != 2 && val != 4)
  2092. return -EINVAL;
  2093. s->dma_dac1.subdivision = val;
  2094. return 0;
  2095. case SOUND_PCM_READ_RATE:
  2096. return put_user(s->dac1rate, p);
  2097. case SOUND_PCM_READ_CHANNELS:
  2098. return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
  2099. case SOUND_PCM_READ_BITS:
  2100. return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p);
  2101. case SOUND_PCM_WRITE_FILTER:
  2102. case SNDCTL_DSP_SETSYNCRO:
  2103. case SOUND_PCM_READ_FILTER:
  2104. return -EINVAL;
  2105. }
  2106. return mixdev_ioctl(s->codec, cmd, arg);
  2107. }
  2108. static int es1371_open_dac(struct inode *inode, struct file *file)
  2109. {
  2110. int minor = iminor(inode);
  2111. DECLARE_WAITQUEUE(wait, current);
  2112. unsigned long flags;
  2113. struct list_head *list;
  2114. struct es1371_state *s;
  2115. for (list = devs.next; ; list = list->next) {
  2116. if (list == &devs)
  2117. return -ENODEV;
  2118. s = list_entry(list, struct es1371_state, devs);
  2119. if (!((s->dev_dac ^ minor) & ~0xf))
  2120. break;
  2121. }
  2122. VALIDATE_STATE(s);
  2123. /* we allow opening with O_RDWR, most programs do it although they will only write */
  2124. #if 0
  2125. if (file->f_mode & FMODE_READ)
  2126. return -EPERM;
  2127. #endif
  2128. if (!(file->f_mode & FMODE_WRITE))
  2129. return -EINVAL;
  2130. file->private_data = s;
  2131. /* wait for device to become free */
  2132. down(&s->open_sem);
  2133. while (s->open_mode & FMODE_DAC) {
  2134. if (file->f_flags & O_NONBLOCK) {
  2135. up(&s->open_sem);
  2136. return -EBUSY;
  2137. }
  2138. add_wait_queue(&s->open_wait, &wait);
  2139. __set_current_state(TASK_INTERRUPTIBLE);
  2140. up(&s->open_sem);
  2141. schedule();
  2142. remove_wait_queue(&s->open_wait, &wait);
  2143. set_current_state(TASK_RUNNING);
  2144. if (signal_pending(current))
  2145. return -ERESTARTSYS;
  2146. down(&s->open_sem);
  2147. }
  2148. s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
  2149. s->dma_dac1.enabled = 1;
  2150. set_dac1_rate(s, 8000);
  2151. spin_lock_irqsave(&s->lock, flags);
  2152. s->sctrl &= ~SCTRL_P1FMT;
  2153. if ((minor & 0xf) == SND_DEV_DSP16)
  2154. s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
  2155. else
  2156. s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
  2157. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  2158. spin_unlock_irqrestore(&s->lock, flags);
  2159. s->open_mode |= FMODE_DAC;
  2160. up(&s->open_sem);
  2161. return nonseekable_open(inode, file);
  2162. }
  2163. static int es1371_release_dac(struct inode *inode, struct file *file)
  2164. {
  2165. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2166. VALIDATE_STATE(s);
  2167. lock_kernel();
  2168. drain_dac1(s, file->f_flags & O_NONBLOCK);
  2169. down(&s->open_sem);
  2170. stop_dac1(s);
  2171. dealloc_dmabuf(s, &s->dma_dac1);
  2172. s->open_mode &= ~FMODE_DAC;
  2173. up(&s->open_sem);
  2174. wake_up(&s->open_wait);
  2175. unlock_kernel();
  2176. return 0;
  2177. }
  2178. static /*const*/ struct file_operations es1371_dac_fops = {
  2179. .owner = THIS_MODULE,
  2180. .llseek = no_llseek,
  2181. .write = es1371_write_dac,
  2182. .poll = es1371_poll_dac,
  2183. .ioctl = es1371_ioctl_dac,
  2184. .mmap = es1371_mmap_dac,
  2185. .open = es1371_open_dac,
  2186. .release = es1371_release_dac,
  2187. };
  2188. /* --------------------------------------------------------------------- */
  2189. static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  2190. {
  2191. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2192. DECLARE_WAITQUEUE(wait, current);
  2193. ssize_t ret;
  2194. unsigned long flags;
  2195. unsigned ptr;
  2196. int cnt;
  2197. VALIDATE_STATE(s);
  2198. if (!access_ok(VERIFY_WRITE, buffer, count))
  2199. return -EFAULT;
  2200. if (count == 0)
  2201. return 0;
  2202. ret = 0;
  2203. add_wait_queue(&s->midi.iwait, &wait);
  2204. while (count > 0) {
  2205. spin_lock_irqsave(&s->lock, flags);
  2206. ptr = s->midi.ird;
  2207. cnt = MIDIINBUF - ptr;
  2208. if (s->midi.icnt < cnt)
  2209. cnt = s->midi.icnt;
  2210. if (cnt <= 0)
  2211. __set_current_state(TASK_INTERRUPTIBLE);
  2212. spin_unlock_irqrestore(&s->lock, flags);
  2213. if (cnt > count)
  2214. cnt = count;
  2215. if (cnt <= 0) {
  2216. if (file->f_flags & O_NONBLOCK) {
  2217. if (!ret)
  2218. ret = -EAGAIN;
  2219. break;
  2220. }
  2221. schedule();
  2222. if (signal_pending(current)) {
  2223. if (!ret)
  2224. ret = -ERESTARTSYS;
  2225. break;
  2226. }
  2227. continue;
  2228. }
  2229. if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
  2230. if (!ret)
  2231. ret = -EFAULT;
  2232. break;
  2233. }
  2234. ptr = (ptr + cnt) % MIDIINBUF;
  2235. spin_lock_irqsave(&s->lock, flags);
  2236. s->midi.ird = ptr;
  2237. s->midi.icnt -= cnt;
  2238. spin_unlock_irqrestore(&s->lock, flags);
  2239. count -= cnt;
  2240. buffer += cnt;
  2241. ret += cnt;
  2242. break;
  2243. }
  2244. __set_current_state(TASK_RUNNING);
  2245. remove_wait_queue(&s->midi.iwait, &wait);
  2246. return ret;
  2247. }
  2248. static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  2249. {
  2250. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2251. DECLARE_WAITQUEUE(wait, current);
  2252. ssize_t ret;
  2253. unsigned long flags;
  2254. unsigned ptr;
  2255. int cnt;
  2256. VALIDATE_STATE(s);
  2257. if (!access_ok(VERIFY_READ, buffer, count))
  2258. return -EFAULT;
  2259. if (count == 0)
  2260. return 0;
  2261. ret = 0;
  2262. add_wait_queue(&s->midi.owait, &wait);
  2263. while (count > 0) {
  2264. spin_lock_irqsave(&s->lock, flags);
  2265. ptr = s->midi.owr;
  2266. cnt = MIDIOUTBUF - ptr;
  2267. if (s->midi.ocnt + cnt > MIDIOUTBUF)
  2268. cnt = MIDIOUTBUF - s->midi.ocnt;
  2269. if (cnt <= 0) {
  2270. __set_current_state(TASK_INTERRUPTIBLE);
  2271. es1371_handle_midi(s);
  2272. }
  2273. spin_unlock_irqrestore(&s->lock, flags);
  2274. if (cnt > count)
  2275. cnt = count;
  2276. if (cnt <= 0) {
  2277. if (file->f_flags & O_NONBLOCK) {
  2278. if (!ret)
  2279. ret = -EAGAIN;
  2280. break;
  2281. }
  2282. schedule();
  2283. if (signal_pending(current)) {
  2284. if (!ret)
  2285. ret = -ERESTARTSYS;
  2286. break;
  2287. }
  2288. continue;
  2289. }
  2290. if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
  2291. if (!ret)
  2292. ret = -EFAULT;
  2293. break;
  2294. }
  2295. ptr = (ptr + cnt) % MIDIOUTBUF;
  2296. spin_lock_irqsave(&s->lock, flags);
  2297. s->midi.owr = ptr;
  2298. s->midi.ocnt += cnt;
  2299. spin_unlock_irqrestore(&s->lock, flags);
  2300. count -= cnt;
  2301. buffer += cnt;
  2302. ret += cnt;
  2303. spin_lock_irqsave(&s->lock, flags);
  2304. es1371_handle_midi(s);
  2305. spin_unlock_irqrestore(&s->lock, flags);
  2306. }
  2307. __set_current_state(TASK_RUNNING);
  2308. remove_wait_queue(&s->midi.owait, &wait);
  2309. return ret;
  2310. }
  2311. /* No kernel lock - we have our own spinlock */
  2312. static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
  2313. {
  2314. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2315. unsigned long flags;
  2316. unsigned int mask = 0;
  2317. VALIDATE_STATE(s);
  2318. if (file->f_mode & FMODE_WRITE)
  2319. poll_wait(file, &s->midi.owait, wait);
  2320. if (file->f_mode & FMODE_READ)
  2321. poll_wait(file, &s->midi.iwait, wait);
  2322. spin_lock_irqsave(&s->lock, flags);
  2323. if (file->f_mode & FMODE_READ) {
  2324. if (s->midi.icnt > 0)
  2325. mask |= POLLIN | POLLRDNORM;
  2326. }
  2327. if (file->f_mode & FMODE_WRITE) {
  2328. if (s->midi.ocnt < MIDIOUTBUF)
  2329. mask |= POLLOUT | POLLWRNORM;
  2330. }
  2331. spin_unlock_irqrestore(&s->lock, flags);
  2332. return mask;
  2333. }
  2334. static int es1371_midi_open(struct inode *inode, struct file *file)
  2335. {
  2336. int minor = iminor(inode);
  2337. DECLARE_WAITQUEUE(wait, current);
  2338. unsigned long flags;
  2339. struct list_head *list;
  2340. struct es1371_state *s;
  2341. for (list = devs.next; ; list = list->next) {
  2342. if (list == &devs)
  2343. return -ENODEV;
  2344. s = list_entry(list, struct es1371_state, devs);
  2345. if (s->dev_midi == minor)
  2346. break;
  2347. }
  2348. VALIDATE_STATE(s);
  2349. file->private_data = s;
  2350. /* wait for device to become free */
  2351. down(&s->open_sem);
  2352. while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
  2353. if (file->f_flags & O_NONBLOCK) {
  2354. up(&s->open_sem);
  2355. return -EBUSY;
  2356. }
  2357. add_wait_queue(&s->open_wait, &wait);
  2358. __set_current_state(TASK_INTERRUPTIBLE);
  2359. up(&s->open_sem);
  2360. schedule();
  2361. remove_wait_queue(&s->open_wait, &wait);
  2362. set_current_state(TASK_RUNNING);
  2363. if (signal_pending(current))
  2364. return -ERESTARTSYS;
  2365. down(&s->open_sem);
  2366. }
  2367. spin_lock_irqsave(&s->lock, flags);
  2368. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2369. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2370. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  2371. outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
  2372. outb(0, s->io+ES1371_REG_UART_CONTROL);
  2373. outb(0, s->io+ES1371_REG_UART_TEST);
  2374. }
  2375. if (file->f_mode & FMODE_READ) {
  2376. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2377. }
  2378. if (file->f_mode & FMODE_WRITE) {
  2379. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  2380. }
  2381. s->ctrl |= CTRL_UART_EN;
  2382. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2383. es1371_handle_midi(s);
  2384. spin_unlock_irqrestore(&s->lock, flags);
  2385. s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
  2386. up(&s->open_sem);
  2387. return nonseekable_open(inode, file);
  2388. }
  2389. static int es1371_midi_release(struct inode *inode, struct file *file)
  2390. {
  2391. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2392. DECLARE_WAITQUEUE(wait, current);
  2393. unsigned long flags;
  2394. unsigned count, tmo;
  2395. VALIDATE_STATE(s);
  2396. lock_kernel();
  2397. if (file->f_mode & FMODE_WRITE) {
  2398. add_wait_queue(&s->midi.owait, &wait);
  2399. for (;;) {
  2400. __set_current_state(TASK_INTERRUPTIBLE);
  2401. spin_lock_irqsave(&s->lock, flags);
  2402. count = s->midi.ocnt;
  2403. spin_unlock_irqrestore(&s->lock, flags);
  2404. if (count <= 0)
  2405. break;
  2406. if (signal_pending(current))
  2407. break;
  2408. if (file->f_flags & O_NONBLOCK)
  2409. break;
  2410. tmo = (count * HZ) / 3100;
  2411. if (!schedule_timeout(tmo ? : 1) && tmo)
  2412. printk(KERN_DEBUG PFX "midi timed out??\n");
  2413. }
  2414. remove_wait_queue(&s->midi.owait, &wait);
  2415. set_current_state(TASK_RUNNING);
  2416. }
  2417. down(&s->open_sem);
  2418. s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
  2419. spin_lock_irqsave(&s->lock, flags);
  2420. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2421. s->ctrl &= ~CTRL_UART_EN;
  2422. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2423. }
  2424. spin_unlock_irqrestore(&s->lock, flags);
  2425. up(&s->open_sem);
  2426. wake_up(&s->open_wait);
  2427. unlock_kernel();
  2428. return 0;
  2429. }
  2430. static /*const*/ struct file_operations es1371_midi_fops = {
  2431. .owner = THIS_MODULE,
  2432. .llseek = no_llseek,
  2433. .read = es1371_midi_read,
  2434. .write = es1371_midi_write,
  2435. .poll = es1371_midi_poll,
  2436. .open = es1371_midi_open,
  2437. .release = es1371_midi_release,
  2438. };
  2439. /* --------------------------------------------------------------------- */
  2440. /*
  2441. * for debugging purposes, we'll create a proc device that dumps the
  2442. * CODEC chipstate
  2443. */
  2444. #ifdef ES1371_DEBUG
  2445. static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
  2446. {
  2447. struct es1371_state *s;
  2448. int cnt, len = 0;
  2449. if (list_empty(&devs))
  2450. return 0;
  2451. s = list_entry(devs.next, struct es1371_state, devs);
  2452. /* print out header */
  2453. len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
  2454. /* print out CODEC state */
  2455. len += sprintf (buf + len, "AC97 CODEC state\n");
  2456. for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
  2457. len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt));
  2458. if (fpos >=len){
  2459. *start = buf;
  2460. *eof =1;
  2461. return 0;
  2462. }
  2463. *start = buf + fpos;
  2464. if ((len -= fpos) > length)
  2465. return length;
  2466. *eof =1;
  2467. return len;
  2468. }
  2469. #endif /* ES1371_DEBUG */
  2470. /* --------------------------------------------------------------------- */
  2471. /* maximum number of devices; only used for command line params */
  2472. #define NR_DEVICE 5
  2473. static int spdif[NR_DEVICE];
  2474. static int nomix[NR_DEVICE];
  2475. static int amplifier[NR_DEVICE];
  2476. static unsigned int devindex;
  2477. module_param_array(spdif, bool, NULL, 0);
  2478. MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
  2479. module_param_array(nomix, bool, NULL, 0);
  2480. MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
  2481. module_param_array(amplifier, bool, NULL, 0);
  2482. MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
  2483. MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
  2484. MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
  2485. MODULE_LICENSE("GPL");
  2486. /* --------------------------------------------------------------------- */
  2487. static struct initvol {
  2488. int mixch;
  2489. int vol;
  2490. } initvol[] __devinitdata = {
  2491. { SOUND_MIXER_WRITE_LINE, 0x4040 },
  2492. { SOUND_MIXER_WRITE_CD, 0x4040 },
  2493. { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
  2494. { SOUND_MIXER_WRITE_LINE1, 0x4040 },
  2495. { SOUND_MIXER_WRITE_PCM, 0x4040 },
  2496. { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
  2497. { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
  2498. { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
  2499. { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
  2500. { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
  2501. { SOUND_MIXER_WRITE_MIC, 0x4040 },
  2502. { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
  2503. { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
  2504. };
  2505. static struct
  2506. {
  2507. short svid, sdid;
  2508. } amplifier_needed[] =
  2509. {
  2510. { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
  2511. { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
  2512. { 0x1102, 0x5938 }, /* Targa Xtender 300 */
  2513. { 0x1102, 0x8938 }, /* IPC notebook */
  2514. { PCI_ANY_ID, PCI_ANY_ID }
  2515. };
  2516. #ifdef SUPPORT_JOYSTICK
  2517. static int __devinit es1371_register_gameport(struct es1371_state *s)
  2518. {
  2519. struct gameport *gp;
  2520. int gpio;
  2521. for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08)
  2522. if (request_region(gpio, JOY_EXTENT, "es1371"))
  2523. break;
  2524. if (gpio < 0x200) {
  2525. printk(KERN_ERR PFX "no free joystick address found\n");
  2526. return -EBUSY;
  2527. }
  2528. s->gameport = gp = gameport_allocate_port();
  2529. if (!gp) {
  2530. printk(KERN_ERR PFX "can not allocate memory for gameport\n");
  2531. release_region(gpio, JOY_EXTENT);
  2532. return -ENOMEM;
  2533. }
  2534. gameport_set_name(gp, "ESS1371 Gameport");
  2535. gameport_set_phys(gp, "isa%04x/gameport0", gpio);
  2536. gp->dev.parent = &s->dev->dev;
  2537. gp->io = gpio;
  2538. s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
  2539. outl(s->ctrl, s->io + ES1371_REG_CONTROL);
  2540. gameport_register_port(gp);
  2541. return 0;
  2542. }
  2543. static inline void es1371_unregister_gameport(struct es1371_state *s)
  2544. {
  2545. if (s->gameport) {
  2546. int gpio = s->gameport->io;
  2547. gameport_unregister_port(s->gameport);
  2548. release_region(gpio, JOY_EXTENT);
  2549. }
  2550. }
  2551. #else
  2552. static inline int es1371_register_gameport(struct es1371_state *s) { return -ENOSYS; }
  2553. static inline void es1371_unregister_gameport(struct es1371_state *s) { }
  2554. #endif /* SUPPORT_JOYSTICK */
  2555. static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
  2556. {
  2557. struct es1371_state *s;
  2558. mm_segment_t fs;
  2559. int i, val, res = -1;
  2560. int idx;
  2561. unsigned long tmo;
  2562. signed long tmo2;
  2563. unsigned int cssr;
  2564. if ((res=pci_enable_device(pcidev)))
  2565. return res;
  2566. if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
  2567. return -ENODEV;
  2568. if (pcidev->irq == 0)
  2569. return -ENODEV;
  2570. i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
  2571. if (i) {
  2572. printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
  2573. return i;
  2574. }
  2575. if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
  2576. printk(KERN_WARNING PFX "out of memory\n");
  2577. return -ENOMEM;
  2578. }
  2579. memset(s, 0, sizeof(struct es1371_state));
  2580. s->codec = ac97_alloc_codec();
  2581. if(s->codec == NULL)
  2582. goto err_codec;
  2583. init_waitqueue_head(&s->dma_adc.wait);
  2584. init_waitqueue_head(&s->dma_dac1.wait);
  2585. init_waitqueue_head(&s->dma_dac2.wait);
  2586. init_waitqueue_head(&s->open_wait);
  2587. init_waitqueue_head(&s->midi.iwait);
  2588. init_waitqueue_head(&s->midi.owait);
  2589. init_MUTEX(&s->open_sem);
  2590. spin_lock_init(&s->lock);
  2591. s->magic = ES1371_MAGIC;
  2592. s->dev = pcidev;
  2593. s->io = pci_resource_start(pcidev, 0);
  2594. s->irq = pcidev->irq;
  2595. s->vendor = pcidev->vendor;
  2596. s->device = pcidev->device;
  2597. pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
  2598. s->codec->private_data = s;
  2599. s->codec->id = 0;
  2600. s->codec->codec_read = rdcodec;
  2601. s->codec->codec_write = wrcodec;
  2602. printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
  2603. s->vendor, s->device, s->rev);
  2604. if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
  2605. printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
  2606. res = -EBUSY;
  2607. goto err_region;
  2608. }
  2609. if ((res=request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371",s))) {
  2610. printk(KERN_ERR PFX "irq %u in use\n", s->irq);
  2611. goto err_irq;
  2612. }
  2613. printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n",
  2614. s->rev, s->io, s->irq);
  2615. /* register devices */
  2616. if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0)
  2617. goto err_dev1;
  2618. if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0)
  2619. goto err_dev2;
  2620. if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0)
  2621. goto err_dev3;
  2622. if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 )
  2623. goto err_dev4;
  2624. #ifdef ES1371_DEBUG
  2625. /* initialize the debug proc device */
  2626. s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
  2627. #endif /* ES1371_DEBUG */
  2628. /* initialize codec registers */
  2629. s->ctrl = 0;
  2630. /* Check amplifier requirements */
  2631. if (amplifier[devindex])
  2632. s->ctrl |= CTRL_GPIO_OUT0;
  2633. else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
  2634. {
  2635. if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
  2636. pcidev->subsystem_device == amplifier_needed[idx].sdid)
  2637. {
  2638. s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
  2639. printk(KERN_INFO PFX "Enabling internal amplifier.\n");
  2640. }
  2641. }
  2642. s->sctrl = 0;
  2643. cssr = 0;
  2644. s->spdif_volume = -1;
  2645. /* check to see if s/pdif mode is being requested */
  2646. if (spdif[devindex]) {
  2647. if (s->rev >= 4) {
  2648. printk(KERN_INFO PFX "enabling S/PDIF output\n");
  2649. s->spdif_volume = 0;
  2650. cssr |= STAT_EN_SPDIF;
  2651. s->ctrl |= CTRL_SPDIFEN_B;
  2652. if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
  2653. s->ctrl |= CTRL_RECEN_B;
  2654. } else {
  2655. printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
  2656. }
  2657. }
  2658. /* initialize the chips */
  2659. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2660. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  2661. outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY);
  2662. pci_set_master(pcidev); /* enable bus mastering */
  2663. /* if we are a 5880 turn on the AC97 */
  2664. if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
  2665. ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
  2666. (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
  2667. (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
  2668. cssr |= CSTAT_5880_AC97_RST;
  2669. outl(cssr, s->io+ES1371_REG_STATUS);
  2670. /* need to delay around 20ms(bleech) to give
  2671. some CODECs enough time to wakeup */
  2672. tmo = jiffies + (HZ / 50) + 1;
  2673. for (;;) {
  2674. tmo2 = tmo - jiffies;
  2675. if (tmo2 <= 0)
  2676. break;
  2677. schedule_timeout(tmo2);
  2678. }
  2679. }
  2680. /* AC97 warm reset to start the bitclk */
  2681. outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
  2682. udelay(2);
  2683. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2684. /* init the sample rate converter */
  2685. src_init(s);
  2686. /* codec init */
  2687. if (!ac97_probe_codec(s->codec)) {
  2688. res = -ENODEV;
  2689. goto err_gp;
  2690. }
  2691. /* set default values */
  2692. fs = get_fs();
  2693. set_fs(KERNEL_DS);
  2694. val = SOUND_MASK_LINE;
  2695. mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
  2696. for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
  2697. val = initvol[i].vol;
  2698. mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val);
  2699. }
  2700. /* mute master and PCM when in S/PDIF mode */
  2701. if (s->spdif_volume != -1) {
  2702. val = 0x0000;
  2703. s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
  2704. s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
  2705. }
  2706. set_fs(fs);
  2707. /* turn on S/PDIF output driver if requested */
  2708. outl(cssr, s->io+ES1371_REG_STATUS);
  2709. es1371_register_gameport(s);
  2710. /* store it in the driver field */
  2711. pci_set_drvdata(pcidev, s);
  2712. /* put it into driver list */
  2713. list_add_tail(&s->devs, &devs);
  2714. /* increment devindex */
  2715. if (devindex < NR_DEVICE-1)
  2716. devindex++;
  2717. return 0;
  2718. err_gp:
  2719. #ifdef ES1371_DEBUG
  2720. if (s->ps)
  2721. remove_proc_entry("es1371", NULL);
  2722. #endif
  2723. unregister_sound_midi(s->dev_midi);
  2724. err_dev4:
  2725. unregister_sound_dsp(s->dev_dac);
  2726. err_dev3:
  2727. unregister_sound_mixer(s->codec->dev_mixer);
  2728. err_dev2:
  2729. unregister_sound_dsp(s->dev_audio);
  2730. err_dev1:
  2731. printk(KERN_ERR PFX "cannot register misc device\n");
  2732. free_irq(s->irq, s);
  2733. err_irq:
  2734. release_region(s->io, ES1371_EXTENT);
  2735. err_region:
  2736. err_codec:
  2737. ac97_release_codec(s->codec);
  2738. kfree(s);
  2739. return res;
  2740. }
  2741. static void __devexit es1371_remove(struct pci_dev *dev)
  2742. {
  2743. struct es1371_state *s = pci_get_drvdata(dev);
  2744. if (!s)
  2745. return;
  2746. list_del(&s->devs);
  2747. #ifdef ES1371_DEBUG
  2748. if (s->ps)
  2749. remove_proc_entry("es1371", NULL);
  2750. #endif /* ES1371_DEBUG */
  2751. outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
  2752. outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
  2753. synchronize_irq(s->irq);
  2754. free_irq(s->irq, s);
  2755. es1371_unregister_gameport(s);
  2756. release_region(s->io, ES1371_EXTENT);
  2757. unregister_sound_dsp(s->dev_audio);
  2758. unregister_sound_mixer(s->codec->dev_mixer);
  2759. unregister_sound_dsp(s->dev_dac);
  2760. unregister_sound_midi(s->dev_midi);
  2761. ac97_release_codec(s->codec);
  2762. kfree(s);
  2763. pci_set_drvdata(dev, NULL);
  2764. }
  2765. static struct pci_device_id id_table[] = {
  2766. { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2767. { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2768. { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2769. { 0, }
  2770. };
  2771. MODULE_DEVICE_TABLE(pci, id_table);
  2772. static struct pci_driver es1371_driver = {
  2773. .name = "es1371",
  2774. .id_table = id_table,
  2775. .probe = es1371_probe,
  2776. .remove = __devexit_p(es1371_remove),
  2777. };
  2778. static int __init init_es1371(void)
  2779. {
  2780. printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n");
  2781. return pci_register_driver(&es1371_driver);
  2782. }
  2783. static void __exit cleanup_es1371(void)
  2784. {
  2785. printk(KERN_INFO PFX "unloading\n");
  2786. pci_unregister_driver(&es1371_driver);
  2787. }
  2788. module_init(init_es1371);
  2789. module_exit(cleanup_es1371);
  2790. /* --------------------------------------------------------------------- */
  2791. #ifndef MODULE
  2792. /* format is: es1371=[spdif,[nomix,[amplifier]]] */
  2793. static int __init es1371_setup(char *str)
  2794. {
  2795. static unsigned __initdata nr_dev = 0;
  2796. if (nr_dev >= NR_DEVICE)
  2797. return 0;
  2798. (void)
  2799. ((get_option(&str, &spdif[nr_dev]) == 2)
  2800. && (get_option(&str, &nomix[nr_dev]) == 2)
  2801. && (get_option(&str, &amplifier[nr_dev])));
  2802. nr_dev++;
  2803. return 1;
  2804. }
  2805. __setup("es1371=", es1371_setup);
  2806. #endif /* MODULE */