au1000.c 57 KB

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  1. /*
  2. * au1000.c -- Sound driver for Alchemy Au1000 MIPS Internet Edge
  3. * Processor.
  4. *
  5. * Copyright 2001 MontaVista Software Inc.
  6. * Author: MontaVista Software, Inc.
  7. * stevel@mvista.com or source@mvista.com
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  17. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  20. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. *
  25. * You should have received a copy of the GNU General Public License along
  26. * with this program; if not, write to the Free Software Foundation, Inc.,
  27. * 675 Mass Ave, Cambridge, MA 02139, USA.
  28. *
  29. *
  30. * Module command line parameters:
  31. *
  32. * Supported devices:
  33. * /dev/dsp standard OSS /dev/dsp device
  34. * /dev/mixer standard OSS /dev/mixer device
  35. *
  36. * Notes:
  37. *
  38. * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
  39. * taken, slightly modified or not at all, from the ES1371 driver,
  40. * so refer to the credits in es1371.c for those. The rest of the
  41. * code (probe, open, read, write, the ISR, etc.) is new.
  42. *
  43. * Revision history
  44. * 06.27.2001 Initial version
  45. * 03.20.2002 Added mutex locks around read/write methods, to prevent
  46. * simultaneous access on SMP or preemptible kernels. Also
  47. * removed the counter/pointer fragment aligning at the end
  48. * of read/write methods [stevel].
  49. * 03.21.2002 Add support for coherent DMA on the audio read/write DMA
  50. * channels [stevel].
  51. *
  52. */
  53. #include <linux/module.h>
  54. #include <linux/string.h>
  55. #include <linux/ioport.h>
  56. #include <linux/sched.h>
  57. #include <linux/delay.h>
  58. #include <linux/sound.h>
  59. #include <linux/slab.h>
  60. #include <linux/soundcard.h>
  61. #include <linux/init.h>
  62. #include <linux/page-flags.h>
  63. #include <linux/poll.h>
  64. #include <linux/pci.h>
  65. #include <linux/bitops.h>
  66. #include <linux/proc_fs.h>
  67. #include <linux/spinlock.h>
  68. #include <linux/smp_lock.h>
  69. #include <linux/ac97_codec.h>
  70. #include <linux/interrupt.h>
  71. #include <asm/io.h>
  72. #include <asm/uaccess.h>
  73. #include <asm/mach-au1x00/au1000.h>
  74. #include <asm/mach-au1x00/au1000_dma.h>
  75. /* --------------------------------------------------------------------- */
  76. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  77. #undef AU1000_DEBUG
  78. #undef AU1000_VERBOSE_DEBUG
  79. #define AU1000_MODULE_NAME "Au1000 audio"
  80. #define PFX AU1000_MODULE_NAME
  81. #ifdef AU1000_DEBUG
  82. #define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
  83. #else
  84. #define dbg(format, arg...) do {} while (0)
  85. #endif
  86. #define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
  87. #define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
  88. #define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
  89. /* misc stuff */
  90. #define POLL_COUNT 0x5000
  91. #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  92. /* Boot options */
  93. static int vra = 0; // 0 = no VRA, 1 = use VRA if codec supports it
  94. MODULE_PARM(vra, "i");
  95. MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  96. /* --------------------------------------------------------------------- */
  97. struct au1000_state {
  98. /* soundcore stuff */
  99. int dev_audio;
  100. #ifdef AU1000_DEBUG
  101. /* debug /proc entry */
  102. struct proc_dir_entry *ps;
  103. struct proc_dir_entry *ac97_ps;
  104. #endif /* AU1000_DEBUG */
  105. struct ac97_codec codec;
  106. unsigned codec_base_caps;// AC'97 reg 00h, "Reset Register"
  107. unsigned codec_ext_caps; // AC'97 reg 28h, "Extended Audio ID"
  108. int no_vra; // do not use VRA
  109. spinlock_t lock;
  110. struct semaphore open_sem;
  111. struct semaphore sem;
  112. mode_t open_mode;
  113. wait_queue_head_t open_wait;
  114. struct dmabuf {
  115. unsigned int dmanr; // DMA Channel number
  116. unsigned sample_rate; // Hz
  117. unsigned src_factor; // SRC interp/decimation (no vra)
  118. unsigned sample_size; // 8 or 16
  119. int num_channels; // 1 = mono, 2 = stereo, 4, 6
  120. int dma_bytes_per_sample;// DMA bytes per audio sample frame
  121. int user_bytes_per_sample;// User bytes per audio sample frame
  122. int cnt_factor; // user-to-DMA bytes per audio
  123. // sample frame
  124. void *rawbuf;
  125. dma_addr_t dmaaddr;
  126. unsigned buforder;
  127. unsigned numfrag; // # of DMA fragments in DMA buffer
  128. unsigned fragshift;
  129. void *nextIn; // ptr to next-in to DMA buffer
  130. void *nextOut;// ptr to next-out from DMA buffer
  131. int count; // current byte count in DMA buffer
  132. unsigned total_bytes; // total bytes written or read
  133. unsigned error; // over/underrun
  134. wait_queue_head_t wait;
  135. /* redundant, but makes calculations easier */
  136. unsigned fragsize; // user perception of fragment size
  137. unsigned dma_fragsize; // DMA (real) fragment size
  138. unsigned dmasize; // Total DMA buffer size
  139. // (mult. of DMA fragsize)
  140. /* OSS stuff */
  141. unsigned mapped:1;
  142. unsigned ready:1;
  143. unsigned stopped:1;
  144. unsigned ossfragshift;
  145. int ossmaxfrags;
  146. unsigned subdivision;
  147. } dma_dac , dma_adc;
  148. } au1000_state;
  149. /* --------------------------------------------------------------------- */
  150. static inline unsigned ld2(unsigned int x)
  151. {
  152. unsigned r = 0;
  153. if (x >= 0x10000) {
  154. x >>= 16;
  155. r += 16;
  156. }
  157. if (x >= 0x100) {
  158. x >>= 8;
  159. r += 8;
  160. }
  161. if (x >= 0x10) {
  162. x >>= 4;
  163. r += 4;
  164. }
  165. if (x >= 4) {
  166. x >>= 2;
  167. r += 2;
  168. }
  169. if (x >= 2)
  170. r++;
  171. return r;
  172. }
  173. /* --------------------------------------------------------------------- */
  174. static void au1000_delay(int msec)
  175. {
  176. unsigned long tmo;
  177. signed long tmo2;
  178. if (in_interrupt())
  179. return;
  180. tmo = jiffies + (msec * HZ) / 1000;
  181. for (;;) {
  182. tmo2 = tmo - jiffies;
  183. if (tmo2 <= 0)
  184. break;
  185. schedule_timeout(tmo2);
  186. }
  187. }
  188. /* --------------------------------------------------------------------- */
  189. static u16 rdcodec(struct ac97_codec *codec, u8 addr)
  190. {
  191. struct au1000_state *s = (struct au1000_state *)codec->private_data;
  192. unsigned long flags;
  193. u32 cmd;
  194. u16 data;
  195. int i;
  196. spin_lock_irqsave(&s->lock, flags);
  197. for (i = 0; i < POLL_COUNT; i++)
  198. if (!(au_readl(AC97C_STATUS) & AC97C_CP))
  199. break;
  200. if (i == POLL_COUNT)
  201. err("rdcodec: codec cmd pending expired!");
  202. cmd = (u32) addr & AC97C_INDEX_MASK;
  203. cmd |= AC97C_READ; // read command
  204. au_writel(cmd, AC97C_CMD);
  205. /* now wait for the data */
  206. for (i = 0; i < POLL_COUNT; i++)
  207. if (!(au_readl(AC97C_STATUS) & AC97C_CP))
  208. break;
  209. if (i == POLL_COUNT) {
  210. err("rdcodec: read poll expired!");
  211. return 0;
  212. }
  213. data = au_readl(AC97C_CMD) & 0xffff;
  214. spin_unlock_irqrestore(&s->lock, flags);
  215. return data;
  216. }
  217. static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  218. {
  219. struct au1000_state *s = (struct au1000_state *)codec->private_data;
  220. unsigned long flags;
  221. u32 cmd;
  222. int i;
  223. spin_lock_irqsave(&s->lock, flags);
  224. for (i = 0; i < POLL_COUNT; i++)
  225. if (!(au_readl(AC97C_STATUS) & AC97C_CP))
  226. break;
  227. if (i == POLL_COUNT)
  228. err("wrcodec: codec cmd pending expired!");
  229. cmd = (u32) addr & AC97C_INDEX_MASK;
  230. cmd &= ~AC97C_READ; // write command
  231. cmd |= ((u32) data << AC97C_WD_BIT); // OR in the data word
  232. au_writel(cmd, AC97C_CMD);
  233. spin_unlock_irqrestore(&s->lock, flags);
  234. }
  235. static void waitcodec(struct ac97_codec *codec)
  236. {
  237. u16 temp;
  238. int i;
  239. /* codec_wait is used to wait for a ready state after
  240. an AC97C_RESET. */
  241. au1000_delay(10);
  242. // first poll the CODEC_READY tag bit
  243. for (i = 0; i < POLL_COUNT; i++)
  244. if (au_readl(AC97C_STATUS) & AC97C_READY)
  245. break;
  246. if (i == POLL_COUNT) {
  247. err("waitcodec: CODEC_READY poll expired!");
  248. return;
  249. }
  250. // get AC'97 powerdown control/status register
  251. temp = rdcodec(codec, AC97_POWER_CONTROL);
  252. // If anything is powered down, power'em up
  253. if (temp & 0x7f00) {
  254. // Power on
  255. wrcodec(codec, AC97_POWER_CONTROL, 0);
  256. au1000_delay(100);
  257. // Reread
  258. temp = rdcodec(codec, AC97_POWER_CONTROL);
  259. }
  260. // Check if Codec REF,ANL,DAC,ADC ready
  261. if ((temp & 0x7f0f) != 0x000f)
  262. err("codec reg 26 status (0x%x) not ready!!", temp);
  263. }
  264. /* --------------------------------------------------------------------- */
  265. /* stop the ADC before calling */
  266. static void set_adc_rate(struct au1000_state *s, unsigned rate)
  267. {
  268. struct dmabuf *adc = &s->dma_adc;
  269. struct dmabuf *dac = &s->dma_dac;
  270. unsigned adc_rate, dac_rate;
  271. u16 ac97_extstat;
  272. if (s->no_vra) {
  273. // calc SRC factor
  274. adc->src_factor = ((96000 / rate) + 1) >> 1;
  275. adc->sample_rate = 48000 / adc->src_factor;
  276. return;
  277. }
  278. adc->src_factor = 1;
  279. ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
  280. rate = rate > 48000 ? 48000 : rate;
  281. // enable VRA
  282. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  283. ac97_extstat | AC97_EXTSTAT_VRA);
  284. // now write the sample rate
  285. wrcodec(&s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
  286. // read it back for actual supported rate
  287. adc_rate = rdcodec(&s->codec, AC97_PCM_LR_ADC_RATE);
  288. #ifdef AU1000_VERBOSE_DEBUG
  289. dbg("%s: set to %d Hz", __FUNCTION__, adc_rate);
  290. #endif
  291. // some codec's don't allow unequal DAC and ADC rates, in which case
  292. // writing one rate reg actually changes both.
  293. dac_rate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE);
  294. if (dac->num_channels > 2)
  295. wrcodec(&s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
  296. if (dac->num_channels > 4)
  297. wrcodec(&s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
  298. adc->sample_rate = adc_rate;
  299. dac->sample_rate = dac_rate;
  300. }
  301. /* stop the DAC before calling */
  302. static void set_dac_rate(struct au1000_state *s, unsigned rate)
  303. {
  304. struct dmabuf *dac = &s->dma_dac;
  305. struct dmabuf *adc = &s->dma_adc;
  306. unsigned adc_rate, dac_rate;
  307. u16 ac97_extstat;
  308. if (s->no_vra) {
  309. // calc SRC factor
  310. dac->src_factor = ((96000 / rate) + 1) >> 1;
  311. dac->sample_rate = 48000 / dac->src_factor;
  312. return;
  313. }
  314. dac->src_factor = 1;
  315. ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
  316. rate = rate > 48000 ? 48000 : rate;
  317. // enable VRA
  318. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  319. ac97_extstat | AC97_EXTSTAT_VRA);
  320. // now write the sample rate
  321. wrcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
  322. // I don't support different sample rates for multichannel,
  323. // so make these channels the same.
  324. if (dac->num_channels > 2)
  325. wrcodec(&s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
  326. if (dac->num_channels > 4)
  327. wrcodec(&s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
  328. // read it back for actual supported rate
  329. dac_rate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE);
  330. #ifdef AU1000_VERBOSE_DEBUG
  331. dbg("%s: set to %d Hz", __FUNCTION__, dac_rate);
  332. #endif
  333. // some codec's don't allow unequal DAC and ADC rates, in which case
  334. // writing one rate reg actually changes both.
  335. adc_rate = rdcodec(&s->codec, AC97_PCM_LR_ADC_RATE);
  336. dac->sample_rate = dac_rate;
  337. adc->sample_rate = adc_rate;
  338. }
  339. static void stop_dac(struct au1000_state *s)
  340. {
  341. struct dmabuf *db = &s->dma_dac;
  342. unsigned long flags;
  343. if (db->stopped)
  344. return;
  345. spin_lock_irqsave(&s->lock, flags);
  346. disable_dma(db->dmanr);
  347. db->stopped = 1;
  348. spin_unlock_irqrestore(&s->lock, flags);
  349. }
  350. static void stop_adc(struct au1000_state *s)
  351. {
  352. struct dmabuf *db = &s->dma_adc;
  353. unsigned long flags;
  354. if (db->stopped)
  355. return;
  356. spin_lock_irqsave(&s->lock, flags);
  357. disable_dma(db->dmanr);
  358. db->stopped = 1;
  359. spin_unlock_irqrestore(&s->lock, flags);
  360. }
  361. static void set_xmit_slots(int num_channels)
  362. {
  363. u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_XMIT_SLOTS_MASK;
  364. switch (num_channels) {
  365. case 1: // mono
  366. case 2: // stereo, slots 3,4
  367. ac97_config |= (0x3 << AC97C_XMIT_SLOTS_BIT);
  368. break;
  369. case 4: // stereo with surround, slots 3,4,7,8
  370. ac97_config |= (0x33 << AC97C_XMIT_SLOTS_BIT);
  371. break;
  372. case 6: // stereo with surround and center/LFE, slots 3,4,6,7,8,9
  373. ac97_config |= (0x7b << AC97C_XMIT_SLOTS_BIT);
  374. break;
  375. }
  376. au_writel(ac97_config, AC97C_CONFIG);
  377. }
  378. static void set_recv_slots(int num_channels)
  379. {
  380. u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_RECV_SLOTS_MASK;
  381. /*
  382. * Always enable slots 3 and 4 (stereo). Slot 6 is
  383. * optional Mic ADC, which I don't support yet.
  384. */
  385. ac97_config |= (0x3 << AC97C_RECV_SLOTS_BIT);
  386. au_writel(ac97_config, AC97C_CONFIG);
  387. }
  388. static void start_dac(struct au1000_state *s)
  389. {
  390. struct dmabuf *db = &s->dma_dac;
  391. unsigned long flags;
  392. unsigned long buf1, buf2;
  393. if (!db->stopped)
  394. return;
  395. spin_lock_irqsave(&s->lock, flags);
  396. au_readl(AC97C_STATUS); // read status to clear sticky bits
  397. // reset Buffer 1 and 2 pointers to nextOut and nextOut+dma_fragsize
  398. buf1 = virt_to_phys(db->nextOut);
  399. buf2 = buf1 + db->dma_fragsize;
  400. if (buf2 >= db->dmaaddr + db->dmasize)
  401. buf2 -= db->dmasize;
  402. set_xmit_slots(db->num_channels);
  403. init_dma(db->dmanr);
  404. if (get_dma_active_buffer(db->dmanr) == 0) {
  405. clear_dma_done0(db->dmanr); // clear DMA done bit
  406. set_dma_addr0(db->dmanr, buf1);
  407. set_dma_addr1(db->dmanr, buf2);
  408. } else {
  409. clear_dma_done1(db->dmanr); // clear DMA done bit
  410. set_dma_addr1(db->dmanr, buf1);
  411. set_dma_addr0(db->dmanr, buf2);
  412. }
  413. set_dma_count(db->dmanr, db->dma_fragsize>>1);
  414. enable_dma_buffers(db->dmanr);
  415. start_dma(db->dmanr);
  416. #ifdef AU1000_VERBOSE_DEBUG
  417. dump_au1000_dma_channel(db->dmanr);
  418. #endif
  419. db->stopped = 0;
  420. spin_unlock_irqrestore(&s->lock, flags);
  421. }
  422. static void start_adc(struct au1000_state *s)
  423. {
  424. struct dmabuf *db = &s->dma_adc;
  425. unsigned long flags;
  426. unsigned long buf1, buf2;
  427. if (!db->stopped)
  428. return;
  429. spin_lock_irqsave(&s->lock, flags);
  430. au_readl(AC97C_STATUS); // read status to clear sticky bits
  431. // reset Buffer 1 and 2 pointers to nextIn and nextIn+dma_fragsize
  432. buf1 = virt_to_phys(db->nextIn);
  433. buf2 = buf1 + db->dma_fragsize;
  434. if (buf2 >= db->dmaaddr + db->dmasize)
  435. buf2 -= db->dmasize;
  436. set_recv_slots(db->num_channels);
  437. init_dma(db->dmanr);
  438. if (get_dma_active_buffer(db->dmanr) == 0) {
  439. clear_dma_done0(db->dmanr); // clear DMA done bit
  440. set_dma_addr0(db->dmanr, buf1);
  441. set_dma_addr1(db->dmanr, buf2);
  442. } else {
  443. clear_dma_done1(db->dmanr); // clear DMA done bit
  444. set_dma_addr1(db->dmanr, buf1);
  445. set_dma_addr0(db->dmanr, buf2);
  446. }
  447. set_dma_count(db->dmanr, db->dma_fragsize>>1);
  448. enable_dma_buffers(db->dmanr);
  449. start_dma(db->dmanr);
  450. #ifdef AU1000_VERBOSE_DEBUG
  451. dump_au1000_dma_channel(db->dmanr);
  452. #endif
  453. db->stopped = 0;
  454. spin_unlock_irqrestore(&s->lock, flags);
  455. }
  456. /* --------------------------------------------------------------------- */
  457. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  458. #define DMABUF_MINORDER 1
  459. static inline void dealloc_dmabuf(struct au1000_state *s, struct dmabuf *db)
  460. {
  461. struct page *page, *pend;
  462. if (db->rawbuf) {
  463. /* undo marking the pages as reserved */
  464. pend = virt_to_page(db->rawbuf +
  465. (PAGE_SIZE << db->buforder) - 1);
  466. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  467. ClearPageReserved(page);
  468. dma_free_noncoherent(NULL,
  469. PAGE_SIZE << db->buforder,
  470. db->rawbuf,
  471. db->dmaaddr);
  472. }
  473. db->rawbuf = db->nextIn = db->nextOut = NULL;
  474. db->mapped = db->ready = 0;
  475. }
  476. static int prog_dmabuf(struct au1000_state *s, struct dmabuf *db)
  477. {
  478. int order;
  479. unsigned user_bytes_per_sec;
  480. unsigned bufs;
  481. struct page *page, *pend;
  482. unsigned rate = db->sample_rate;
  483. if (!db->rawbuf) {
  484. db->ready = db->mapped = 0;
  485. for (order = DMABUF_DEFAULTORDER;
  486. order >= DMABUF_MINORDER; order--)
  487. if ((db->rawbuf = dma_alloc_noncoherent(NULL,
  488. PAGE_SIZE << order,
  489. &db->dmaaddr,
  490. 0)))
  491. break;
  492. if (!db->rawbuf)
  493. return -ENOMEM;
  494. db->buforder = order;
  495. /* now mark the pages as reserved;
  496. otherwise remap_pfn_range doesn't do what we want */
  497. pend = virt_to_page(db->rawbuf +
  498. (PAGE_SIZE << db->buforder) - 1);
  499. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  500. SetPageReserved(page);
  501. }
  502. db->cnt_factor = 1;
  503. if (db->sample_size == 8)
  504. db->cnt_factor *= 2;
  505. if (db->num_channels == 1)
  506. db->cnt_factor *= 2;
  507. db->cnt_factor *= db->src_factor;
  508. db->count = 0;
  509. db->nextIn = db->nextOut = db->rawbuf;
  510. db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
  511. db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
  512. 2 : db->num_channels);
  513. user_bytes_per_sec = rate * db->user_bytes_per_sample;
  514. bufs = PAGE_SIZE << db->buforder;
  515. if (db->ossfragshift) {
  516. if ((1000 << db->ossfragshift) < user_bytes_per_sec)
  517. db->fragshift = ld2(user_bytes_per_sec/1000);
  518. else
  519. db->fragshift = db->ossfragshift;
  520. } else {
  521. db->fragshift = ld2(user_bytes_per_sec / 100 /
  522. (db->subdivision ? db->subdivision : 1));
  523. if (db->fragshift < 3)
  524. db->fragshift = 3;
  525. }
  526. db->fragsize = 1 << db->fragshift;
  527. db->dma_fragsize = db->fragsize * db->cnt_factor;
  528. db->numfrag = bufs / db->dma_fragsize;
  529. while (db->numfrag < 4 && db->fragshift > 3) {
  530. db->fragshift--;
  531. db->fragsize = 1 << db->fragshift;
  532. db->dma_fragsize = db->fragsize * db->cnt_factor;
  533. db->numfrag = bufs / db->dma_fragsize;
  534. }
  535. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  536. db->numfrag = db->ossmaxfrags;
  537. db->dmasize = db->dma_fragsize * db->numfrag;
  538. memset(db->rawbuf, 0, bufs);
  539. #ifdef AU1000_VERBOSE_DEBUG
  540. dbg("rate=%d, samplesize=%d, channels=%d",
  541. rate, db->sample_size, db->num_channels);
  542. dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
  543. db->fragsize, db->cnt_factor, db->dma_fragsize);
  544. dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
  545. #endif
  546. db->ready = 1;
  547. return 0;
  548. }
  549. static inline int prog_dmabuf_adc(struct au1000_state *s)
  550. {
  551. stop_adc(s);
  552. return prog_dmabuf(s, &s->dma_adc);
  553. }
  554. static inline int prog_dmabuf_dac(struct au1000_state *s)
  555. {
  556. stop_dac(s);
  557. return prog_dmabuf(s, &s->dma_dac);
  558. }
  559. /* hold spinlock for the following */
  560. static irqreturn_t dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  561. {
  562. struct au1000_state *s = (struct au1000_state *) dev_id;
  563. struct dmabuf *dac = &s->dma_dac;
  564. unsigned long newptr;
  565. u32 ac97c_stat, buff_done;
  566. ac97c_stat = au_readl(AC97C_STATUS);
  567. #ifdef AU1000_VERBOSE_DEBUG
  568. if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
  569. dbg("AC97C status = 0x%08x", ac97c_stat);
  570. #endif
  571. if ((buff_done = get_dma_buffer_done(dac->dmanr)) == 0) {
  572. /* fastpath out, to ease interrupt sharing */
  573. return IRQ_HANDLED;
  574. }
  575. spin_lock(&s->lock);
  576. if (buff_done != (DMA_D0 | DMA_D1)) {
  577. dac->nextOut += dac->dma_fragsize;
  578. if (dac->nextOut >= dac->rawbuf + dac->dmasize)
  579. dac->nextOut -= dac->dmasize;
  580. /* update playback pointers */
  581. newptr = virt_to_phys(dac->nextOut) + dac->dma_fragsize;
  582. if (newptr >= dac->dmaaddr + dac->dmasize)
  583. newptr -= dac->dmasize;
  584. dac->count -= dac->dma_fragsize;
  585. dac->total_bytes += dac->dma_fragsize;
  586. if (dac->count <= 0) {
  587. #ifdef AU1000_VERBOSE_DEBUG
  588. dbg("dac underrun");
  589. #endif
  590. spin_unlock(&s->lock);
  591. stop_dac(s);
  592. spin_lock(&s->lock);
  593. dac->count = 0;
  594. dac->nextIn = dac->nextOut;
  595. } else if (buff_done == DMA_D0) {
  596. clear_dma_done0(dac->dmanr); // clear DMA done bit
  597. set_dma_count0(dac->dmanr, dac->dma_fragsize>>1);
  598. set_dma_addr0(dac->dmanr, newptr);
  599. enable_dma_buffer0(dac->dmanr); // reenable
  600. } else {
  601. clear_dma_done1(dac->dmanr); // clear DMA done bit
  602. set_dma_count1(dac->dmanr, dac->dma_fragsize>>1);
  603. set_dma_addr1(dac->dmanr, newptr);
  604. enable_dma_buffer1(dac->dmanr); // reenable
  605. }
  606. } else {
  607. // both done bits set, we missed an interrupt
  608. spin_unlock(&s->lock);
  609. stop_dac(s);
  610. spin_lock(&s->lock);
  611. dac->nextOut += 2*dac->dma_fragsize;
  612. if (dac->nextOut >= dac->rawbuf + dac->dmasize)
  613. dac->nextOut -= dac->dmasize;
  614. dac->count -= 2*dac->dma_fragsize;
  615. dac->total_bytes += 2*dac->dma_fragsize;
  616. if (dac->count > 0) {
  617. spin_unlock(&s->lock);
  618. start_dac(s);
  619. spin_lock(&s->lock);
  620. }
  621. }
  622. /* wake up anybody listening */
  623. if (waitqueue_active(&dac->wait))
  624. wake_up(&dac->wait);
  625. spin_unlock(&s->lock);
  626. return IRQ_HANDLED;
  627. }
  628. static irqreturn_t adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  629. {
  630. struct au1000_state *s = (struct au1000_state *) dev_id;
  631. struct dmabuf *adc = &s->dma_adc;
  632. unsigned long newptr;
  633. u32 ac97c_stat, buff_done;
  634. ac97c_stat = au_readl(AC97C_STATUS);
  635. #ifdef AU1000_VERBOSE_DEBUG
  636. if (ac97c_stat & (AC97C_RU | AC97C_RO))
  637. dbg("AC97C status = 0x%08x", ac97c_stat);
  638. #endif
  639. if ((buff_done = get_dma_buffer_done(adc->dmanr)) == 0) {
  640. /* fastpath out, to ease interrupt sharing */
  641. return IRQ_HANDLED;
  642. }
  643. spin_lock(&s->lock);
  644. if (buff_done != (DMA_D0 | DMA_D1)) {
  645. if (adc->count + adc->dma_fragsize > adc->dmasize) {
  646. // Overrun. Stop ADC and log the error
  647. spin_unlock(&s->lock);
  648. stop_adc(s);
  649. adc->error++;
  650. err("adc overrun");
  651. return IRQ_NONE;
  652. }
  653. adc->nextIn += adc->dma_fragsize;
  654. if (adc->nextIn >= adc->rawbuf + adc->dmasize)
  655. adc->nextIn -= adc->dmasize;
  656. /* update capture pointers */
  657. newptr = virt_to_phys(adc->nextIn) + adc->dma_fragsize;
  658. if (newptr >= adc->dmaaddr + adc->dmasize)
  659. newptr -= adc->dmasize;
  660. adc->count += adc->dma_fragsize;
  661. adc->total_bytes += adc->dma_fragsize;
  662. if (buff_done == DMA_D0) {
  663. clear_dma_done0(adc->dmanr); // clear DMA done bit
  664. set_dma_count0(adc->dmanr, adc->dma_fragsize>>1);
  665. set_dma_addr0(adc->dmanr, newptr);
  666. enable_dma_buffer0(adc->dmanr); // reenable
  667. } else {
  668. clear_dma_done1(adc->dmanr); // clear DMA done bit
  669. set_dma_count1(adc->dmanr, adc->dma_fragsize>>1);
  670. set_dma_addr1(adc->dmanr, newptr);
  671. enable_dma_buffer1(adc->dmanr); // reenable
  672. }
  673. } else {
  674. // both done bits set, we missed an interrupt
  675. spin_unlock(&s->lock);
  676. stop_adc(s);
  677. spin_lock(&s->lock);
  678. if (adc->count + 2*adc->dma_fragsize > adc->dmasize) {
  679. // Overrun. Log the error
  680. adc->error++;
  681. err("adc overrun");
  682. spin_unlock(&s->lock);
  683. return IRQ_NONE;
  684. }
  685. adc->nextIn += 2*adc->dma_fragsize;
  686. if (adc->nextIn >= adc->rawbuf + adc->dmasize)
  687. adc->nextIn -= adc->dmasize;
  688. adc->count += 2*adc->dma_fragsize;
  689. adc->total_bytes += 2*adc->dma_fragsize;
  690. spin_unlock(&s->lock);
  691. start_adc(s);
  692. spin_lock(&s->lock);
  693. }
  694. /* wake up anybody listening */
  695. if (waitqueue_active(&adc->wait))
  696. wake_up(&adc->wait);
  697. spin_unlock(&s->lock);
  698. return IRQ_HANDLED;
  699. }
  700. /* --------------------------------------------------------------------- */
  701. static loff_t au1000_llseek(struct file *file, loff_t offset, int origin)
  702. {
  703. return -ESPIPE;
  704. }
  705. static int au1000_open_mixdev(struct inode *inode, struct file *file)
  706. {
  707. file->private_data = &au1000_state;
  708. return nonseekable_open(inode, file);
  709. }
  710. static int au1000_release_mixdev(struct inode *inode, struct file *file)
  711. {
  712. return 0;
  713. }
  714. static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  715. unsigned long arg)
  716. {
  717. return codec->mixer_ioctl(codec, cmd, arg);
  718. }
  719. static int au1000_ioctl_mixdev(struct inode *inode, struct file *file,
  720. unsigned int cmd, unsigned long arg)
  721. {
  722. struct au1000_state *s = (struct au1000_state *)file->private_data;
  723. struct ac97_codec *codec = &s->codec;
  724. return mixdev_ioctl(codec, cmd, arg);
  725. }
  726. static /*const */ struct file_operations au1000_mixer_fops = {
  727. .owner = THIS_MODULE,
  728. .llseek = au1000_llseek,
  729. .ioctl = au1000_ioctl_mixdev,
  730. .open = au1000_open_mixdev,
  731. .release = au1000_release_mixdev,
  732. };
  733. /* --------------------------------------------------------------------- */
  734. static int drain_dac(struct au1000_state *s, int nonblock)
  735. {
  736. unsigned long flags;
  737. int count, tmo;
  738. if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
  739. return 0;
  740. for (;;) {
  741. spin_lock_irqsave(&s->lock, flags);
  742. count = s->dma_dac.count;
  743. spin_unlock_irqrestore(&s->lock, flags);
  744. if (count <= 0)
  745. break;
  746. if (signal_pending(current))
  747. break;
  748. if (nonblock)
  749. return -EBUSY;
  750. tmo = 1000 * count / (s->no_vra ?
  751. 48000 : s->dma_dac.sample_rate);
  752. tmo /= s->dma_dac.dma_bytes_per_sample;
  753. au1000_delay(tmo);
  754. }
  755. if (signal_pending(current))
  756. return -ERESTARTSYS;
  757. return 0;
  758. }
  759. /* --------------------------------------------------------------------- */
  760. static inline u8 S16_TO_U8(s16 ch)
  761. {
  762. return (u8) (ch >> 8) + 0x80;
  763. }
  764. static inline s16 U8_TO_S16(u8 ch)
  765. {
  766. return (s16) (ch - 0x80) << 8;
  767. }
  768. /*
  769. * Translates user samples to dma buffer suitable for AC'97 DAC data:
  770. * If mono, copy left channel to right channel in dma buffer.
  771. * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
  772. * If interpolating (no VRA), duplicate every audio frame src_factor times.
  773. */
  774. static int translate_from_user(struct dmabuf *db,
  775. char* dmabuf,
  776. char* userbuf,
  777. int dmacount)
  778. {
  779. int sample, i;
  780. int interp_bytes_per_sample;
  781. int num_samples;
  782. int mono = (db->num_channels == 1);
  783. char usersample[12];
  784. s16 ch, dmasample[6];
  785. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  786. // no translation necessary, just copy
  787. if (copy_from_user(dmabuf, userbuf, dmacount))
  788. return -EFAULT;
  789. return dmacount;
  790. }
  791. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  792. num_samples = dmacount / interp_bytes_per_sample;
  793. for (sample = 0; sample < num_samples; sample++) {
  794. if (copy_from_user(usersample, userbuf,
  795. db->user_bytes_per_sample)) {
  796. dbg("%s: fault", __FUNCTION__);
  797. return -EFAULT;
  798. }
  799. for (i = 0; i < db->num_channels; i++) {
  800. if (db->sample_size == 8)
  801. ch = U8_TO_S16(usersample[i]);
  802. else
  803. ch = *((s16 *) (&usersample[i * 2]));
  804. dmasample[i] = ch;
  805. if (mono)
  806. dmasample[i + 1] = ch; // right channel
  807. }
  808. // duplicate every audio frame src_factor times
  809. for (i = 0; i < db->src_factor; i++)
  810. memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
  811. userbuf += db->user_bytes_per_sample;
  812. dmabuf += interp_bytes_per_sample;
  813. }
  814. return num_samples * interp_bytes_per_sample;
  815. }
  816. /*
  817. * Translates AC'97 ADC samples to user buffer:
  818. * If mono, send only left channel to user buffer.
  819. * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
  820. * If decimating (no VRA), skip over src_factor audio frames.
  821. */
  822. static int translate_to_user(struct dmabuf *db,
  823. char* userbuf,
  824. char* dmabuf,
  825. int dmacount)
  826. {
  827. int sample, i;
  828. int interp_bytes_per_sample;
  829. int num_samples;
  830. int mono = (db->num_channels == 1);
  831. char usersample[12];
  832. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  833. // no translation necessary, just copy
  834. if (copy_to_user(userbuf, dmabuf, dmacount))
  835. return -EFAULT;
  836. return dmacount;
  837. }
  838. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  839. num_samples = dmacount / interp_bytes_per_sample;
  840. for (sample = 0; sample < num_samples; sample++) {
  841. for (i = 0; i < db->num_channels; i++) {
  842. if (db->sample_size == 8)
  843. usersample[i] =
  844. S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
  845. else
  846. *((s16 *) (&usersample[i * 2])) =
  847. *((s16 *) (&dmabuf[i * 2]));
  848. }
  849. if (copy_to_user(userbuf, usersample,
  850. db->user_bytes_per_sample)) {
  851. dbg("%s: fault", __FUNCTION__);
  852. return -EFAULT;
  853. }
  854. userbuf += db->user_bytes_per_sample;
  855. dmabuf += interp_bytes_per_sample;
  856. }
  857. return num_samples * interp_bytes_per_sample;
  858. }
  859. /*
  860. * Copy audio data to/from user buffer from/to dma buffer, taking care
  861. * that we wrap when reading/writing the dma buffer. Returns actual byte
  862. * count written to or read from the dma buffer.
  863. */
  864. static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
  865. int count, int to_user)
  866. {
  867. char *bufptr = to_user ? db->nextOut : db->nextIn;
  868. char *bufend = db->rawbuf + db->dmasize;
  869. int cnt, ret;
  870. if (bufptr + count > bufend) {
  871. int partial = (int) (bufend - bufptr);
  872. if (to_user) {
  873. if ((cnt = translate_to_user(db, userbuf,
  874. bufptr, partial)) < 0)
  875. return cnt;
  876. ret = cnt;
  877. if ((cnt = translate_to_user(db, userbuf + partial,
  878. db->rawbuf,
  879. count - partial)) < 0)
  880. return cnt;
  881. ret += cnt;
  882. } else {
  883. if ((cnt = translate_from_user(db, bufptr, userbuf,
  884. partial)) < 0)
  885. return cnt;
  886. ret = cnt;
  887. if ((cnt = translate_from_user(db, db->rawbuf,
  888. userbuf + partial,
  889. count - partial)) < 0)
  890. return cnt;
  891. ret += cnt;
  892. }
  893. } else {
  894. if (to_user)
  895. ret = translate_to_user(db, userbuf, bufptr, count);
  896. else
  897. ret = translate_from_user(db, bufptr, userbuf, count);
  898. }
  899. return ret;
  900. }
  901. static ssize_t au1000_read(struct file *file, char *buffer,
  902. size_t count, loff_t *ppos)
  903. {
  904. struct au1000_state *s = (struct au1000_state *)file->private_data;
  905. struct dmabuf *db = &s->dma_adc;
  906. DECLARE_WAITQUEUE(wait, current);
  907. ssize_t ret;
  908. unsigned long flags;
  909. int cnt, usercnt, avail;
  910. if (db->mapped)
  911. return -ENXIO;
  912. if (!access_ok(VERIFY_WRITE, buffer, count))
  913. return -EFAULT;
  914. ret = 0;
  915. count *= db->cnt_factor;
  916. down(&s->sem);
  917. add_wait_queue(&db->wait, &wait);
  918. while (count > 0) {
  919. // wait for samples in ADC dma buffer
  920. do {
  921. if (db->stopped)
  922. start_adc(s);
  923. spin_lock_irqsave(&s->lock, flags);
  924. avail = db->count;
  925. if (avail <= 0)
  926. __set_current_state(TASK_INTERRUPTIBLE);
  927. spin_unlock_irqrestore(&s->lock, flags);
  928. if (avail <= 0) {
  929. if (file->f_flags & O_NONBLOCK) {
  930. if (!ret)
  931. ret = -EAGAIN;
  932. goto out;
  933. }
  934. up(&s->sem);
  935. schedule();
  936. if (signal_pending(current)) {
  937. if (!ret)
  938. ret = -ERESTARTSYS;
  939. goto out2;
  940. }
  941. down(&s->sem);
  942. }
  943. } while (avail <= 0);
  944. // copy from nextOut to user
  945. if ((cnt = copy_dmabuf_user(db, buffer,
  946. count > avail ?
  947. avail : count, 1)) < 0) {
  948. if (!ret)
  949. ret = -EFAULT;
  950. goto out;
  951. }
  952. spin_lock_irqsave(&s->lock, flags);
  953. db->count -= cnt;
  954. db->nextOut += cnt;
  955. if (db->nextOut >= db->rawbuf + db->dmasize)
  956. db->nextOut -= db->dmasize;
  957. spin_unlock_irqrestore(&s->lock, flags);
  958. count -= cnt;
  959. usercnt = cnt / db->cnt_factor;
  960. buffer += usercnt;
  961. ret += usercnt;
  962. } // while (count > 0)
  963. out:
  964. up(&s->sem);
  965. out2:
  966. remove_wait_queue(&db->wait, &wait);
  967. set_current_state(TASK_RUNNING);
  968. return ret;
  969. }
  970. static ssize_t au1000_write(struct file *file, const char *buffer,
  971. size_t count, loff_t * ppos)
  972. {
  973. struct au1000_state *s = (struct au1000_state *)file->private_data;
  974. struct dmabuf *db = &s->dma_dac;
  975. DECLARE_WAITQUEUE(wait, current);
  976. ssize_t ret = 0;
  977. unsigned long flags;
  978. int cnt, usercnt, avail;
  979. #ifdef AU1000_VERBOSE_DEBUG
  980. dbg("write: count=%d", count);
  981. #endif
  982. if (db->mapped)
  983. return -ENXIO;
  984. if (!access_ok(VERIFY_READ, buffer, count))
  985. return -EFAULT;
  986. count *= db->cnt_factor;
  987. down(&s->sem);
  988. add_wait_queue(&db->wait, &wait);
  989. while (count > 0) {
  990. // wait for space in playback buffer
  991. do {
  992. spin_lock_irqsave(&s->lock, flags);
  993. avail = (int) db->dmasize - db->count;
  994. if (avail <= 0)
  995. __set_current_state(TASK_INTERRUPTIBLE);
  996. spin_unlock_irqrestore(&s->lock, flags);
  997. if (avail <= 0) {
  998. if (file->f_flags & O_NONBLOCK) {
  999. if (!ret)
  1000. ret = -EAGAIN;
  1001. goto out;
  1002. }
  1003. up(&s->sem);
  1004. schedule();
  1005. if (signal_pending(current)) {
  1006. if (!ret)
  1007. ret = -ERESTARTSYS;
  1008. goto out2;
  1009. }
  1010. down(&s->sem);
  1011. }
  1012. } while (avail <= 0);
  1013. // copy from user to nextIn
  1014. if ((cnt = copy_dmabuf_user(db, (char *) buffer,
  1015. count > avail ?
  1016. avail : count, 0)) < 0) {
  1017. if (!ret)
  1018. ret = -EFAULT;
  1019. goto out;
  1020. }
  1021. spin_lock_irqsave(&s->lock, flags);
  1022. db->count += cnt;
  1023. db->nextIn += cnt;
  1024. if (db->nextIn >= db->rawbuf + db->dmasize)
  1025. db->nextIn -= db->dmasize;
  1026. spin_unlock_irqrestore(&s->lock, flags);
  1027. if (db->stopped)
  1028. start_dac(s);
  1029. count -= cnt;
  1030. usercnt = cnt / db->cnt_factor;
  1031. buffer += usercnt;
  1032. ret += usercnt;
  1033. } // while (count > 0)
  1034. out:
  1035. up(&s->sem);
  1036. out2:
  1037. remove_wait_queue(&db->wait, &wait);
  1038. set_current_state(TASK_RUNNING);
  1039. return ret;
  1040. }
  1041. /* No kernel lock - we have our own spinlock */
  1042. static unsigned int au1000_poll(struct file *file,
  1043. struct poll_table_struct *wait)
  1044. {
  1045. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1046. unsigned long flags;
  1047. unsigned int mask = 0;
  1048. if (file->f_mode & FMODE_WRITE) {
  1049. if (!s->dma_dac.ready)
  1050. return 0;
  1051. poll_wait(file, &s->dma_dac.wait, wait);
  1052. }
  1053. if (file->f_mode & FMODE_READ) {
  1054. if (!s->dma_adc.ready)
  1055. return 0;
  1056. poll_wait(file, &s->dma_adc.wait, wait);
  1057. }
  1058. spin_lock_irqsave(&s->lock, flags);
  1059. if (file->f_mode & FMODE_READ) {
  1060. if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
  1061. mask |= POLLIN | POLLRDNORM;
  1062. }
  1063. if (file->f_mode & FMODE_WRITE) {
  1064. if (s->dma_dac.mapped) {
  1065. if (s->dma_dac.count >=
  1066. (signed)s->dma_dac.dma_fragsize)
  1067. mask |= POLLOUT | POLLWRNORM;
  1068. } else {
  1069. if ((signed) s->dma_dac.dmasize >=
  1070. s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
  1071. mask |= POLLOUT | POLLWRNORM;
  1072. }
  1073. }
  1074. spin_unlock_irqrestore(&s->lock, flags);
  1075. return mask;
  1076. }
  1077. static int au1000_mmap(struct file *file, struct vm_area_struct *vma)
  1078. {
  1079. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1080. struct dmabuf *db;
  1081. unsigned long size;
  1082. int ret = 0;
  1083. dbg("%s", __FUNCTION__);
  1084. lock_kernel();
  1085. down(&s->sem);
  1086. if (vma->vm_flags & VM_WRITE)
  1087. db = &s->dma_dac;
  1088. else if (vma->vm_flags & VM_READ)
  1089. db = &s->dma_adc;
  1090. else {
  1091. ret = -EINVAL;
  1092. goto out;
  1093. }
  1094. if (vma->vm_pgoff != 0) {
  1095. ret = -EINVAL;
  1096. goto out;
  1097. }
  1098. size = vma->vm_end - vma->vm_start;
  1099. if (size > (PAGE_SIZE << db->buforder)) {
  1100. ret = -EINVAL;
  1101. goto out;
  1102. }
  1103. if (remap_pfn_range(vma, vma->vm_start, virt_to_phys(db->rawbuf),
  1104. size, vma->vm_page_prot)) {
  1105. ret = -EAGAIN;
  1106. goto out;
  1107. }
  1108. vma->vm_flags &= ~VM_IO;
  1109. db->mapped = 1;
  1110. out:
  1111. up(&s->sem);
  1112. unlock_kernel();
  1113. return ret;
  1114. }
  1115. #ifdef AU1000_VERBOSE_DEBUG
  1116. static struct ioctl_str_t {
  1117. unsigned int cmd;
  1118. const char *str;
  1119. } ioctl_str[] = {
  1120. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1121. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1122. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1123. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1124. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1125. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1126. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1127. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1128. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1129. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1130. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1131. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1132. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1133. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1134. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1135. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1136. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1137. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1138. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1139. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1140. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1141. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1142. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1143. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1144. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1145. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1146. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1147. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1148. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1149. {OSS_GETVERSION, "OSS_GETVERSION"},
  1150. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1151. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1152. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1153. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1154. };
  1155. #endif
  1156. // Need to hold a spin-lock before calling this!
  1157. static int dma_count_done(struct dmabuf *db)
  1158. {
  1159. if (db->stopped)
  1160. return 0;
  1161. return db->dma_fragsize - get_dma_residue(db->dmanr);
  1162. }
  1163. static int au1000_ioctl(struct inode *inode, struct file *file,
  1164. unsigned int cmd, unsigned long arg)
  1165. {
  1166. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1167. unsigned long flags;
  1168. audio_buf_info abinfo;
  1169. count_info cinfo;
  1170. int count;
  1171. int val, mapped, ret, diff;
  1172. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1173. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1174. #ifdef AU1000_VERBOSE_DEBUG
  1175. for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
  1176. if (ioctl_str[count].cmd == cmd)
  1177. break;
  1178. }
  1179. if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
  1180. dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
  1181. else
  1182. dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
  1183. #endif
  1184. switch (cmd) {
  1185. case OSS_GETVERSION:
  1186. return put_user(SOUND_VERSION, (int *) arg);
  1187. case SNDCTL_DSP_SYNC:
  1188. if (file->f_mode & FMODE_WRITE)
  1189. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1190. return 0;
  1191. case SNDCTL_DSP_SETDUPLEX:
  1192. return 0;
  1193. case SNDCTL_DSP_GETCAPS:
  1194. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1195. DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
  1196. case SNDCTL_DSP_RESET:
  1197. if (file->f_mode & FMODE_WRITE) {
  1198. stop_dac(s);
  1199. synchronize_irq();
  1200. s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1201. s->dma_dac.nextIn = s->dma_dac.nextOut =
  1202. s->dma_dac.rawbuf;
  1203. }
  1204. if (file->f_mode & FMODE_READ) {
  1205. stop_adc(s);
  1206. synchronize_irq();
  1207. s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1208. s->dma_adc.nextIn = s->dma_adc.nextOut =
  1209. s->dma_adc.rawbuf;
  1210. }
  1211. return 0;
  1212. case SNDCTL_DSP_SPEED:
  1213. if (get_user(val, (int *) arg))
  1214. return -EFAULT;
  1215. if (val >= 0) {
  1216. if (file->f_mode & FMODE_READ) {
  1217. stop_adc(s);
  1218. set_adc_rate(s, val);
  1219. }
  1220. if (file->f_mode & FMODE_WRITE) {
  1221. stop_dac(s);
  1222. set_dac_rate(s, val);
  1223. }
  1224. if (s->open_mode & FMODE_READ)
  1225. if ((ret = prog_dmabuf_adc(s)))
  1226. return ret;
  1227. if (s->open_mode & FMODE_WRITE)
  1228. if ((ret = prog_dmabuf_dac(s)))
  1229. return ret;
  1230. }
  1231. return put_user((file->f_mode & FMODE_READ) ?
  1232. s->dma_adc.sample_rate :
  1233. s->dma_dac.sample_rate,
  1234. (int *)arg);
  1235. case SNDCTL_DSP_STEREO:
  1236. if (get_user(val, (int *) arg))
  1237. return -EFAULT;
  1238. if (file->f_mode & FMODE_READ) {
  1239. stop_adc(s);
  1240. s->dma_adc.num_channels = val ? 2 : 1;
  1241. if ((ret = prog_dmabuf_adc(s)))
  1242. return ret;
  1243. }
  1244. if (file->f_mode & FMODE_WRITE) {
  1245. stop_dac(s);
  1246. s->dma_dac.num_channels = val ? 2 : 1;
  1247. if (s->codec_ext_caps & AC97_EXT_DACS) {
  1248. // disable surround and center/lfe in AC'97
  1249. u16 ext_stat = rdcodec(&s->codec,
  1250. AC97_EXTENDED_STATUS);
  1251. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  1252. ext_stat | (AC97_EXTSTAT_PRI |
  1253. AC97_EXTSTAT_PRJ |
  1254. AC97_EXTSTAT_PRK));
  1255. }
  1256. if ((ret = prog_dmabuf_dac(s)))
  1257. return ret;
  1258. }
  1259. return 0;
  1260. case SNDCTL_DSP_CHANNELS:
  1261. if (get_user(val, (int *) arg))
  1262. return -EFAULT;
  1263. if (val != 0) {
  1264. if (file->f_mode & FMODE_READ) {
  1265. if (val < 0 || val > 2)
  1266. return -EINVAL;
  1267. stop_adc(s);
  1268. s->dma_adc.num_channels = val;
  1269. if ((ret = prog_dmabuf_adc(s)))
  1270. return ret;
  1271. }
  1272. if (file->f_mode & FMODE_WRITE) {
  1273. switch (val) {
  1274. case 1:
  1275. case 2:
  1276. break;
  1277. case 3:
  1278. case 5:
  1279. return -EINVAL;
  1280. case 4:
  1281. if (!(s->codec_ext_caps &
  1282. AC97_EXTID_SDAC))
  1283. return -EINVAL;
  1284. break;
  1285. case 6:
  1286. if ((s->codec_ext_caps &
  1287. AC97_EXT_DACS) != AC97_EXT_DACS)
  1288. return -EINVAL;
  1289. break;
  1290. default:
  1291. return -EINVAL;
  1292. }
  1293. stop_dac(s);
  1294. if (val <= 2 &&
  1295. (s->codec_ext_caps & AC97_EXT_DACS)) {
  1296. // disable surround and center/lfe
  1297. // channels in AC'97
  1298. u16 ext_stat =
  1299. rdcodec(&s->codec,
  1300. AC97_EXTENDED_STATUS);
  1301. wrcodec(&s->codec,
  1302. AC97_EXTENDED_STATUS,
  1303. ext_stat | (AC97_EXTSTAT_PRI |
  1304. AC97_EXTSTAT_PRJ |
  1305. AC97_EXTSTAT_PRK));
  1306. } else if (val >= 4) {
  1307. // enable surround, center/lfe
  1308. // channels in AC'97
  1309. u16 ext_stat =
  1310. rdcodec(&s->codec,
  1311. AC97_EXTENDED_STATUS);
  1312. ext_stat &= ~AC97_EXTSTAT_PRJ;
  1313. if (val == 6)
  1314. ext_stat &=
  1315. ~(AC97_EXTSTAT_PRI |
  1316. AC97_EXTSTAT_PRK);
  1317. wrcodec(&s->codec,
  1318. AC97_EXTENDED_STATUS,
  1319. ext_stat);
  1320. }
  1321. s->dma_dac.num_channels = val;
  1322. if ((ret = prog_dmabuf_dac(s)))
  1323. return ret;
  1324. }
  1325. }
  1326. return put_user(val, (int *) arg);
  1327. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1328. return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
  1329. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
  1330. if (get_user(val, (int *) arg))
  1331. return -EFAULT;
  1332. if (val != AFMT_QUERY) {
  1333. if (file->f_mode & FMODE_READ) {
  1334. stop_adc(s);
  1335. if (val == AFMT_S16_LE)
  1336. s->dma_adc.sample_size = 16;
  1337. else {
  1338. val = AFMT_U8;
  1339. s->dma_adc.sample_size = 8;
  1340. }
  1341. if ((ret = prog_dmabuf_adc(s)))
  1342. return ret;
  1343. }
  1344. if (file->f_mode & FMODE_WRITE) {
  1345. stop_dac(s);
  1346. if (val == AFMT_S16_LE)
  1347. s->dma_dac.sample_size = 16;
  1348. else {
  1349. val = AFMT_U8;
  1350. s->dma_dac.sample_size = 8;
  1351. }
  1352. if ((ret = prog_dmabuf_dac(s)))
  1353. return ret;
  1354. }
  1355. } else {
  1356. if (file->f_mode & FMODE_READ)
  1357. val = (s->dma_adc.sample_size == 16) ?
  1358. AFMT_S16_LE : AFMT_U8;
  1359. else
  1360. val = (s->dma_dac.sample_size == 16) ?
  1361. AFMT_S16_LE : AFMT_U8;
  1362. }
  1363. return put_user(val, (int *) arg);
  1364. case SNDCTL_DSP_POST:
  1365. return 0;
  1366. case SNDCTL_DSP_GETTRIGGER:
  1367. val = 0;
  1368. spin_lock_irqsave(&s->lock, flags);
  1369. if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
  1370. val |= PCM_ENABLE_INPUT;
  1371. if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
  1372. val |= PCM_ENABLE_OUTPUT;
  1373. spin_unlock_irqrestore(&s->lock, flags);
  1374. return put_user(val, (int *) arg);
  1375. case SNDCTL_DSP_SETTRIGGER:
  1376. if (get_user(val, (int *) arg))
  1377. return -EFAULT;
  1378. if (file->f_mode & FMODE_READ) {
  1379. if (val & PCM_ENABLE_INPUT)
  1380. start_adc(s);
  1381. else
  1382. stop_adc(s);
  1383. }
  1384. if (file->f_mode & FMODE_WRITE) {
  1385. if (val & PCM_ENABLE_OUTPUT)
  1386. start_dac(s);
  1387. else
  1388. stop_dac(s);
  1389. }
  1390. return 0;
  1391. case SNDCTL_DSP_GETOSPACE:
  1392. if (!(file->f_mode & FMODE_WRITE))
  1393. return -EINVAL;
  1394. abinfo.fragsize = s->dma_dac.fragsize;
  1395. spin_lock_irqsave(&s->lock, flags);
  1396. count = s->dma_dac.count;
  1397. count -= dma_count_done(&s->dma_dac);
  1398. spin_unlock_irqrestore(&s->lock, flags);
  1399. if (count < 0)
  1400. count = 0;
  1401. abinfo.bytes = (s->dma_dac.dmasize - count) /
  1402. s->dma_dac.cnt_factor;
  1403. abinfo.fragstotal = s->dma_dac.numfrag;
  1404. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1405. #ifdef AU1000_VERBOSE_DEBUG
  1406. dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
  1407. #endif
  1408. return copy_to_user((void *) arg, &abinfo,
  1409. sizeof(abinfo)) ? -EFAULT : 0;
  1410. case SNDCTL_DSP_GETISPACE:
  1411. if (!(file->f_mode & FMODE_READ))
  1412. return -EINVAL;
  1413. abinfo.fragsize = s->dma_adc.fragsize;
  1414. spin_lock_irqsave(&s->lock, flags);
  1415. count = s->dma_adc.count;
  1416. count += dma_count_done(&s->dma_adc);
  1417. spin_unlock_irqrestore(&s->lock, flags);
  1418. if (count < 0)
  1419. count = 0;
  1420. abinfo.bytes = count / s->dma_adc.cnt_factor;
  1421. abinfo.fragstotal = s->dma_adc.numfrag;
  1422. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1423. return copy_to_user((void *) arg, &abinfo,
  1424. sizeof(abinfo)) ? -EFAULT : 0;
  1425. case SNDCTL_DSP_NONBLOCK:
  1426. file->f_flags |= O_NONBLOCK;
  1427. return 0;
  1428. case SNDCTL_DSP_GETODELAY:
  1429. if (!(file->f_mode & FMODE_WRITE))
  1430. return -EINVAL;
  1431. spin_lock_irqsave(&s->lock, flags);
  1432. count = s->dma_dac.count;
  1433. count -= dma_count_done(&s->dma_dac);
  1434. spin_unlock_irqrestore(&s->lock, flags);
  1435. if (count < 0)
  1436. count = 0;
  1437. count /= s->dma_dac.cnt_factor;
  1438. return put_user(count, (int *) arg);
  1439. case SNDCTL_DSP_GETIPTR:
  1440. if (!(file->f_mode & FMODE_READ))
  1441. return -EINVAL;
  1442. spin_lock_irqsave(&s->lock, flags);
  1443. cinfo.bytes = s->dma_adc.total_bytes;
  1444. count = s->dma_adc.count;
  1445. if (!s->dma_adc.stopped) {
  1446. diff = dma_count_done(&s->dma_adc);
  1447. count += diff;
  1448. cinfo.bytes += diff;
  1449. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
  1450. s->dma_adc.dmaaddr;
  1451. } else
  1452. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
  1453. s->dma_adc.dmaaddr;
  1454. if (s->dma_adc.mapped)
  1455. s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
  1456. spin_unlock_irqrestore(&s->lock, flags);
  1457. if (count < 0)
  1458. count = 0;
  1459. cinfo.blocks = count >> s->dma_adc.fragshift;
  1460. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
  1461. case SNDCTL_DSP_GETOPTR:
  1462. if (!(file->f_mode & FMODE_READ))
  1463. return -EINVAL;
  1464. spin_lock_irqsave(&s->lock, flags);
  1465. cinfo.bytes = s->dma_dac.total_bytes;
  1466. count = s->dma_dac.count;
  1467. if (!s->dma_dac.stopped) {
  1468. diff = dma_count_done(&s->dma_dac);
  1469. count -= diff;
  1470. cinfo.bytes += diff;
  1471. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
  1472. s->dma_dac.dmaaddr;
  1473. } else
  1474. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
  1475. s->dma_dac.dmaaddr;
  1476. if (s->dma_dac.mapped)
  1477. s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
  1478. spin_unlock_irqrestore(&s->lock, flags);
  1479. if (count < 0)
  1480. count = 0;
  1481. cinfo.blocks = count >> s->dma_dac.fragshift;
  1482. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
  1483. case SNDCTL_DSP_GETBLKSIZE:
  1484. if (file->f_mode & FMODE_WRITE)
  1485. return put_user(s->dma_dac.fragsize, (int *) arg);
  1486. else
  1487. return put_user(s->dma_adc.fragsize, (int *) arg);
  1488. case SNDCTL_DSP_SETFRAGMENT:
  1489. if (get_user(val, (int *) arg))
  1490. return -EFAULT;
  1491. if (file->f_mode & FMODE_READ) {
  1492. stop_adc(s);
  1493. s->dma_adc.ossfragshift = val & 0xffff;
  1494. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1495. if (s->dma_adc.ossfragshift < 4)
  1496. s->dma_adc.ossfragshift = 4;
  1497. if (s->dma_adc.ossfragshift > 15)
  1498. s->dma_adc.ossfragshift = 15;
  1499. if (s->dma_adc.ossmaxfrags < 4)
  1500. s->dma_adc.ossmaxfrags = 4;
  1501. if ((ret = prog_dmabuf_adc(s)))
  1502. return ret;
  1503. }
  1504. if (file->f_mode & FMODE_WRITE) {
  1505. stop_dac(s);
  1506. s->dma_dac.ossfragshift = val & 0xffff;
  1507. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1508. if (s->dma_dac.ossfragshift < 4)
  1509. s->dma_dac.ossfragshift = 4;
  1510. if (s->dma_dac.ossfragshift > 15)
  1511. s->dma_dac.ossfragshift = 15;
  1512. if (s->dma_dac.ossmaxfrags < 4)
  1513. s->dma_dac.ossmaxfrags = 4;
  1514. if ((ret = prog_dmabuf_dac(s)))
  1515. return ret;
  1516. }
  1517. return 0;
  1518. case SNDCTL_DSP_SUBDIVIDE:
  1519. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1520. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1521. return -EINVAL;
  1522. if (get_user(val, (int *) arg))
  1523. return -EFAULT;
  1524. if (val != 1 && val != 2 && val != 4)
  1525. return -EINVAL;
  1526. if (file->f_mode & FMODE_READ) {
  1527. stop_adc(s);
  1528. s->dma_adc.subdivision = val;
  1529. if ((ret = prog_dmabuf_adc(s)))
  1530. return ret;
  1531. }
  1532. if (file->f_mode & FMODE_WRITE) {
  1533. stop_dac(s);
  1534. s->dma_dac.subdivision = val;
  1535. if ((ret = prog_dmabuf_dac(s)))
  1536. return ret;
  1537. }
  1538. return 0;
  1539. case SOUND_PCM_READ_RATE:
  1540. return put_user((file->f_mode & FMODE_READ) ?
  1541. s->dma_adc.sample_rate :
  1542. s->dma_dac.sample_rate,
  1543. (int *)arg);
  1544. case SOUND_PCM_READ_CHANNELS:
  1545. if (file->f_mode & FMODE_READ)
  1546. return put_user(s->dma_adc.num_channels, (int *)arg);
  1547. else
  1548. return put_user(s->dma_dac.num_channels, (int *)arg);
  1549. case SOUND_PCM_READ_BITS:
  1550. if (file->f_mode & FMODE_READ)
  1551. return put_user(s->dma_adc.sample_size, (int *)arg);
  1552. else
  1553. return put_user(s->dma_dac.sample_size, (int *)arg);
  1554. case SOUND_PCM_WRITE_FILTER:
  1555. case SNDCTL_DSP_SETSYNCRO:
  1556. case SOUND_PCM_READ_FILTER:
  1557. return -EINVAL;
  1558. }
  1559. return mixdev_ioctl(&s->codec, cmd, arg);
  1560. }
  1561. static int au1000_open(struct inode *inode, struct file *file)
  1562. {
  1563. int minor = iminor(inode);
  1564. DECLARE_WAITQUEUE(wait, current);
  1565. struct au1000_state *s = &au1000_state;
  1566. int ret;
  1567. #ifdef AU1000_VERBOSE_DEBUG
  1568. if (file->f_flags & O_NONBLOCK)
  1569. dbg("%s: non-blocking", __FUNCTION__);
  1570. else
  1571. dbg("%s: blocking", __FUNCTION__);
  1572. #endif
  1573. file->private_data = s;
  1574. /* wait for device to become free */
  1575. down(&s->open_sem);
  1576. while (s->open_mode & file->f_mode) {
  1577. if (file->f_flags & O_NONBLOCK) {
  1578. up(&s->open_sem);
  1579. return -EBUSY;
  1580. }
  1581. add_wait_queue(&s->open_wait, &wait);
  1582. __set_current_state(TASK_INTERRUPTIBLE);
  1583. up(&s->open_sem);
  1584. schedule();
  1585. remove_wait_queue(&s->open_wait, &wait);
  1586. set_current_state(TASK_RUNNING);
  1587. if (signal_pending(current))
  1588. return -ERESTARTSYS;
  1589. down(&s->open_sem);
  1590. }
  1591. stop_dac(s);
  1592. stop_adc(s);
  1593. if (file->f_mode & FMODE_READ) {
  1594. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  1595. s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
  1596. s->dma_adc.num_channels = 1;
  1597. s->dma_adc.sample_size = 8;
  1598. set_adc_rate(s, 8000);
  1599. if ((minor & 0xf) == SND_DEV_DSP16)
  1600. s->dma_adc.sample_size = 16;
  1601. }
  1602. if (file->f_mode & FMODE_WRITE) {
  1603. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  1604. s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
  1605. s->dma_dac.num_channels = 1;
  1606. s->dma_dac.sample_size = 8;
  1607. set_dac_rate(s, 8000);
  1608. if ((minor & 0xf) == SND_DEV_DSP16)
  1609. s->dma_dac.sample_size = 16;
  1610. }
  1611. if (file->f_mode & FMODE_READ) {
  1612. if ((ret = prog_dmabuf_adc(s)))
  1613. return ret;
  1614. }
  1615. if (file->f_mode & FMODE_WRITE) {
  1616. if ((ret = prog_dmabuf_dac(s)))
  1617. return ret;
  1618. }
  1619. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1620. up(&s->open_sem);
  1621. init_MUTEX(&s->sem);
  1622. return nonseekable_open(inode, file);
  1623. }
  1624. static int au1000_release(struct inode *inode, struct file *file)
  1625. {
  1626. struct au1000_state *s = (struct au1000_state *)file->private_data;
  1627. lock_kernel();
  1628. if (file->f_mode & FMODE_WRITE) {
  1629. unlock_kernel();
  1630. drain_dac(s, file->f_flags & O_NONBLOCK);
  1631. lock_kernel();
  1632. }
  1633. down(&s->open_sem);
  1634. if (file->f_mode & FMODE_WRITE) {
  1635. stop_dac(s);
  1636. dealloc_dmabuf(s, &s->dma_dac);
  1637. }
  1638. if (file->f_mode & FMODE_READ) {
  1639. stop_adc(s);
  1640. dealloc_dmabuf(s, &s->dma_adc);
  1641. }
  1642. s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
  1643. up(&s->open_sem);
  1644. wake_up(&s->open_wait);
  1645. unlock_kernel();
  1646. return 0;
  1647. }
  1648. static /*const */ struct file_operations au1000_audio_fops = {
  1649. .owner = THIS_MODULE,
  1650. .llseek = au1000_llseek,
  1651. .read = au1000_read,
  1652. .write = au1000_write,
  1653. .poll = au1000_poll,
  1654. .ioctl = au1000_ioctl,
  1655. .mmap = au1000_mmap,
  1656. .open = au1000_open,
  1657. .release = au1000_release,
  1658. };
  1659. /* --------------------------------------------------------------------- */
  1660. /* --------------------------------------------------------------------- */
  1661. /*
  1662. * for debugging purposes, we'll create a proc device that dumps the
  1663. * CODEC chipstate
  1664. */
  1665. #ifdef AU1000_DEBUG
  1666. static int proc_au1000_dump(char *buf, char **start, off_t fpos,
  1667. int length, int *eof, void *data)
  1668. {
  1669. struct au1000_state *s = &au1000_state;
  1670. int cnt, len = 0;
  1671. /* print out header */
  1672. len += sprintf(buf + len, "\n\t\tAU1000 Audio Debug\n\n");
  1673. // print out digital controller state
  1674. len += sprintf(buf + len, "AU1000 Audio Controller registers\n");
  1675. len += sprintf(buf + len, "---------------------------------\n");
  1676. len += sprintf (buf + len, "AC97C_CONFIG = %08x\n",
  1677. au_readl(AC97C_CONFIG));
  1678. len += sprintf (buf + len, "AC97C_STATUS = %08x\n",
  1679. au_readl(AC97C_STATUS));
  1680. len += sprintf (buf + len, "AC97C_CNTRL = %08x\n",
  1681. au_readl(AC97C_CNTRL));
  1682. /* print out CODEC state */
  1683. len += sprintf(buf + len, "\nAC97 CODEC registers\n");
  1684. len += sprintf(buf + len, "----------------------\n");
  1685. for (cnt = 0; cnt <= 0x7e; cnt += 2)
  1686. len += sprintf(buf + len, "reg %02x = %04x\n",
  1687. cnt, rdcodec(&s->codec, cnt));
  1688. if (fpos >= len) {
  1689. *start = buf;
  1690. *eof = 1;
  1691. return 0;
  1692. }
  1693. *start = buf + fpos;
  1694. if ((len -= fpos) > length)
  1695. return length;
  1696. *eof = 1;
  1697. return len;
  1698. }
  1699. #endif /* AU1000_DEBUG */
  1700. /* --------------------------------------------------------------------- */
  1701. MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
  1702. MODULE_DESCRIPTION("Au1000 Audio Driver");
  1703. /* --------------------------------------------------------------------- */
  1704. static int __devinit au1000_probe(void)
  1705. {
  1706. struct au1000_state *s = &au1000_state;
  1707. int val;
  1708. #ifdef AU1000_DEBUG
  1709. char proc_str[80];
  1710. #endif
  1711. memset(s, 0, sizeof(struct au1000_state));
  1712. init_waitqueue_head(&s->dma_adc.wait);
  1713. init_waitqueue_head(&s->dma_dac.wait);
  1714. init_waitqueue_head(&s->open_wait);
  1715. init_MUTEX(&s->open_sem);
  1716. spin_lock_init(&s->lock);
  1717. s->codec.private_data = s;
  1718. s->codec.id = 0;
  1719. s->codec.codec_read = rdcodec;
  1720. s->codec.codec_write = wrcodec;
  1721. s->codec.codec_wait = waitcodec;
  1722. if (!request_mem_region(CPHYSADDR(AC97C_CONFIG),
  1723. 0x14, AU1000_MODULE_NAME)) {
  1724. err("AC'97 ports in use");
  1725. return -1;
  1726. }
  1727. // Allocate the DMA Channels
  1728. if ((s->dma_dac.dmanr = request_au1000_dma(DMA_ID_AC97C_TX,
  1729. "audio DAC",
  1730. dac_dma_interrupt,
  1731. SA_INTERRUPT, s)) < 0) {
  1732. err("Can't get DAC DMA");
  1733. goto err_dma1;
  1734. }
  1735. if ((s->dma_adc.dmanr = request_au1000_dma(DMA_ID_AC97C_RX,
  1736. "audio ADC",
  1737. adc_dma_interrupt,
  1738. SA_INTERRUPT, s)) < 0) {
  1739. err("Can't get ADC DMA");
  1740. goto err_dma2;
  1741. }
  1742. info("DAC: DMA%d/IRQ%d, ADC: DMA%d/IRQ%d",
  1743. s->dma_dac.dmanr, get_dma_done_irq(s->dma_dac.dmanr),
  1744. s->dma_adc.dmanr, get_dma_done_irq(s->dma_adc.dmanr));
  1745. // enable DMA coherency in read/write DMA channels
  1746. set_dma_mode(s->dma_dac.dmanr,
  1747. get_dma_mode(s->dma_dac.dmanr) & ~DMA_NC);
  1748. set_dma_mode(s->dma_adc.dmanr,
  1749. get_dma_mode(s->dma_adc.dmanr) & ~DMA_NC);
  1750. /* register devices */
  1751. if ((s->dev_audio = register_sound_dsp(&au1000_audio_fops, -1)) < 0)
  1752. goto err_dev1;
  1753. if ((s->codec.dev_mixer =
  1754. register_sound_mixer(&au1000_mixer_fops, -1)) < 0)
  1755. goto err_dev2;
  1756. #ifdef AU1000_DEBUG
  1757. /* intialize the debug proc device */
  1758. s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
  1759. proc_au1000_dump, NULL);
  1760. #endif /* AU1000_DEBUG */
  1761. // configure pins for AC'97
  1762. au_writel(au_readl(SYS_PINFUNC) & ~0x02, SYS_PINFUNC);
  1763. // Assert reset for 10msec to the AC'97 controller, and enable clock
  1764. au_writel(AC97C_RS | AC97C_CE, AC97C_CNTRL);
  1765. au1000_delay(10);
  1766. au_writel(AC97C_CE, AC97C_CNTRL);
  1767. au1000_delay(10); // wait for clock to stabilize
  1768. /* cold reset the AC'97 */
  1769. au_writel(AC97C_RESET, AC97C_CONFIG);
  1770. au1000_delay(10);
  1771. au_writel(0, AC97C_CONFIG);
  1772. /* need to delay around 500msec(bleech) to give
  1773. some CODECs enough time to wakeup */
  1774. au1000_delay(500);
  1775. /* warm reset the AC'97 to start the bitclk */
  1776. au_writel(AC97C_SG | AC97C_SYNC, AC97C_CONFIG);
  1777. udelay(100);
  1778. au_writel(0, AC97C_CONFIG);
  1779. /* codec init */
  1780. if (!ac97_probe_codec(&s->codec))
  1781. goto err_dev3;
  1782. s->codec_base_caps = rdcodec(&s->codec, AC97_RESET);
  1783. s->codec_ext_caps = rdcodec(&s->codec, AC97_EXTENDED_ID);
  1784. info("AC'97 Base/Extended ID = %04x/%04x",
  1785. s->codec_base_caps, s->codec_ext_caps);
  1786. /*
  1787. * On the Pb1000, audio playback is on the AUX_OUT
  1788. * channel (which defaults to LNLVL_OUT in AC'97
  1789. * rev 2.2) so make sure this channel is listed
  1790. * as supported (soundcard.h calls this channel
  1791. * ALTPCM). ac97_codec.c does not handle detection
  1792. * of this channel correctly.
  1793. */
  1794. s->codec.supported_mixers |= SOUND_MASK_ALTPCM;
  1795. /*
  1796. * Now set AUX_OUT's default volume.
  1797. */
  1798. val = 0x4343;
  1799. mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_ALTPCM,
  1800. (unsigned long) &val);
  1801. if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
  1802. // codec does not support VRA
  1803. s->no_vra = 1;
  1804. } else if (!vra) {
  1805. // Boot option says disable VRA
  1806. u16 ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
  1807. wrcodec(&s->codec, AC97_EXTENDED_STATUS,
  1808. ac97_extstat & ~AC97_EXTSTAT_VRA);
  1809. s->no_vra = 1;
  1810. }
  1811. if (s->no_vra)
  1812. info("no VRA, interpolating and decimating");
  1813. /* set mic to be the recording source */
  1814. val = SOUND_MASK_MIC;
  1815. mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC,
  1816. (unsigned long) &val);
  1817. #ifdef AU1000_DEBUG
  1818. sprintf(proc_str, "driver/%s/%d/ac97", AU1000_MODULE_NAME,
  1819. s->codec.id);
  1820. s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
  1821. ac97_read_proc, &s->codec);
  1822. #endif
  1823. #ifdef CONFIG_MIPS_XXS1500
  1824. /* deassert eapd */
  1825. wrcodec(&s->codec, AC97_POWER_CONTROL,
  1826. rdcodec(&s->codec, AC97_POWER_CONTROL) & ~0x8000);
  1827. /* mute a number of signals which seem to be causing problems
  1828. * if not muted.
  1829. */
  1830. wrcodec(&s->codec, AC97_PCBEEP_VOL, 0x8000);
  1831. wrcodec(&s->codec, AC97_PHONE_VOL, 0x8008);
  1832. wrcodec(&s->codec, AC97_MIC_VOL, 0x8008);
  1833. wrcodec(&s->codec, AC97_LINEIN_VOL, 0x8808);
  1834. wrcodec(&s->codec, AC97_CD_VOL, 0x8808);
  1835. wrcodec(&s->codec, AC97_VIDEO_VOL, 0x8808);
  1836. wrcodec(&s->codec, AC97_AUX_VOL, 0x8808);
  1837. wrcodec(&s->codec, AC97_PCMOUT_VOL, 0x0808);
  1838. wrcodec(&s->codec, AC97_GENERAL_PURPOSE, 0x2000);
  1839. #endif
  1840. return 0;
  1841. err_dev3:
  1842. unregister_sound_mixer(s->codec.dev_mixer);
  1843. err_dev2:
  1844. unregister_sound_dsp(s->dev_audio);
  1845. err_dev1:
  1846. free_au1000_dma(s->dma_adc.dmanr);
  1847. err_dma2:
  1848. free_au1000_dma(s->dma_dac.dmanr);
  1849. err_dma1:
  1850. release_mem_region(CPHYSADDR(AC97C_CONFIG), 0x14);
  1851. return -1;
  1852. }
  1853. static void au1000_remove(void)
  1854. {
  1855. struct au1000_state *s = &au1000_state;
  1856. if (!s)
  1857. return;
  1858. #ifdef AU1000_DEBUG
  1859. if (s->ps)
  1860. remove_proc_entry(AU1000_MODULE_NAME, NULL);
  1861. #endif /* AU1000_DEBUG */
  1862. synchronize_irq();
  1863. free_au1000_dma(s->dma_adc.dmanr);
  1864. free_au1000_dma(s->dma_dac.dmanr);
  1865. release_mem_region(CPHYSADDR(AC97C_CONFIG), 0x14);
  1866. unregister_sound_dsp(s->dev_audio);
  1867. unregister_sound_mixer(s->codec.dev_mixer);
  1868. }
  1869. static int __init init_au1000(void)
  1870. {
  1871. info("stevel@mvista.com, built " __TIME__ " on " __DATE__);
  1872. return au1000_probe();
  1873. }
  1874. static void __exit cleanup_au1000(void)
  1875. {
  1876. info("unloading");
  1877. au1000_remove();
  1878. }
  1879. module_init(init_au1000);
  1880. module_exit(cleanup_au1000);
  1881. /* --------------------------------------------------------------------- */
  1882. #ifndef MODULE
  1883. static int __init au1000_setup(char *options)
  1884. {
  1885. char *this_opt;
  1886. if (!options || !*options)
  1887. return 0;
  1888. while ((this_opt = strsep(&options, ","))) {
  1889. if (!*this_opt)
  1890. continue;
  1891. if (!strncmp(this_opt, "vra", 3)) {
  1892. vra = 1;
  1893. }
  1894. }
  1895. return 1;
  1896. }
  1897. __setup("au1000_audio=", au1000_setup);
  1898. #endif /* MODULE */