irq.h 4.0 KB

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  1. /* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
  2. * irq.h: IRQ registers on the 64-bit Sparc.
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5. * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
  6. */
  7. #ifndef _SPARC64_IRQ_H
  8. #define _SPARC64_IRQ_H
  9. #include <linux/config.h>
  10. #include <linux/linkage.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/interrupt.h>
  14. #include <asm/pil.h>
  15. #include <asm/ptrace.h>
  16. struct ino_bucket;
  17. #define MAX_IRQ_DESC_ACTION 4
  18. struct irq_desc {
  19. void (*pre_handler)(struct ino_bucket *, void *, void *);
  20. void *pre_handler_arg1;
  21. void *pre_handler_arg2;
  22. u32 action_active_mask;
  23. struct irqaction action[MAX_IRQ_DESC_ACTION];
  24. };
  25. /* You should not mess with this directly. That's the job of irq.c.
  26. *
  27. * If you make changes here, please update hand coded assembler of
  28. * the vectored interrupt trap handler in entry.S -DaveM
  29. *
  30. * This is currently one DCACHE line, two buckets per L2 cache
  31. * line. Keep this in mind please.
  32. */
  33. struct ino_bucket {
  34. /* Next handler in per-CPU PIL worklist. We know that
  35. * bucket pointers have the high 32-bits clear, so to
  36. * save space we only store the bits we need.
  37. */
  38. /*0x00*/unsigned int irq_chain;
  39. /* PIL to schedule this IVEC at. */
  40. /*0x04*/unsigned char pil;
  41. /* If an IVEC arrives while irq_info is NULL, we
  42. * set this to notify request_irq() about the event.
  43. */
  44. /*0x05*/unsigned char pending;
  45. /* Miscellaneous flags. */
  46. /*0x06*/unsigned char flags;
  47. /* Currently unused. */
  48. /*0x07*/unsigned char __pad;
  49. /* Reference to IRQ descriptor for this bucket. */
  50. /*0x08*/struct irq_desc *irq_info;
  51. /* Sun5 Interrupt Clear Register. */
  52. /*0x10*/unsigned long iclr;
  53. /* Sun5 Interrupt Mapping Register. */
  54. /*0x18*/unsigned long imap;
  55. };
  56. /* IMAP/ICLR register defines */
  57. #define IMAP_VALID 0x80000000 /* IRQ Enabled */
  58. #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
  59. #define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
  60. #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
  61. #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
  62. #define IMAP_IGN 0x000007c0 /* IRQ Group Number */
  63. #define IMAP_INO 0x0000003f /* IRQ Number */
  64. #define IMAP_INR 0x000007ff /* Full interrupt number*/
  65. #define ICLR_IDLE 0x00000000 /* Idle state */
  66. #define ICLR_TRANSMIT 0x00000001 /* Transmit state */
  67. #define ICLR_PENDING 0x00000003 /* Pending state */
  68. /* Only 8-bits are available, be careful. -DaveM */
  69. #define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
  70. #define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
  71. #define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
  72. #define NUM_IVECS (IMAP_INR + 1)
  73. extern struct ino_bucket ivector_table[NUM_IVECS];
  74. #define __irq_ino(irq) \
  75. (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
  76. #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
  77. #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
  78. #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
  79. static __inline__ char *__irq_itoa(unsigned int irq)
  80. {
  81. static char buff[16];
  82. sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
  83. return buff;
  84. }
  85. #define NR_IRQS 16
  86. #define irq_canonicalize(irq) (irq)
  87. extern void disable_irq(unsigned int);
  88. #define disable_irq_nosync disable_irq
  89. extern void enable_irq(unsigned int);
  90. extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
  91. extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
  92. static __inline__ void set_softint(unsigned long bits)
  93. {
  94. __asm__ __volatile__("wr %0, 0x0, %%set_softint"
  95. : /* No outputs */
  96. : "r" (bits));
  97. }
  98. static __inline__ void clear_softint(unsigned long bits)
  99. {
  100. __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
  101. : /* No outputs */
  102. : "r" (bits));
  103. }
  104. static __inline__ unsigned long get_softint(void)
  105. {
  106. unsigned long retval;
  107. __asm__ __volatile__("rd %%softint, %0"
  108. : "=r" (retval));
  109. return retval;
  110. }
  111. struct irqaction;
  112. struct pt_regs;
  113. int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
  114. #endif