topology.h 2.9 KB

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  1. /*
  2. * linux/include/asm-ia64/topology.h
  3. *
  4. * Copyright (C) 2002, Erich Focht, NEC
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #ifndef _ASM_IA64_TOPOLOGY_H
  14. #define _ASM_IA64_TOPOLOGY_H
  15. #include <asm/acpi.h>
  16. #include <asm/numa.h>
  17. #include <asm/smp.h>
  18. #ifdef CONFIG_NUMA
  19. /* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
  20. #define PENALTY_FOR_NODE_WITH_CPUS 255
  21. /*
  22. * Returns the number of the node containing CPU 'cpu'
  23. */
  24. #define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
  25. /*
  26. * Returns a bitmask of CPUs on Node 'node'.
  27. */
  28. #define node_to_cpumask(node) (node_to_cpu_mask[node])
  29. /*
  30. * Returns the number of the node containing Node 'nid'.
  31. * Not implemented here. Multi-level hierarchies detected with
  32. * the help of node_distance().
  33. */
  34. #define parent_node(nid) (nid)
  35. /*
  36. * Returns the number of the first CPU on Node 'node'.
  37. */
  38. #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
  39. /*
  40. * Determines the node for a given pci bus
  41. */
  42. #define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
  43. void build_cpu_to_node_map(void);
  44. #define SD_CPU_INIT (struct sched_domain) { \
  45. .span = CPU_MASK_NONE, \
  46. .parent = NULL, \
  47. .groups = NULL, \
  48. .min_interval = 1, \
  49. .max_interval = 4, \
  50. .busy_factor = 64, \
  51. .imbalance_pct = 125, \
  52. .per_cpu_gain = 100, \
  53. .cache_nice_tries = 2, \
  54. .busy_idx = 2, \
  55. .idle_idx = 1, \
  56. .newidle_idx = 2, \
  57. .wake_idx = 1, \
  58. .forkexec_idx = 1, \
  59. .flags = SD_LOAD_BALANCE \
  60. | SD_BALANCE_NEWIDLE \
  61. | SD_BALANCE_EXEC \
  62. | SD_WAKE_AFFINE, \
  63. .last_balance = jiffies, \
  64. .balance_interval = 1, \
  65. .nr_balance_failed = 0, \
  66. }
  67. /* sched_domains SD_NODE_INIT for IA64 NUMA machines */
  68. #define SD_NODE_INIT (struct sched_domain) { \
  69. .span = CPU_MASK_NONE, \
  70. .parent = NULL, \
  71. .groups = NULL, \
  72. .min_interval = 8, \
  73. .max_interval = 8*(min(num_online_cpus(), 32)), \
  74. .busy_factor = 64, \
  75. .imbalance_pct = 125, \
  76. .cache_nice_tries = 2, \
  77. .busy_idx = 3, \
  78. .idle_idx = 2, \
  79. .newidle_idx = 0, /* unused */ \
  80. .wake_idx = 1, \
  81. .forkexec_idx = 1, \
  82. .per_cpu_gain = 100, \
  83. .flags = SD_LOAD_BALANCE \
  84. | SD_BALANCE_EXEC \
  85. | SD_BALANCE_FORK \
  86. | SD_WAKE_BALANCE, \
  87. .last_balance = jiffies, \
  88. .balance_interval = 64, \
  89. .nr_balance_failed = 0, \
  90. }
  91. #endif /* CONFIG_NUMA */
  92. #ifdef CONFIG_SMP
  93. #define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
  94. #define topology_core_id(cpu) (cpu_data(cpu)->core_id)
  95. #define topology_core_siblings(cpu) (cpu_core_map[cpu])
  96. #define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
  97. #endif
  98. #include <asm-generic/topology.h>
  99. #endif /* _ASM_IA64_TOPOLOGY_H */