intelfb.h 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286
  1. #ifndef _INTELFB_H
  2. #define _INTELFB_H
  3. /* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */
  4. #include <linux/agp_backend.h>
  5. #include <linux/fb.h>
  6. /*** Version/name ***/
  7. #define INTELFB_VERSION "0.9.2"
  8. #define INTELFB_MODULE_NAME "intelfb"
  9. #define SUPPORTED_CHIPSETS "830M/845G/852GM/855GM/865G/915G/915GM"
  10. /*** Debug/feature defines ***/
  11. #ifndef DEBUG
  12. #define DEBUG 0
  13. #endif
  14. #ifndef VERBOSE
  15. #define VERBOSE 0
  16. #endif
  17. #ifndef REGDUMP
  18. #define REGDUMP 0
  19. #endif
  20. #ifndef DETECT_VGA_CLASS_ONLY
  21. #define DETECT_VGA_CLASS_ONLY 1
  22. #endif
  23. #ifndef ALLOCATE_FOR_PANNING
  24. #define ALLOCATE_FOR_PANNING 1
  25. #endif
  26. #ifndef PREFERRED_MODE
  27. #define PREFERRED_MODE "1024x768-32@70"
  28. #endif
  29. /*** hw-related values ***/
  30. /* Resource Allocation */
  31. #define INTELFB_FB_ACQUIRED 1
  32. #define INTELFB_MMIO_ACQUIRED 2
  33. /* PCI ids for supported devices */
  34. #define PCI_DEVICE_ID_INTEL_830M 0x3577
  35. #define PCI_DEVICE_ID_INTEL_845G 0x2562
  36. #define PCI_DEVICE_ID_INTEL_85XGM 0x3582
  37. #define PCI_DEVICE_ID_INTEL_865G 0x2572
  38. #define PCI_DEVICE_ID_INTEL_915G 0x2582
  39. #define PCI_DEVICE_ID_INTEL_915GM 0x2592
  40. /* Size of MMIO region */
  41. #define INTEL_REG_SIZE 0x80000
  42. #define STRIDE_ALIGNMENT 16
  43. #define PALETTE_8_ENTRIES 256
  44. /*** Macros ***/
  45. /* basic arithmetic */
  46. #define KB(x) ((x) * 1024)
  47. #define MB(x) ((x) * 1024 * 1024)
  48. #define BtoKB(x) ((x) / 1024)
  49. #define BtoMB(x) ((x) / 1024 / 1024)
  50. #define GTT_PAGE_SIZE KB(4)
  51. #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
  52. #define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
  53. #define ROUND_UP_TO_PAGE(x) ROUND_UP_TO((x), GTT_PAGE_SIZE)
  54. #define ROUND_DOWN_TO_PAGE(x) ROUND_DOWN_TO((x), GTT_PAGE_SIZE)
  55. /* messages */
  56. #define PFX INTELFB_MODULE_NAME ": "
  57. #define ERR_MSG(fmt, args...) printk(KERN_ERR PFX fmt, ## args)
  58. #define WRN_MSG(fmt, args...) printk(KERN_WARNING PFX fmt, ## args)
  59. #define NOT_MSG(fmt, args...) printk(KERN_NOTICE PFX fmt, ## args)
  60. #define INF_MSG(fmt, args...) printk(KERN_INFO PFX fmt, ## args)
  61. #if DEBUG
  62. #define DBG_MSG(fmt, args...) printk(KERN_DEBUG PFX fmt, ## args)
  63. #else
  64. #define DBG_MSG(fmt, args...) while (0) printk(fmt, ## args)
  65. #endif
  66. /* get commonly used pointers */
  67. #define GET_DINFO(info) (info)->par
  68. /* misc macros */
  69. #define ACCEL(d, i) \
  70. ((d)->accel && !(d)->ring_lockup && \
  71. ((i)->var.accel_flags & FB_ACCELF_TEXT))
  72. /*#define NOACCEL_CHIPSET(d) \
  73. ((d)->chipset != INTEL_865G)*/
  74. #define NOACCEL_CHIPSET(d) \
  75. (0)
  76. #define FIXED_MODE(d) ((d)->fixed_mode)
  77. /*** Driver paramters ***/
  78. #define RINGBUFFER_SIZE KB(64)
  79. #define HW_CURSOR_SIZE KB(4)
  80. /* Intel agpgart driver */
  81. #define AGP_PHYSICAL_MEMORY 2
  82. /*** Data Types ***/
  83. /* supported chipsets */
  84. enum intel_chips {
  85. INTEL_830M,
  86. INTEL_845G,
  87. INTEL_85XGM,
  88. INTEL_852GM,
  89. INTEL_852GME,
  90. INTEL_855GM,
  91. INTEL_855GME,
  92. INTEL_865G,
  93. INTEL_915G,
  94. INTEL_915GM
  95. };
  96. struct intelfb_hwstate {
  97. u32 vga0_divisor;
  98. u32 vga1_divisor;
  99. u32 vga_pd;
  100. u32 dpll_a;
  101. u32 dpll_b;
  102. u32 fpa0;
  103. u32 fpa1;
  104. u32 fpb0;
  105. u32 fpb1;
  106. u32 palette_a[PALETTE_8_ENTRIES];
  107. u32 palette_b[PALETTE_8_ENTRIES];
  108. u32 htotal_a;
  109. u32 hblank_a;
  110. u32 hsync_a;
  111. u32 vtotal_a;
  112. u32 vblank_a;
  113. u32 vsync_a;
  114. u32 src_size_a;
  115. u32 bclrpat_a;
  116. u32 htotal_b;
  117. u32 hblank_b;
  118. u32 hsync_b;
  119. u32 vtotal_b;
  120. u32 vblank_b;
  121. u32 vsync_b;
  122. u32 src_size_b;
  123. u32 bclrpat_b;
  124. u32 adpa;
  125. u32 dvoa;
  126. u32 dvob;
  127. u32 dvoc;
  128. u32 dvoa_srcdim;
  129. u32 dvob_srcdim;
  130. u32 dvoc_srcdim;
  131. u32 lvds;
  132. u32 pipe_a_conf;
  133. u32 pipe_b_conf;
  134. u32 disp_arb;
  135. u32 cursor_a_control;
  136. u32 cursor_b_control;
  137. u32 cursor_a_base;
  138. u32 cursor_b_base;
  139. u32 cursor_size;
  140. u32 disp_a_ctrl;
  141. u32 disp_b_ctrl;
  142. u32 disp_a_base;
  143. u32 disp_b_base;
  144. u32 cursor_a_palette[4];
  145. u32 cursor_b_palette[4];
  146. u32 disp_a_stride;
  147. u32 disp_b_stride;
  148. u32 vgacntrl;
  149. u32 add_id;
  150. u32 swf0x[7];
  151. u32 swf1x[7];
  152. u32 swf3x[3];
  153. u32 fence[8];
  154. u32 instpm;
  155. u32 mem_mode;
  156. u32 fw_blc_0;
  157. u32 fw_blc_1;
  158. };
  159. struct intelfb_heap_data {
  160. u32 physical;
  161. u8 __iomem *virtual;
  162. u32 offset; // in GATT pages
  163. u32 size; // in bytes
  164. };
  165. struct intelfb_info {
  166. struct fb_info *info;
  167. struct fb_ops *fbops;
  168. struct pci_dev *pdev;
  169. struct intelfb_hwstate save_state;
  170. /* agpgart structs */
  171. struct agp_memory *gtt_fb_mem; // use all stolen memory or vram
  172. struct agp_memory *gtt_ring_mem; // ring buffer
  173. struct agp_memory *gtt_cursor_mem; // hw cursor
  174. /* use a gart reserved fb mem */
  175. u8 fbmem_gart;
  176. /* mtrr support */
  177. u32 mtrr_reg;
  178. u32 has_mtrr;
  179. /* heap data */
  180. struct intelfb_heap_data aperture;
  181. struct intelfb_heap_data fb;
  182. struct intelfb_heap_data ring;
  183. struct intelfb_heap_data cursor;
  184. /* mmio regs */
  185. u32 mmio_base_phys;
  186. u8 __iomem *mmio_base;
  187. /* fb start offset (in bytes) */
  188. u32 fb_start;
  189. /* ring buffer */
  190. u8 __iomem *ring_head;
  191. u32 ring_tail;
  192. u32 ring_tail_mask;
  193. u32 ring_space;
  194. u32 ring_lockup;
  195. /* palette */
  196. u32 pseudo_palette[17];
  197. /* chip info */
  198. int pci_chipset;
  199. int chipset;
  200. const char *name;
  201. int mobile;
  202. /* current mode */
  203. int bpp, depth;
  204. u32 visual;
  205. int xres, yres, pitch;
  206. int pixclock;
  207. /* current pipe */
  208. int pipe;
  209. /* some flags */
  210. int accel;
  211. int hwcursor;
  212. int fixed_mode;
  213. int ring_active;
  214. int flag;
  215. /* hw cursor */
  216. int cursor_on;
  217. int cursor_blanked;
  218. u8 cursor_src[64];
  219. /* initial parameters */
  220. int initial_vga;
  221. struct fb_var_screeninfo initial_var;
  222. u32 initial_fb_base;
  223. u32 initial_video_ram;
  224. u32 initial_pitch;
  225. /* driver registered */
  226. int registered;
  227. };
  228. /*** function prototypes ***/
  229. extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
  230. #endif /* _INTELFB_H */