sata_nv.c 17 KB

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  1. /*
  2. * sata_nv.c - NVIDIA nForce SATA
  3. *
  4. * Copyright 2004 NVIDIA Corp. All rights reserved.
  5. * Copyright 2004 Andrew Chew
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; see the file COPYING. If not, write to
  20. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. *
  23. * libata documentation is available via 'make {ps|pdf}docs',
  24. * as Documentation/DocBook/libata.*
  25. *
  26. * No hardware documentation available outside of NVIDIA.
  27. * This driver programs the NVIDIA SATA controller in a similar
  28. * fashion as with other PCI IDE BMDMA controllers, with a few
  29. * NV-specific details such as register offsets, SATA phy location,
  30. * hotplug info, etc.
  31. *
  32. * 0.10
  33. * - Fixed spurious interrupts issue seen with the Maxtor 6H500F0 500GB
  34. * drive. Also made the check_hotplug() callbacks return whether there
  35. * was a hotplug interrupt or not. This was not the source of the
  36. * spurious interrupts, but is the right thing to do anyway.
  37. *
  38. * 0.09
  39. * - Fixed bug introduced by 0.08's MCP51 and MCP55 support.
  40. *
  41. * 0.08
  42. * - Added support for MCP51 and MCP55.
  43. *
  44. * 0.07
  45. * - Added support for RAID class code.
  46. *
  47. * 0.06
  48. * - Added generic SATA support by using a pci_device_id that filters on
  49. * the IDE storage class code.
  50. *
  51. * 0.03
  52. * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
  53. * mmio_base, which is only set for the CK804/MCP04 case.
  54. *
  55. * 0.02
  56. * - Added support for CK804 SATA controller.
  57. *
  58. * 0.01
  59. * - Initial revision.
  60. */
  61. #include <linux/config.h>
  62. #include <linux/kernel.h>
  63. #include <linux/module.h>
  64. #include <linux/pci.h>
  65. #include <linux/init.h>
  66. #include <linux/blkdev.h>
  67. #include <linux/delay.h>
  68. #include <linux/interrupt.h>
  69. #include <linux/device.h>
  70. #include <scsi/scsi_host.h>
  71. #include <linux/libata.h>
  72. #define DRV_NAME "sata_nv"
  73. #define DRV_VERSION "0.8"
  74. #define NV_PORTS 2
  75. #define NV_PIO_MASK 0x1f
  76. #define NV_MWDMA_MASK 0x07
  77. #define NV_UDMA_MASK 0x7f
  78. #define NV_PORT0_SCR_REG_OFFSET 0x00
  79. #define NV_PORT1_SCR_REG_OFFSET 0x40
  80. #define NV_INT_STATUS 0x10
  81. #define NV_INT_STATUS_CK804 0x440
  82. #define NV_INT_STATUS_PDEV_INT 0x01
  83. #define NV_INT_STATUS_PDEV_PM 0x02
  84. #define NV_INT_STATUS_PDEV_ADDED 0x04
  85. #define NV_INT_STATUS_PDEV_REMOVED 0x08
  86. #define NV_INT_STATUS_SDEV_INT 0x10
  87. #define NV_INT_STATUS_SDEV_PM 0x20
  88. #define NV_INT_STATUS_SDEV_ADDED 0x40
  89. #define NV_INT_STATUS_SDEV_REMOVED 0x80
  90. #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
  91. NV_INT_STATUS_PDEV_REMOVED)
  92. #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
  93. NV_INT_STATUS_SDEV_REMOVED)
  94. #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
  95. NV_INT_STATUS_SDEV_HOTPLUG)
  96. #define NV_INT_ENABLE 0x11
  97. #define NV_INT_ENABLE_CK804 0x441
  98. #define NV_INT_ENABLE_PDEV_MASK 0x01
  99. #define NV_INT_ENABLE_PDEV_PM 0x02
  100. #define NV_INT_ENABLE_PDEV_ADDED 0x04
  101. #define NV_INT_ENABLE_PDEV_REMOVED 0x08
  102. #define NV_INT_ENABLE_SDEV_MASK 0x10
  103. #define NV_INT_ENABLE_SDEV_PM 0x20
  104. #define NV_INT_ENABLE_SDEV_ADDED 0x40
  105. #define NV_INT_ENABLE_SDEV_REMOVED 0x80
  106. #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
  107. NV_INT_ENABLE_PDEV_REMOVED)
  108. #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
  109. NV_INT_ENABLE_SDEV_REMOVED)
  110. #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
  111. NV_INT_ENABLE_SDEV_HOTPLUG)
  112. #define NV_INT_CONFIG 0x12
  113. #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
  114. // For PCI config register 20
  115. #define NV_MCP_SATA_CFG_20 0x50
  116. #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
  117. static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  118. static irqreturn_t nv_interrupt (int irq, void *dev_instance,
  119. struct pt_regs *regs);
  120. static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
  121. static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  122. static void nv_host_stop (struct ata_host_set *host_set);
  123. static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
  124. static void nv_disable_hotplug(struct ata_host_set *host_set);
  125. static int nv_check_hotplug(struct ata_host_set *host_set);
  126. static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
  127. static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
  128. static int nv_check_hotplug_ck804(struct ata_host_set *host_set);
  129. enum nv_host_type
  130. {
  131. GENERIC,
  132. NFORCE2,
  133. NFORCE3,
  134. CK804
  135. };
  136. static const struct pci_device_id nv_pci_tbl[] = {
  137. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
  138. PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
  139. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
  140. PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
  141. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
  142. PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
  143. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
  144. PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
  145. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
  146. PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
  147. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
  148. PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
  149. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
  150. PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
  151. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
  152. PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
  153. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
  154. PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
  155. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
  156. PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
  157. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
  158. PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
  159. { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  160. PCI_ANY_ID, PCI_ANY_ID,
  161. PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
  162. { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  163. PCI_ANY_ID, PCI_ANY_ID,
  164. PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
  165. { 0, } /* terminate list */
  166. };
  167. #define NV_HOST_FLAGS_SCR_MMIO 0x00000001
  168. struct nv_host_desc
  169. {
  170. enum nv_host_type host_type;
  171. void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
  172. void (*disable_hotplug)(struct ata_host_set *host_set);
  173. int (*check_hotplug)(struct ata_host_set *host_set);
  174. };
  175. static struct nv_host_desc nv_device_tbl[] = {
  176. {
  177. .host_type = GENERIC,
  178. .enable_hotplug = NULL,
  179. .disable_hotplug= NULL,
  180. .check_hotplug = NULL,
  181. },
  182. {
  183. .host_type = NFORCE2,
  184. .enable_hotplug = nv_enable_hotplug,
  185. .disable_hotplug= nv_disable_hotplug,
  186. .check_hotplug = nv_check_hotplug,
  187. },
  188. {
  189. .host_type = NFORCE3,
  190. .enable_hotplug = nv_enable_hotplug,
  191. .disable_hotplug= nv_disable_hotplug,
  192. .check_hotplug = nv_check_hotplug,
  193. },
  194. { .host_type = CK804,
  195. .enable_hotplug = nv_enable_hotplug_ck804,
  196. .disable_hotplug= nv_disable_hotplug_ck804,
  197. .check_hotplug = nv_check_hotplug_ck804,
  198. },
  199. };
  200. struct nv_host
  201. {
  202. struct nv_host_desc *host_desc;
  203. unsigned long host_flags;
  204. };
  205. static struct pci_driver nv_pci_driver = {
  206. .name = DRV_NAME,
  207. .id_table = nv_pci_tbl,
  208. .probe = nv_init_one,
  209. .remove = ata_pci_remove_one,
  210. };
  211. static struct scsi_host_template nv_sht = {
  212. .module = THIS_MODULE,
  213. .name = DRV_NAME,
  214. .ioctl = ata_scsi_ioctl,
  215. .queuecommand = ata_scsi_queuecmd,
  216. .eh_strategy_handler = ata_scsi_error,
  217. .can_queue = ATA_DEF_QUEUE,
  218. .this_id = ATA_SHT_THIS_ID,
  219. .sg_tablesize = LIBATA_MAX_PRD,
  220. .max_sectors = ATA_MAX_SECTORS,
  221. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  222. .emulated = ATA_SHT_EMULATED,
  223. .use_clustering = ATA_SHT_USE_CLUSTERING,
  224. .proc_name = DRV_NAME,
  225. .dma_boundary = ATA_DMA_BOUNDARY,
  226. .slave_configure = ata_scsi_slave_config,
  227. .bios_param = ata_std_bios_param,
  228. };
  229. static const struct ata_port_operations nv_ops = {
  230. .port_disable = ata_port_disable,
  231. .tf_load = ata_tf_load,
  232. .tf_read = ata_tf_read,
  233. .exec_command = ata_exec_command,
  234. .check_status = ata_check_status,
  235. .dev_select = ata_std_dev_select,
  236. .phy_reset = sata_phy_reset,
  237. .bmdma_setup = ata_bmdma_setup,
  238. .bmdma_start = ata_bmdma_start,
  239. .bmdma_stop = ata_bmdma_stop,
  240. .bmdma_status = ata_bmdma_status,
  241. .qc_prep = ata_qc_prep,
  242. .qc_issue = ata_qc_issue_prot,
  243. .eng_timeout = ata_eng_timeout,
  244. .irq_handler = nv_interrupt,
  245. .irq_clear = ata_bmdma_irq_clear,
  246. .scr_read = nv_scr_read,
  247. .scr_write = nv_scr_write,
  248. .port_start = ata_port_start,
  249. .port_stop = ata_port_stop,
  250. .host_stop = nv_host_stop,
  251. };
  252. /* FIXME: The hardware provides the necessary SATA PHY controls
  253. * to support ATA_FLAG_SATA_RESET. However, it is currently
  254. * necessary to disable that flag, to solve misdetection problems.
  255. * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
  256. *
  257. * This problem really needs to be investigated further. But in the
  258. * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
  259. */
  260. static struct ata_port_info nv_port_info = {
  261. .sht = &nv_sht,
  262. .host_flags = ATA_FLAG_SATA |
  263. /* ATA_FLAG_SATA_RESET | */
  264. ATA_FLAG_SRST |
  265. ATA_FLAG_NO_LEGACY,
  266. .pio_mask = NV_PIO_MASK,
  267. .mwdma_mask = NV_MWDMA_MASK,
  268. .udma_mask = NV_UDMA_MASK,
  269. .port_ops = &nv_ops,
  270. };
  271. MODULE_AUTHOR("NVIDIA");
  272. MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
  273. MODULE_LICENSE("GPL");
  274. MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
  275. MODULE_VERSION(DRV_VERSION);
  276. static irqreturn_t nv_interrupt (int irq, void *dev_instance,
  277. struct pt_regs *regs)
  278. {
  279. struct ata_host_set *host_set = dev_instance;
  280. struct nv_host *host = host_set->private_data;
  281. unsigned int i;
  282. unsigned int handled = 0;
  283. unsigned long flags;
  284. spin_lock_irqsave(&host_set->lock, flags);
  285. for (i = 0; i < host_set->n_ports; i++) {
  286. struct ata_port *ap;
  287. ap = host_set->ports[i];
  288. if (ap &&
  289. !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
  290. struct ata_queued_cmd *qc;
  291. qc = ata_qc_from_tag(ap, ap->active_tag);
  292. if (qc && (!(qc->tf.ctl & ATA_NIEN)))
  293. handled += ata_host_intr(ap, qc);
  294. else
  295. // No request pending? Clear interrupt status
  296. // anyway, in case there's one pending.
  297. ap->ops->check_status(ap);
  298. }
  299. }
  300. if (host->host_desc->check_hotplug)
  301. handled += host->host_desc->check_hotplug(host_set);
  302. spin_unlock_irqrestore(&host_set->lock, flags);
  303. return IRQ_RETVAL(handled);
  304. }
  305. static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
  306. {
  307. struct ata_host_set *host_set = ap->host_set;
  308. struct nv_host *host = host_set->private_data;
  309. if (sc_reg > SCR_CONTROL)
  310. return 0xffffffffU;
  311. if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
  312. return readl((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
  313. else
  314. return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
  315. }
  316. static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
  317. {
  318. struct ata_host_set *host_set = ap->host_set;
  319. struct nv_host *host = host_set->private_data;
  320. if (sc_reg > SCR_CONTROL)
  321. return;
  322. if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
  323. writel(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
  324. else
  325. outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
  326. }
  327. static void nv_host_stop (struct ata_host_set *host_set)
  328. {
  329. struct nv_host *host = host_set->private_data;
  330. struct pci_dev *pdev = to_pci_dev(host_set->dev);
  331. // Disable hotplug event interrupts.
  332. if (host->host_desc->disable_hotplug)
  333. host->host_desc->disable_hotplug(host_set);
  334. kfree(host);
  335. if (host_set->mmio_base)
  336. pci_iounmap(pdev, host_set->mmio_base);
  337. }
  338. static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  339. {
  340. static int printed_version = 0;
  341. struct nv_host *host;
  342. struct ata_port_info *ppi;
  343. struct ata_probe_ent *probe_ent;
  344. int pci_dev_busy = 0;
  345. int rc;
  346. u32 bar;
  347. // Make sure this is a SATA controller by counting the number of bars
  348. // (NVIDIA SATA controllers will always have six bars). Otherwise,
  349. // it's an IDE controller and we ignore it.
  350. for (bar=0; bar<6; bar++)
  351. if (pci_resource_start(pdev, bar) == 0)
  352. return -ENODEV;
  353. if (!printed_version++)
  354. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  355. rc = pci_enable_device(pdev);
  356. if (rc)
  357. goto err_out;
  358. rc = pci_request_regions(pdev, DRV_NAME);
  359. if (rc) {
  360. pci_dev_busy = 1;
  361. goto err_out_disable;
  362. }
  363. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  364. if (rc)
  365. goto err_out_regions;
  366. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  367. if (rc)
  368. goto err_out_regions;
  369. rc = -ENOMEM;
  370. ppi = &nv_port_info;
  371. probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
  372. if (!probe_ent)
  373. goto err_out_regions;
  374. host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
  375. if (!host)
  376. goto err_out_free_ent;
  377. memset(host, 0, sizeof(struct nv_host));
  378. host->host_desc = &nv_device_tbl[ent->driver_data];
  379. probe_ent->private_data = host;
  380. if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM)
  381. host->host_flags |= NV_HOST_FLAGS_SCR_MMIO;
  382. if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
  383. unsigned long base;
  384. probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
  385. if (probe_ent->mmio_base == NULL) {
  386. rc = -EIO;
  387. goto err_out_free_host;
  388. }
  389. base = (unsigned long)probe_ent->mmio_base;
  390. probe_ent->port[0].scr_addr =
  391. base + NV_PORT0_SCR_REG_OFFSET;
  392. probe_ent->port[1].scr_addr =
  393. base + NV_PORT1_SCR_REG_OFFSET;
  394. } else {
  395. probe_ent->port[0].scr_addr =
  396. pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
  397. probe_ent->port[1].scr_addr =
  398. pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
  399. }
  400. pci_set_master(pdev);
  401. rc = ata_device_add(probe_ent);
  402. if (rc != NV_PORTS)
  403. goto err_out_iounmap;
  404. // Enable hotplug event interrupts.
  405. if (host->host_desc->enable_hotplug)
  406. host->host_desc->enable_hotplug(probe_ent);
  407. kfree(probe_ent);
  408. return 0;
  409. err_out_iounmap:
  410. if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
  411. pci_iounmap(pdev, probe_ent->mmio_base);
  412. err_out_free_host:
  413. kfree(host);
  414. err_out_free_ent:
  415. kfree(probe_ent);
  416. err_out_regions:
  417. pci_release_regions(pdev);
  418. err_out_disable:
  419. if (!pci_dev_busy)
  420. pci_disable_device(pdev);
  421. err_out:
  422. return rc;
  423. }
  424. static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
  425. {
  426. u8 intr_mask;
  427. outb(NV_INT_STATUS_HOTPLUG,
  428. probe_ent->port[0].scr_addr + NV_INT_STATUS);
  429. intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
  430. intr_mask |= NV_INT_ENABLE_HOTPLUG;
  431. outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
  432. }
  433. static void nv_disable_hotplug(struct ata_host_set *host_set)
  434. {
  435. u8 intr_mask;
  436. intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
  437. intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
  438. outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
  439. }
  440. static int nv_check_hotplug(struct ata_host_set *host_set)
  441. {
  442. u8 intr_status;
  443. intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
  444. // Clear interrupt status.
  445. outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
  446. if (intr_status & NV_INT_STATUS_HOTPLUG) {
  447. if (intr_status & NV_INT_STATUS_PDEV_ADDED)
  448. printk(KERN_WARNING "nv_sata: "
  449. "Primary device added\n");
  450. if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
  451. printk(KERN_WARNING "nv_sata: "
  452. "Primary device removed\n");
  453. if (intr_status & NV_INT_STATUS_SDEV_ADDED)
  454. printk(KERN_WARNING "nv_sata: "
  455. "Secondary device added\n");
  456. if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
  457. printk(KERN_WARNING "nv_sata: "
  458. "Secondary device removed\n");
  459. return 1;
  460. }
  461. return 0;
  462. }
  463. static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
  464. {
  465. struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
  466. u8 intr_mask;
  467. u8 regval;
  468. pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
  469. regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
  470. pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
  471. writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
  472. intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
  473. intr_mask |= NV_INT_ENABLE_HOTPLUG;
  474. writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
  475. }
  476. static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
  477. {
  478. struct pci_dev *pdev = to_pci_dev(host_set->dev);
  479. u8 intr_mask;
  480. u8 regval;
  481. intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
  482. intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
  483. writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
  484. pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
  485. regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
  486. pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
  487. }
  488. static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
  489. {
  490. u8 intr_status;
  491. intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
  492. // Clear interrupt status.
  493. writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
  494. if (intr_status & NV_INT_STATUS_HOTPLUG) {
  495. if (intr_status & NV_INT_STATUS_PDEV_ADDED)
  496. printk(KERN_WARNING "nv_sata: "
  497. "Primary device added\n");
  498. if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
  499. printk(KERN_WARNING "nv_sata: "
  500. "Primary device removed\n");
  501. if (intr_status & NV_INT_STATUS_SDEV_ADDED)
  502. printk(KERN_WARNING "nv_sata: "
  503. "Secondary device added\n");
  504. if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
  505. printk(KERN_WARNING "nv_sata: "
  506. "Secondary device removed\n");
  507. return 1;
  508. }
  509. return 0;
  510. }
  511. static int __init nv_init(void)
  512. {
  513. return pci_module_init(&nv_pci_driver);
  514. }
  515. static void __exit nv_exit(void)
  516. {
  517. pci_unregister_driver(&nv_pci_driver);
  518. }
  519. module_init(nv_init);
  520. module_exit(nv_exit);