i82092.c 18 KB

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  1. /*
  2. * Driver for Intel I82092AA PCI-PCMCIA bridge.
  3. *
  4. * (C) 2001 Red Hat, Inc.
  5. *
  6. * Author: Arjan Van De Ven <arjanv@redhat.com>
  7. * Loosly based on i82365.c from the pcmcia-cs package
  8. *
  9. * $Id: i82092aa.c,v 1.2 2001/10/23 14:43:34 arjanv Exp $
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/config.h>
  13. #include <linux/module.h>
  14. #include <linux/pci.h>
  15. #include <linux/init.h>
  16. #include <linux/workqueue.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/device.h>
  19. #include <pcmcia/cs_types.h>
  20. #include <pcmcia/ss.h>
  21. #include <pcmcia/cs.h>
  22. #include <asm/system.h>
  23. #include <asm/io.h>
  24. #include "i82092aa.h"
  25. #include "i82365.h"
  26. MODULE_LICENSE("GPL");
  27. /* PCI core routines */
  28. static struct pci_device_id i82092aa_pci_ids[] = {
  29. {
  30. .vendor = PCI_VENDOR_ID_INTEL,
  31. .device = PCI_DEVICE_ID_INTEL_82092AA_0,
  32. .subvendor = PCI_ANY_ID,
  33. .subdevice = PCI_ANY_ID,
  34. },
  35. {}
  36. };
  37. MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
  38. static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state)
  39. {
  40. return pcmcia_socket_dev_suspend(&dev->dev, state);
  41. }
  42. static int i82092aa_socket_resume (struct pci_dev *dev)
  43. {
  44. return pcmcia_socket_dev_resume(&dev->dev);
  45. }
  46. static struct pci_driver i82092aa_pci_drv = {
  47. .name = "i82092aa",
  48. .id_table = i82092aa_pci_ids,
  49. .probe = i82092aa_pci_probe,
  50. .remove = __devexit_p(i82092aa_pci_remove),
  51. .suspend = i82092aa_socket_suspend,
  52. .resume = i82092aa_socket_resume,
  53. };
  54. /* the pccard structure and its functions */
  55. static struct pccard_operations i82092aa_operations = {
  56. .init = i82092aa_init,
  57. .get_status = i82092aa_get_status,
  58. .set_socket = i82092aa_set_socket,
  59. .set_io_map = i82092aa_set_io_map,
  60. .set_mem_map = i82092aa_set_mem_map,
  61. };
  62. /* The card can do upto 4 sockets, allocate a structure for each of them */
  63. struct socket_info {
  64. int number;
  65. int card_state; /* 0 = no socket,
  66. 1 = empty socket,
  67. 2 = card but not initialized,
  68. 3 = operational card */
  69. kio_addr_t io_base; /* base io address of the socket */
  70. struct pcmcia_socket socket;
  71. struct pci_dev *dev; /* The PCI device for the socket */
  72. };
  73. #define MAX_SOCKETS 4
  74. static struct socket_info sockets[MAX_SOCKETS];
  75. static int socket_count; /* shortcut */
  76. static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  77. {
  78. unsigned char configbyte;
  79. int i, ret;
  80. enter("i82092aa_pci_probe");
  81. if ((ret = pci_enable_device(dev)))
  82. return ret;
  83. pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */
  84. switch(configbyte&6) {
  85. case 0:
  86. socket_count = 2;
  87. break;
  88. case 2:
  89. socket_count = 1;
  90. break;
  91. case 4:
  92. case 6:
  93. socket_count = 4;
  94. break;
  95. default:
  96. printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n");
  97. ret = -EIO;
  98. goto err_out_disable;
  99. }
  100. printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count);
  101. if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
  102. ret = -EBUSY;
  103. goto err_out_disable;
  104. }
  105. for (i = 0;i<socket_count;i++) {
  106. sockets[i].card_state = 1; /* 1 = present but empty */
  107. sockets[i].io_base = pci_resource_start(dev, 0);
  108. sockets[i].socket.features |= SS_CAP_PCCARD;
  109. sockets[i].socket.map_size = 0x1000;
  110. sockets[i].socket.irq_mask = 0;
  111. sockets[i].socket.pci_irq = dev->irq;
  112. sockets[i].socket.owner = THIS_MODULE;
  113. sockets[i].number = i;
  114. if (card_present(i)) {
  115. sockets[i].card_state = 3;
  116. dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i);
  117. } else {
  118. dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i);
  119. }
  120. }
  121. /* Now, specifiy that all interrupts are to be done as PCI interrupts */
  122. configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */
  123. pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */
  124. /* Register the interrupt handler */
  125. dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq);
  126. if ((ret = request_irq(dev->irq, i82092aa_interrupt, SA_SHIRQ, "i82092aa", i82092aa_interrupt))) {
  127. printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq);
  128. goto err_out_free_res;
  129. }
  130. pci_set_drvdata(dev, &sockets[i].socket);
  131. for (i = 0; i<socket_count; i++) {
  132. sockets[i].socket.dev.dev = &dev->dev;
  133. sockets[i].socket.ops = &i82092aa_operations;
  134. sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
  135. ret = pcmcia_register_socket(&sockets[i].socket);
  136. if (ret) {
  137. goto err_out_free_sockets;
  138. }
  139. }
  140. leave("i82092aa_pci_probe");
  141. return 0;
  142. err_out_free_sockets:
  143. if (i) {
  144. for (i--;i>=0;i--) {
  145. pcmcia_unregister_socket(&sockets[i].socket);
  146. }
  147. }
  148. free_irq(dev->irq, i82092aa_interrupt);
  149. err_out_free_res:
  150. release_region(pci_resource_start(dev, 0), 2);
  151. err_out_disable:
  152. pci_disable_device(dev);
  153. return ret;
  154. }
  155. static void __devexit i82092aa_pci_remove(struct pci_dev *dev)
  156. {
  157. struct pcmcia_socket *socket = pci_get_drvdata(dev);
  158. enter("i82092aa_pci_remove");
  159. free_irq(dev->irq, i82092aa_interrupt);
  160. if (socket)
  161. pcmcia_unregister_socket(socket);
  162. leave("i82092aa_pci_remove");
  163. }
  164. static DEFINE_SPINLOCK(port_lock);
  165. /* basic value read/write functions */
  166. static unsigned char indirect_read(int socket, unsigned short reg)
  167. {
  168. unsigned short int port;
  169. unsigned char val;
  170. unsigned long flags;
  171. spin_lock_irqsave(&port_lock,flags);
  172. reg += socket * 0x40;
  173. port = sockets[socket].io_base;
  174. outb(reg,port);
  175. val = inb(port+1);
  176. spin_unlock_irqrestore(&port_lock,flags);
  177. return val;
  178. }
  179. #if 0
  180. static unsigned short indirect_read16(int socket, unsigned short reg)
  181. {
  182. unsigned short int port;
  183. unsigned short tmp;
  184. unsigned long flags;
  185. spin_lock_irqsave(&port_lock,flags);
  186. reg = reg + socket * 0x40;
  187. port = sockets[socket].io_base;
  188. outb(reg,port);
  189. tmp = inb(port+1);
  190. reg++;
  191. outb(reg,port);
  192. tmp = tmp | (inb(port+1)<<8);
  193. spin_unlock_irqrestore(&port_lock,flags);
  194. return tmp;
  195. }
  196. #endif
  197. static void indirect_write(int socket, unsigned short reg, unsigned char value)
  198. {
  199. unsigned short int port;
  200. unsigned long flags;
  201. spin_lock_irqsave(&port_lock,flags);
  202. reg = reg + socket * 0x40;
  203. port = sockets[socket].io_base;
  204. outb(reg,port);
  205. outb(value,port+1);
  206. spin_unlock_irqrestore(&port_lock,flags);
  207. }
  208. static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
  209. {
  210. unsigned short int port;
  211. unsigned char val;
  212. unsigned long flags;
  213. spin_lock_irqsave(&port_lock,flags);
  214. reg = reg + socket * 0x40;
  215. port = sockets[socket].io_base;
  216. outb(reg,port);
  217. val = inb(port+1);
  218. val |= mask;
  219. outb(reg,port);
  220. outb(val,port+1);
  221. spin_unlock_irqrestore(&port_lock,flags);
  222. }
  223. static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask)
  224. {
  225. unsigned short int port;
  226. unsigned char val;
  227. unsigned long flags;
  228. spin_lock_irqsave(&port_lock,flags);
  229. reg = reg + socket * 0x40;
  230. port = sockets[socket].io_base;
  231. outb(reg,port);
  232. val = inb(port+1);
  233. val &= ~mask;
  234. outb(reg,port);
  235. outb(val,port+1);
  236. spin_unlock_irqrestore(&port_lock,flags);
  237. }
  238. static void indirect_write16(int socket, unsigned short reg, unsigned short value)
  239. {
  240. unsigned short int port;
  241. unsigned char val;
  242. unsigned long flags;
  243. spin_lock_irqsave(&port_lock,flags);
  244. reg = reg + socket * 0x40;
  245. port = sockets[socket].io_base;
  246. outb(reg,port);
  247. val = value & 255;
  248. outb(val,port+1);
  249. reg++;
  250. outb(reg,port);
  251. val = value>>8;
  252. outb(val,port+1);
  253. spin_unlock_irqrestore(&port_lock,flags);
  254. }
  255. /* simple helper functions */
  256. /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
  257. static int cycle_time = 120;
  258. static int to_cycles(int ns)
  259. {
  260. if (cycle_time!=0)
  261. return ns/cycle_time;
  262. else
  263. return 0;
  264. }
  265. /* Interrupt handler functionality */
  266. static irqreturn_t i82092aa_interrupt(int irq, void *dev, struct pt_regs *regs)
  267. {
  268. int i;
  269. int loopcount = 0;
  270. int handled = 0;
  271. unsigned int events, active=0;
  272. /* enter("i82092aa_interrupt");*/
  273. while (1) {
  274. loopcount++;
  275. if (loopcount>20) {
  276. printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n");
  277. break;
  278. }
  279. active = 0;
  280. for (i=0;i<socket_count;i++) {
  281. int csc;
  282. if (sockets[i].card_state==0) /* Inactive socket, should not happen */
  283. continue;
  284. csc = indirect_read(i,I365_CSC); /* card status change register */
  285. if (csc==0) /* no events on this socket */
  286. continue;
  287. handled = 1;
  288. events = 0;
  289. if (csc & I365_CSC_DETECT) {
  290. events |= SS_DETECT;
  291. printk("Card detected in socket %i!\n",i);
  292. }
  293. if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) {
  294. /* For IO/CARDS, bit 0 means "read the card" */
  295. events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
  296. } else {
  297. /* Check for battery/ready events */
  298. events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
  299. events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
  300. events |= (csc & I365_CSC_READY) ? SS_READY : 0;
  301. }
  302. if (events) {
  303. pcmcia_parse_events(&sockets[i].socket, events);
  304. }
  305. active |= events;
  306. }
  307. if (active==0) /* no more events to handle */
  308. break;
  309. }
  310. return IRQ_RETVAL(handled);
  311. /* leave("i82092aa_interrupt");*/
  312. }
  313. /* socket functions */
  314. static int card_present(int socketno)
  315. {
  316. unsigned int val;
  317. enter("card_present");
  318. if ((socketno<0) || (socketno >= MAX_SOCKETS))
  319. return 0;
  320. if (sockets[socketno].io_base == 0)
  321. return 0;
  322. val = indirect_read(socketno, 1); /* Interface status register */
  323. if ((val&12)==12) {
  324. leave("card_present 1");
  325. return 1;
  326. }
  327. leave("card_present 0");
  328. return 0;
  329. }
  330. static void set_bridge_state(int sock)
  331. {
  332. enter("set_bridge_state");
  333. indirect_write(sock, I365_GBLCTL,0x00);
  334. indirect_write(sock, I365_GENCTL,0x00);
  335. indirect_setbit(sock, I365_INTCTL,0x08);
  336. leave("set_bridge_state");
  337. }
  338. static int i82092aa_init(struct pcmcia_socket *sock)
  339. {
  340. int i;
  341. struct resource res = { .start = 0, .end = 0x0fff };
  342. pccard_io_map io = { 0, 0, 0, 0, 1 };
  343. pccard_mem_map mem = { .res = &res, };
  344. enter("i82092aa_init");
  345. for (i = 0; i < 2; i++) {
  346. io.map = i;
  347. i82092aa_set_io_map(sock, &io);
  348. }
  349. for (i = 0; i < 5; i++) {
  350. mem.map = i;
  351. i82092aa_set_mem_map(sock, &mem);
  352. }
  353. leave("i82092aa_init");
  354. return 0;
  355. }
  356. static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
  357. {
  358. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  359. unsigned int status;
  360. enter("i82092aa_get_status");
  361. status = indirect_read(sock,I365_STATUS); /* Interface Status Register */
  362. *value = 0;
  363. if ((status & I365_CS_DETECT) == I365_CS_DETECT) {
  364. *value |= SS_DETECT;
  365. }
  366. /* IO cards have a different meaning of bits 0,1 */
  367. /* Also notice the inverse-logic on the bits */
  368. if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
  369. /* IO card */
  370. if (!(status & I365_CS_STSCHG))
  371. *value |= SS_STSCHG;
  372. } else { /* non I/O card */
  373. if (!(status & I365_CS_BVD1))
  374. *value |= SS_BATDEAD;
  375. if (!(status & I365_CS_BVD2))
  376. *value |= SS_BATWARN;
  377. }
  378. if (status & I365_CS_WRPROT)
  379. (*value) |= SS_WRPROT; /* card is write protected */
  380. if (status & I365_CS_READY)
  381. (*value) |= SS_READY; /* card is not busy */
  382. if (status & I365_CS_POWERON)
  383. (*value) |= SS_POWERON; /* power is applied to the card */
  384. leave("i82092aa_get_status");
  385. return 0;
  386. }
  387. static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state)
  388. {
  389. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  390. unsigned char reg;
  391. enter("i82092aa_set_socket");
  392. /* First, set the global controller options */
  393. set_bridge_state(sock);
  394. /* Values for the IGENC register */
  395. reg = 0;
  396. if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */
  397. reg = reg | I365_PC_RESET;
  398. if (state->flags & SS_IOCARD)
  399. reg = reg | I365_PC_IOCARD;
  400. indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */
  401. /* Power registers */
  402. reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
  403. if (state->flags & SS_PWR_AUTO) {
  404. printk("Auto power\n");
  405. reg |= I365_PWR_AUTO; /* automatic power mngmnt */
  406. }
  407. if (state->flags & SS_OUTPUT_ENA) {
  408. printk("Power Enabled \n");
  409. reg |= I365_PWR_OUT; /* enable power */
  410. }
  411. switch (state->Vcc) {
  412. case 0:
  413. break;
  414. case 50:
  415. printk("setting voltage to Vcc to 5V on socket %i\n",sock);
  416. reg |= I365_VCC_5V;
  417. break;
  418. default:
  419. printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc);
  420. leave("i82092aa_set_socket");
  421. return -EINVAL;
  422. }
  423. switch (state->Vpp) {
  424. case 0:
  425. printk("not setting Vpp on socket %i\n",sock);
  426. break;
  427. case 50:
  428. printk("setting Vpp to 5.0 for socket %i\n",sock);
  429. reg |= I365_VPP1_5V | I365_VPP2_5V;
  430. break;
  431. case 120:
  432. printk("setting Vpp to 12.0\n");
  433. reg |= I365_VPP1_12V | I365_VPP2_12V;
  434. break;
  435. default:
  436. printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc);
  437. leave("i82092aa_set_socket");
  438. return -EINVAL;
  439. }
  440. if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */
  441. indirect_write(sock,I365_POWER,reg);
  442. /* Enable specific interrupt events */
  443. reg = 0x00;
  444. if (state->csc_mask & SS_DETECT) {
  445. reg |= I365_CSC_DETECT;
  446. }
  447. if (state->flags & SS_IOCARD) {
  448. if (state->csc_mask & SS_STSCHG)
  449. reg |= I365_CSC_STSCHG;
  450. } else {
  451. if (state->csc_mask & SS_BATDEAD)
  452. reg |= I365_CSC_BVD1;
  453. if (state->csc_mask & SS_BATWARN)
  454. reg |= I365_CSC_BVD2;
  455. if (state->csc_mask & SS_READY)
  456. reg |= I365_CSC_READY;
  457. }
  458. /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/
  459. indirect_write(sock,I365_CSCINT,reg);
  460. (void)indirect_read(sock,I365_CSC);
  461. leave("i82092aa_set_socket");
  462. return 0;
  463. }
  464. static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io)
  465. {
  466. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  467. unsigned char map, ioctl;
  468. enter("i82092aa_set_io_map");
  469. map = io->map;
  470. /* Check error conditions */
  471. if (map > 1) {
  472. leave("i82092aa_set_io_map with invalid map");
  473. return -EINVAL;
  474. }
  475. if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){
  476. leave("i82092aa_set_io_map with invalid io");
  477. return -EINVAL;
  478. }
  479. /* Turn off the window before changing anything */
  480. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
  481. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
  482. /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */
  483. /* write the new values */
  484. indirect_write16(sock,I365_IO(map)+I365_W_START,io->start);
  485. indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop);
  486. ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map);
  487. if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
  488. ioctl |= I365_IOCTL_16BIT(map);
  489. indirect_write(sock,I365_IOCTL,ioctl);
  490. /* Turn the window back on if needed */
  491. if (io->flags & MAP_ACTIVE)
  492. indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map));
  493. leave("i82092aa_set_io_map");
  494. return 0;
  495. }
  496. static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem)
  497. {
  498. struct socket_info *sock_info = container_of(socket, struct socket_info, socket);
  499. unsigned int sock = sock_info->number;
  500. struct pci_bus_region region;
  501. unsigned short base, i;
  502. unsigned char map;
  503. enter("i82092aa_set_mem_map");
  504. pcibios_resource_to_bus(sock_info->dev, &region, mem->res);
  505. map = mem->map;
  506. if (map > 4) {
  507. leave("i82092aa_set_mem_map: invalid map");
  508. return -EINVAL;
  509. }
  510. if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) ||
  511. (mem->speed > 1000) ) {
  512. leave("i82092aa_set_mem_map: invalid address / speed");
  513. printk("invalid mem map for socket %i : %lx to %lx with a start of %x \n",sock,region.start, region.end, mem->card_start);
  514. return -EINVAL;
  515. }
  516. /* Turn off the window before changing anything */
  517. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
  518. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  519. /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */
  520. /* write the start address */
  521. base = I365_MEM(map);
  522. i = (region.start >> 12) & 0x0fff;
  523. if (mem->flags & MAP_16BIT)
  524. i |= I365_MEM_16BIT;
  525. if (mem->flags & MAP_0WS)
  526. i |= I365_MEM_0WS;
  527. indirect_write16(sock,base+I365_W_START,i);
  528. /* write the stop address */
  529. i= (region.end >> 12) & 0x0fff;
  530. switch (to_cycles(mem->speed)) {
  531. case 0:
  532. break;
  533. case 1:
  534. i |= I365_MEM_WS0;
  535. break;
  536. case 2:
  537. i |= I365_MEM_WS1;
  538. break;
  539. default:
  540. i |= I365_MEM_WS1 | I365_MEM_WS0;
  541. break;
  542. }
  543. indirect_write16(sock,base+I365_W_STOP,i);
  544. /* card start */
  545. i = ((mem->card_start - region.start) >> 12) & 0x3fff;
  546. if (mem->flags & MAP_WRPROT)
  547. i |= I365_MEM_WRPROT;
  548. if (mem->flags & MAP_ATTRIB) {
  549. /* printk("requesting attribute memory for socket %i\n",sock);*/
  550. i |= I365_MEM_REG;
  551. } else {
  552. /* printk("requesting normal memory for socket %i\n",sock);*/
  553. }
  554. indirect_write16(sock,base+I365_W_OFF,i);
  555. /* Enable the window if necessary */
  556. if (mem->flags & MAP_ACTIVE)
  557. indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  558. leave("i82092aa_set_mem_map");
  559. return 0;
  560. }
  561. static int i82092aa_module_init(void)
  562. {
  563. enter("i82092aa_module_init");
  564. pci_register_driver(&i82092aa_pci_drv);
  565. leave("i82092aa_module_init");
  566. return 0;
  567. }
  568. static void i82092aa_module_exit(void)
  569. {
  570. enter("i82092aa_module_exit");
  571. pci_unregister_driver(&i82092aa_pci_drv);
  572. if (sockets[0].io_base>0)
  573. release_region(sockets[0].io_base, 2);
  574. leave("i82092aa_module_exit");
  575. }
  576. module_init(i82092aa_module_init);
  577. module_exit(i82092aa_module_exit);