au1550nd.c 11 KB

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  1. /*
  2. * drivers/mtd/nand/au1550nd.c
  3. *
  4. * Copyright (C) 2004 Embedded Edge, LLC
  5. *
  6. * $Id: au1550nd.c,v 1.13 2005/11/07 11:14:30 gleixner Exp $
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/slab.h>
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/nand.h>
  18. #include <linux/mtd/partitions.h>
  19. #include <linux/version.h>
  20. #include <asm/io.h>
  21. /* fixme: this is ugly */
  22. #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
  23. #include <asm/mach-au1x00/au1xxx.h>
  24. #else
  25. #include <asm/au1000.h>
  26. #ifdef CONFIG_MIPS_PB1550
  27. #include <asm/pb1550.h>
  28. #endif
  29. #ifdef CONFIG_MIPS_DB1550
  30. #include <asm/db1x00.h>
  31. #endif
  32. #endif
  33. /*
  34. * MTD structure for NAND controller
  35. */
  36. static struct mtd_info *au1550_mtd = NULL;
  37. static void __iomem *p_nand;
  38. static int nand_width = 1; /* default x8*/
  39. /*
  40. * Define partitions for flash device
  41. */
  42. static const struct mtd_partition partition_info[] = {
  43. {
  44. .name = "NAND FS 0",
  45. .offset = 0,
  46. .size = 8*1024*1024
  47. },
  48. {
  49. .name = "NAND FS 1",
  50. .offset = MTDPART_OFS_APPEND,
  51. .size = MTDPART_SIZ_FULL
  52. }
  53. };
  54. #define NB_OF(x) (sizeof(x)/sizeof(x[0]))
  55. /**
  56. * au_read_byte - read one byte from the chip
  57. * @mtd: MTD device structure
  58. *
  59. * read function for 8bit buswith
  60. */
  61. static u_char au_read_byte(struct mtd_info *mtd)
  62. {
  63. struct nand_chip *this = mtd->priv;
  64. u_char ret = readb(this->IO_ADDR_R);
  65. au_sync();
  66. return ret;
  67. }
  68. /**
  69. * au_write_byte - write one byte to the chip
  70. * @mtd: MTD device structure
  71. * @byte: pointer to data byte to write
  72. *
  73. * write function for 8it buswith
  74. */
  75. static void au_write_byte(struct mtd_info *mtd, u_char byte)
  76. {
  77. struct nand_chip *this = mtd->priv;
  78. writeb(byte, this->IO_ADDR_W);
  79. au_sync();
  80. }
  81. /**
  82. * au_read_byte16 - read one byte endianess aware from the chip
  83. * @mtd: MTD device structure
  84. *
  85. * read function for 16bit buswith with
  86. * endianess conversion
  87. */
  88. static u_char au_read_byte16(struct mtd_info *mtd)
  89. {
  90. struct nand_chip *this = mtd->priv;
  91. u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
  92. au_sync();
  93. return ret;
  94. }
  95. /**
  96. * au_write_byte16 - write one byte endianess aware to the chip
  97. * @mtd: MTD device structure
  98. * @byte: pointer to data byte to write
  99. *
  100. * write function for 16bit buswith with
  101. * endianess conversion
  102. */
  103. static void au_write_byte16(struct mtd_info *mtd, u_char byte)
  104. {
  105. struct nand_chip *this = mtd->priv;
  106. writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
  107. au_sync();
  108. }
  109. /**
  110. * au_read_word - read one word from the chip
  111. * @mtd: MTD device structure
  112. *
  113. * read function for 16bit buswith without
  114. * endianess conversion
  115. */
  116. static u16 au_read_word(struct mtd_info *mtd)
  117. {
  118. struct nand_chip *this = mtd->priv;
  119. u16 ret = readw(this->IO_ADDR_R);
  120. au_sync();
  121. return ret;
  122. }
  123. /**
  124. * au_write_word - write one word to the chip
  125. * @mtd: MTD device structure
  126. * @word: data word to write
  127. *
  128. * write function for 16bit buswith without
  129. * endianess conversion
  130. */
  131. static void au_write_word(struct mtd_info *mtd, u16 word)
  132. {
  133. struct nand_chip *this = mtd->priv;
  134. writew(word, this->IO_ADDR_W);
  135. au_sync();
  136. }
  137. /**
  138. * au_write_buf - write buffer to chip
  139. * @mtd: MTD device structure
  140. * @buf: data buffer
  141. * @len: number of bytes to write
  142. *
  143. * write function for 8bit buswith
  144. */
  145. static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  146. {
  147. int i;
  148. struct nand_chip *this = mtd->priv;
  149. for (i=0; i<len; i++) {
  150. writeb(buf[i], this->IO_ADDR_W);
  151. au_sync();
  152. }
  153. }
  154. /**
  155. * au_read_buf - read chip data into buffer
  156. * @mtd: MTD device structure
  157. * @buf: buffer to store date
  158. * @len: number of bytes to read
  159. *
  160. * read function for 8bit buswith
  161. */
  162. static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  163. {
  164. int i;
  165. struct nand_chip *this = mtd->priv;
  166. for (i=0; i<len; i++) {
  167. buf[i] = readb(this->IO_ADDR_R);
  168. au_sync();
  169. }
  170. }
  171. /**
  172. * au_verify_buf - Verify chip data against buffer
  173. * @mtd: MTD device structure
  174. * @buf: buffer containing the data to compare
  175. * @len: number of bytes to compare
  176. *
  177. * verify function for 8bit buswith
  178. */
  179. static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
  180. {
  181. int i;
  182. struct nand_chip *this = mtd->priv;
  183. for (i=0; i<len; i++) {
  184. if (buf[i] != readb(this->IO_ADDR_R))
  185. return -EFAULT;
  186. au_sync();
  187. }
  188. return 0;
  189. }
  190. /**
  191. * au_write_buf16 - write buffer to chip
  192. * @mtd: MTD device structure
  193. * @buf: data buffer
  194. * @len: number of bytes to write
  195. *
  196. * write function for 16bit buswith
  197. */
  198. static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
  199. {
  200. int i;
  201. struct nand_chip *this = mtd->priv;
  202. u16 *p = (u16 *) buf;
  203. len >>= 1;
  204. for (i=0; i<len; i++) {
  205. writew(p[i], this->IO_ADDR_W);
  206. au_sync();
  207. }
  208. }
  209. /**
  210. * au_read_buf16 - read chip data into buffer
  211. * @mtd: MTD device structure
  212. * @buf: buffer to store date
  213. * @len: number of bytes to read
  214. *
  215. * read function for 16bit buswith
  216. */
  217. static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
  218. {
  219. int i;
  220. struct nand_chip *this = mtd->priv;
  221. u16 *p = (u16 *) buf;
  222. len >>= 1;
  223. for (i=0; i<len; i++) {
  224. p[i] = readw(this->IO_ADDR_R);
  225. au_sync();
  226. }
  227. }
  228. /**
  229. * au_verify_buf16 - Verify chip data against buffer
  230. * @mtd: MTD device structure
  231. * @buf: buffer containing the data to compare
  232. * @len: number of bytes to compare
  233. *
  234. * verify function for 16bit buswith
  235. */
  236. static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
  237. {
  238. int i;
  239. struct nand_chip *this = mtd->priv;
  240. u16 *p = (u16 *) buf;
  241. len >>= 1;
  242. for (i=0; i<len; i++) {
  243. if (p[i] != readw(this->IO_ADDR_R))
  244. return -EFAULT;
  245. au_sync();
  246. }
  247. return 0;
  248. }
  249. static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
  250. {
  251. register struct nand_chip *this = mtd->priv;
  252. switch(cmd){
  253. case NAND_CTL_SETCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; break;
  254. case NAND_CTL_CLRCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; break;
  255. case NAND_CTL_SETALE: this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; break;
  256. case NAND_CTL_CLRALE:
  257. this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
  258. /* FIXME: Nobody knows why this is neccecary,
  259. * but it works only that way */
  260. udelay(1);
  261. break;
  262. case NAND_CTL_SETNCE:
  263. /* assert (force assert) chip enable */
  264. au_writel((1<<(4+NAND_CS)) , MEM_STNDCTL); break;
  265. break;
  266. case NAND_CTL_CLRNCE:
  267. /* deassert chip enable */
  268. au_writel(0, MEM_STNDCTL); break;
  269. break;
  270. }
  271. this->IO_ADDR_R = this->IO_ADDR_W;
  272. /* Drain the writebuffer */
  273. au_sync();
  274. }
  275. int au1550_device_ready(struct mtd_info *mtd)
  276. {
  277. int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
  278. au_sync();
  279. return ret;
  280. }
  281. /*
  282. * Main initialization routine
  283. */
  284. int __init au1xxx_nand_init (void)
  285. {
  286. struct nand_chip *this;
  287. u16 boot_swapboot = 0; /* default value */
  288. int retval;
  289. u32 mem_staddr;
  290. u32 nand_phys;
  291. /* Allocate memory for MTD device structure and private data */
  292. au1550_mtd = kmalloc (sizeof(struct mtd_info) +
  293. sizeof (struct nand_chip), GFP_KERNEL);
  294. if (!au1550_mtd) {
  295. printk ("Unable to allocate NAND MTD dev structure.\n");
  296. return -ENOMEM;
  297. }
  298. /* Get pointer to private data */
  299. this = (struct nand_chip *) (&au1550_mtd[1]);
  300. /* Initialize structures */
  301. memset((char *) au1550_mtd, 0, sizeof(struct mtd_info));
  302. memset((char *) this, 0, sizeof(struct nand_chip));
  303. /* Link the private data with the MTD structure */
  304. au1550_mtd->priv = this;
  305. /* disable interrupts */
  306. au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
  307. /* disable NAND boot */
  308. au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
  309. #ifdef CONFIG_MIPS_PB1550
  310. /* set gpio206 high */
  311. au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR);
  312. boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) |
  313. ((bcsr->status >> 6) & 0x1);
  314. switch (boot_swapboot) {
  315. case 0:
  316. case 2:
  317. case 8:
  318. case 0xC:
  319. case 0xD:
  320. /* x16 NAND Flash */
  321. nand_width = 0;
  322. break;
  323. case 1:
  324. case 9:
  325. case 3:
  326. case 0xE:
  327. case 0xF:
  328. /* x8 NAND Flash */
  329. nand_width = 1;
  330. break;
  331. default:
  332. printk("Pb1550 NAND: bad boot:swap\n");
  333. retval = -EINVAL;
  334. goto outmem;
  335. }
  336. #endif
  337. /* Configure chip-select; normally done by boot code, e.g. YAMON */
  338. #ifdef NAND_STCFG
  339. if (NAND_CS == 0) {
  340. au_writel(NAND_STCFG, MEM_STCFG0);
  341. au_writel(NAND_STTIME, MEM_STTIME0);
  342. au_writel(NAND_STADDR, MEM_STADDR0);
  343. }
  344. if (NAND_CS == 1) {
  345. au_writel(NAND_STCFG, MEM_STCFG1);
  346. au_writel(NAND_STTIME, MEM_STTIME1);
  347. au_writel(NAND_STADDR, MEM_STADDR1);
  348. }
  349. if (NAND_CS == 2) {
  350. au_writel(NAND_STCFG, MEM_STCFG2);
  351. au_writel(NAND_STTIME, MEM_STTIME2);
  352. au_writel(NAND_STADDR, MEM_STADDR2);
  353. }
  354. if (NAND_CS == 3) {
  355. au_writel(NAND_STCFG, MEM_STCFG3);
  356. au_writel(NAND_STTIME, MEM_STTIME3);
  357. au_writel(NAND_STADDR, MEM_STADDR3);
  358. }
  359. #endif
  360. /* Locate NAND chip-select in order to determine NAND phys address */
  361. mem_staddr = 0x00000000;
  362. if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
  363. mem_staddr = au_readl(MEM_STADDR0);
  364. else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
  365. mem_staddr = au_readl(MEM_STADDR1);
  366. else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
  367. mem_staddr = au_readl(MEM_STADDR2);
  368. else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
  369. mem_staddr = au_readl(MEM_STADDR3);
  370. if (mem_staddr == 0x00000000) {
  371. printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
  372. kfree(au1550_mtd);
  373. return 1;
  374. }
  375. nand_phys = (mem_staddr << 4) & 0xFFFC0000;
  376. p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
  377. /* make controller and MTD agree */
  378. if (NAND_CS == 0)
  379. nand_width = au_readl(MEM_STCFG0) & (1<<22);
  380. if (NAND_CS == 1)
  381. nand_width = au_readl(MEM_STCFG1) & (1<<22);
  382. if (NAND_CS == 2)
  383. nand_width = au_readl(MEM_STCFG2) & (1<<22);
  384. if (NAND_CS == 3)
  385. nand_width = au_readl(MEM_STCFG3) & (1<<22);
  386. /* Set address of hardware control function */
  387. this->hwcontrol = au1550_hwcontrol;
  388. this->dev_ready = au1550_device_ready;
  389. /* 30 us command delay time */
  390. this->chip_delay = 30;
  391. this->eccmode = NAND_ECC_SOFT;
  392. this->options = NAND_NO_AUTOINCR;
  393. if (!nand_width)
  394. this->options |= NAND_BUSWIDTH_16;
  395. this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
  396. this->write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
  397. this->write_word = au_write_word;
  398. this->read_word = au_read_word;
  399. this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
  400. this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
  401. this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
  402. /* Scan to find existence of the device */
  403. if (nand_scan (au1550_mtd, 1)) {
  404. retval = -ENXIO;
  405. goto outio;
  406. }
  407. /* Register the partitions */
  408. add_mtd_partitions(au1550_mtd, partition_info, NB_OF(partition_info));
  409. return 0;
  410. outio:
  411. iounmap ((void *)p_nand);
  412. outmem:
  413. kfree (au1550_mtd);
  414. return retval;
  415. }
  416. module_init(au1xxx_nand_init);
  417. /*
  418. * Clean up routine
  419. */
  420. #ifdef MODULE
  421. static void __exit au1550_cleanup (void)
  422. {
  423. struct nand_chip *this = (struct nand_chip *) &au1550_mtd[1];
  424. /* Release resources, unregister device */
  425. nand_release (au1550_mtd);
  426. /* Free the MTD device structure */
  427. kfree (au1550_mtd);
  428. /* Unmap */
  429. iounmap ((void *)p_nand);
  430. }
  431. module_exit(au1550_cleanup);
  432. #endif
  433. MODULE_LICENSE("GPL");
  434. MODULE_AUTHOR("Embedded Edge, LLC");
  435. MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");