ucb1x00.h 6.7 KB

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  1. /*
  2. * linux/drivers/mfd/ucb1x00.h
  3. *
  4. * Copyright (C) 2001 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. */
  10. #ifndef UCB1200_H
  11. #define UCB1200_H
  12. #define UCB_IO_DATA 0x00
  13. #define UCB_IO_DIR 0x01
  14. #define UCB_IO_0 (1 << 0)
  15. #define UCB_IO_1 (1 << 1)
  16. #define UCB_IO_2 (1 << 2)
  17. #define UCB_IO_3 (1 << 3)
  18. #define UCB_IO_4 (1 << 4)
  19. #define UCB_IO_5 (1 << 5)
  20. #define UCB_IO_6 (1 << 6)
  21. #define UCB_IO_7 (1 << 7)
  22. #define UCB_IO_8 (1 << 8)
  23. #define UCB_IO_9 (1 << 9)
  24. #define UCB_IE_RIS 0x02
  25. #define UCB_IE_FAL 0x03
  26. #define UCB_IE_STATUS 0x04
  27. #define UCB_IE_CLEAR 0x04
  28. #define UCB_IE_ADC (1 << 11)
  29. #define UCB_IE_TSPX (1 << 12)
  30. #define UCB_IE_TSMX (1 << 13)
  31. #define UCB_IE_TCLIP (1 << 14)
  32. #define UCB_IE_ACLIP (1 << 15)
  33. #define UCB_IRQ_TSPX 12
  34. #define UCB_TC_A 0x05
  35. #define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
  36. #define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
  37. #define UCB_TC_B 0x06
  38. #define UCB_TC_B_VOICE_ENA (1 << 3)
  39. #define UCB_TC_B_CLIP (1 << 4)
  40. #define UCB_TC_B_ATT (1 << 6)
  41. #define UCB_TC_B_SIDE_ENA (1 << 11)
  42. #define UCB_TC_B_MUTE (1 << 13)
  43. #define UCB_TC_B_IN_ENA (1 << 14)
  44. #define UCB_TC_B_OUT_ENA (1 << 15)
  45. #define UCB_AC_A 0x07
  46. #define UCB_AC_B 0x08
  47. #define UCB_AC_B_LOOP (1 << 8)
  48. #define UCB_AC_B_MUTE (1 << 13)
  49. #define UCB_AC_B_IN_ENA (1 << 14)
  50. #define UCB_AC_B_OUT_ENA (1 << 15)
  51. #define UCB_TS_CR 0x09
  52. #define UCB_TS_CR_TSMX_POW (1 << 0)
  53. #define UCB_TS_CR_TSPX_POW (1 << 1)
  54. #define UCB_TS_CR_TSMY_POW (1 << 2)
  55. #define UCB_TS_CR_TSPY_POW (1 << 3)
  56. #define UCB_TS_CR_TSMX_GND (1 << 4)
  57. #define UCB_TS_CR_TSPX_GND (1 << 5)
  58. #define UCB_TS_CR_TSMY_GND (1 << 6)
  59. #define UCB_TS_CR_TSPY_GND (1 << 7)
  60. #define UCB_TS_CR_MODE_INT (0 << 8)
  61. #define UCB_TS_CR_MODE_PRES (1 << 8)
  62. #define UCB_TS_CR_MODE_POS (2 << 8)
  63. #define UCB_TS_CR_BIAS_ENA (1 << 11)
  64. #define UCB_TS_CR_TSPX_LOW (1 << 12)
  65. #define UCB_TS_CR_TSMX_LOW (1 << 13)
  66. #define UCB_ADC_CR 0x0a
  67. #define UCB_ADC_SYNC_ENA (1 << 0)
  68. #define UCB_ADC_VREFBYP_CON (1 << 1)
  69. #define UCB_ADC_INP_TSPX (0 << 2)
  70. #define UCB_ADC_INP_TSMX (1 << 2)
  71. #define UCB_ADC_INP_TSPY (2 << 2)
  72. #define UCB_ADC_INP_TSMY (3 << 2)
  73. #define UCB_ADC_INP_AD0 (4 << 2)
  74. #define UCB_ADC_INP_AD1 (5 << 2)
  75. #define UCB_ADC_INP_AD2 (6 << 2)
  76. #define UCB_ADC_INP_AD3 (7 << 2)
  77. #define UCB_ADC_EXT_REF (1 << 5)
  78. #define UCB_ADC_START (1 << 7)
  79. #define UCB_ADC_ENA (1 << 15)
  80. #define UCB_ADC_DATA 0x0b
  81. #define UCB_ADC_DAT_VAL (1 << 15)
  82. #define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
  83. #define UCB_ID 0x0c
  84. #define UCB_ID_1200 0x1004
  85. #define UCB_ID_1300 0x1005
  86. #define UCB_MODE 0x0d
  87. #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
  88. #define UCB_MODE_AUD_OFF_CAN (1 << 13)
  89. #include "mcp.h"
  90. struct ucb1x00_irq {
  91. void *devid;
  92. void (*fn)(int, void *);
  93. };
  94. struct ucb1x00 {
  95. spinlock_t lock;
  96. struct mcp *mcp;
  97. unsigned int irq;
  98. struct semaphore adc_sem;
  99. spinlock_t io_lock;
  100. u16 id;
  101. u16 io_dir;
  102. u16 io_out;
  103. u16 adc_cr;
  104. u16 irq_fal_enbl;
  105. u16 irq_ris_enbl;
  106. struct ucb1x00_irq irq_handler[16];
  107. struct class_device cdev;
  108. struct list_head node;
  109. struct list_head devs;
  110. };
  111. struct ucb1x00_driver;
  112. struct ucb1x00_dev {
  113. struct list_head dev_node;
  114. struct list_head drv_node;
  115. struct ucb1x00 *ucb;
  116. struct ucb1x00_driver *drv;
  117. void *priv;
  118. };
  119. struct ucb1x00_driver {
  120. struct list_head node;
  121. struct list_head devs;
  122. int (*add)(struct ucb1x00_dev *dev);
  123. void (*remove)(struct ucb1x00_dev *dev);
  124. int (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
  125. int (*resume)(struct ucb1x00_dev *dev);
  126. };
  127. #define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, cdev)
  128. int ucb1x00_register_driver(struct ucb1x00_driver *);
  129. void ucb1x00_unregister_driver(struct ucb1x00_driver *);
  130. /**
  131. * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
  132. * @ucb: UCB1x00 structure describing chip
  133. *
  134. * Return the SIB clock rate in Hz.
  135. */
  136. static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
  137. {
  138. return mcp_get_sclk_rate(ucb->mcp);
  139. }
  140. /**
  141. * ucb1x00_enable - enable the UCB1x00 SIB clock
  142. * @ucb: UCB1x00 structure describing chip
  143. *
  144. * Enable the SIB clock. This can be called multiple times.
  145. */
  146. static inline void ucb1x00_enable(struct ucb1x00 *ucb)
  147. {
  148. mcp_enable(ucb->mcp);
  149. }
  150. /**
  151. * ucb1x00_disable - disable the UCB1x00 SIB clock
  152. * @ucb: UCB1x00 structure describing chip
  153. *
  154. * Disable the SIB clock. The SIB clock will only be disabled
  155. * when the number of ucb1x00_enable calls match the number of
  156. * ucb1x00_disable calls.
  157. */
  158. static inline void ucb1x00_disable(struct ucb1x00 *ucb)
  159. {
  160. mcp_disable(ucb->mcp);
  161. }
  162. /**
  163. * ucb1x00_reg_write - write a UCB1x00 register
  164. * @ucb: UCB1x00 structure describing chip
  165. * @reg: UCB1x00 4-bit register index to write
  166. * @val: UCB1x00 16-bit value to write
  167. *
  168. * Write the UCB1x00 register @reg with value @val. The SIB
  169. * clock must be running for this function to return.
  170. */
  171. static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
  172. {
  173. mcp_reg_write(ucb->mcp, reg, val);
  174. }
  175. /**
  176. * ucb1x00_reg_read - read a UCB1x00 register
  177. * @ucb: UCB1x00 structure describing chip
  178. * @reg: UCB1x00 4-bit register index to write
  179. *
  180. * Read the UCB1x00 register @reg and return its value. The SIB
  181. * clock must be running for this function to return.
  182. */
  183. static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
  184. {
  185. return mcp_reg_read(ucb->mcp, reg);
  186. }
  187. /**
  188. * ucb1x00_set_audio_divisor -
  189. * @ucb: UCB1x00 structure describing chip
  190. * @div: SIB clock divisor
  191. */
  192. static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
  193. {
  194. mcp_set_audio_divisor(ucb->mcp, div);
  195. }
  196. /**
  197. * ucb1x00_set_telecom_divisor -
  198. * @ucb: UCB1x00 structure describing chip
  199. * @div: SIB clock divisor
  200. */
  201. static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
  202. {
  203. mcp_set_telecom_divisor(ucb->mcp, div);
  204. }
  205. void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
  206. void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
  207. unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
  208. #define UCB_NOSYNC (0)
  209. #define UCB_SYNC (1)
  210. unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
  211. void ucb1x00_adc_enable(struct ucb1x00 *ucb);
  212. void ucb1x00_adc_disable(struct ucb1x00 *ucb);
  213. /*
  214. * Which edges of the IRQ do you want to control today?
  215. */
  216. #define UCB_RISING (1 << 0)
  217. #define UCB_FALLING (1 << 1)
  218. int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
  219. void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
  220. void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
  221. int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
  222. #endif